KR100292387B1 - Trench manufacturing method for semiconductor device isolation - Google Patents
Trench manufacturing method for semiconductor device isolation Download PDFInfo
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- KR100292387B1 KR100292387B1 KR1019980043623A KR19980043623A KR100292387B1 KR 100292387 B1 KR100292387 B1 KR 100292387B1 KR 1019980043623 A KR1019980043623 A KR 1019980043623A KR 19980043623 A KR19980043623 A KR 19980043623A KR 100292387 B1 KR100292387 B1 KR 100292387B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Abstract
반도체 소자의 분리를 위한 트랜치 제조 방법에 관한 것으로, 트랜치를 매립한 산화막 위에 감광막을 도포하고, 감광막과 산화물의 식각율 선택비를 1 : 1 로 하여 산화막이 두께 0.3 내지 0.7 ㎛ 정도로 남도록 건식 에치 백(dry etch back) 공정에 의해 어느 정도 평탄화하고, 산화막을 포토리소그래피 공정에 의해 식각한 후, 화학 기계적 연마 공정을 함으로써, 화학 기계적 연마 공정시 산화막 모서리의 각진 부분이 깨져 엑티브 영역이나 필드 영역에 흠집을 발생시키며, 파티클 소스로 작용하여 공정 오차를 발생하는 것을 방지함으로써, 수율을 향상시킬 뿐만 아니라 소자의 신뢰성을 향상시킨다.A trench manufacturing method for isolation of a semiconductor device, the method comprising: applying a photoresist film on an oxide film having a trench embedded therein, and having an etch rate selectivity between the photoresist film and an oxide of 1: 1, so that the oxide film remains about 0.3 to 0.7 탆 thick. (planarized to some extent by a dry etch back process, the oxide film is etched by a photolithography process, and then subjected to a chemical mechanical polishing process, whereby the angled portions of the edges of the oxide film are broken during the chemical mechanical polishing process, and the active or field regions are scratched. By preventing the occurrence of process errors by acting as a particle source, not only improves the yield but also improves the reliability of the device.
Description
본 발명은 반도체 소자 분리 방법에 관한 것으로, 더욱 상세하게는 반도체 소자 분리를 위한 트랜치를 제조하는 방법에 관한 것이다.The present invention relates to a semiconductor device isolation method, and more particularly, to a method for manufacturing a trench for semiconductor device isolation.
일반적으로 반도체 소자 분리 방법으로 LOCOS(local oxidation of silicon) 소자 분리가 이용되어 왔다. LOCOS는 질화막을 마스크로 해서 실리콘 웨이퍼 자체를 열산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막질이 좋다는 큰 이점이 있다.In general, local oxidation of silicon (LOCOS) device isolation has been used as a semiconductor device isolation method. Since LOCOS thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple, and there is a big advantage that the element stress problem of the oxide film is small, and that the resulting oxide film quality is good.
그러나 LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 차지하는 면적이 크기 때문에 미세화에 한계가 있을 뿐만 아니라 버즈 비크(bird's beak)가 발생한다.However, when the LOCOS device isolation method occupies a large area of the device isolation region, there is a limitation in miniaturization and a bird's beak occurs.
이러한 것을 극복하기 위해 LOCOS를 대체하는 소자 분리 기술로서 트랜치 소자 분리가 있다.To overcome this, trench isolation is a device isolation technology that replaces LOCOS.
트랜치 소자 분리 방법은 반응성 이온 에칭(RIE ; reactive ion etching)이나 플라즈마 에칭과 같은 건식 에칭 기술을 사용하여 좁고 깊은 트랜치를 만들고, 그 속에 산화막을 채우는 방법으로 실리콘 웨이퍼에 트랜치를 만들어 절연물을 집어넣기 때문에 버즈 비크와 관련된 문제가 없어진다. 또한, 채워진 트랜치는 표면을 평탄하게 하므로 소자 분리 영역이 차지하는 면적이 작아서 미세화에 유리한 방법이다.The trench isolation method uses a dry etching technique such as reactive ion etching (RIE) or plasma etching to form a narrow, deep trench, and fills an insulator by trenching the silicon wafer by filling an oxide film therein. The problem with Buzz Beek is eliminated. In addition, since the filled trench is flat, the area occupied by the device isolation region is small, which is advantageous for miniaturization.
그러면, 반도체 소자 분리를 위한 트랜치를 제조하는 종래의 방법을 첨부된 도 1a 내지 도 1c를 참조하여 설명한다.Then, a conventional method for manufacturing a trench for semiconductor device isolation will be described with reference to FIGS. 1A-1C.
먼저, 도 1a에 도시한 바와 같이 실리콘 웨이퍼(1)를 열산화하여 150Å 정도의 두께로 패드 산화막(2)을 열성장시키고, 그 상부에 화학 기상 증착법(CVD ; chemical vapor deposition)에 의해 2000Å 정도의 두께로 질화막(3)을 증착한다. 그리고, 포토리소그래피(photolithography) 공정에 의해 질화막(3)과 패드 산화막(2)을 선택적으로 식각하여 제거하고, 드러난 실리콘 웨이퍼(1)를 일정 깊이로 식각하여 실리콘 웨이퍼(1)의 소자 분리 영역에 트랜치(4)를 형성한다. 이후, 트랜치(4)가 형성된 실리콘 웨이퍼(1)를 세정하고, 트랜치(4)의 소자 분리 특성을 강화하기 위하여 실리콘 웨이퍼(1)를 열산화하여 트랜치(4)의 내벽에 270Å 정도의 두께로 라이너(liner) 산화막(5)을 성장시킨다.First, as shown in FIG. 1A, the silicon wafer 1 is thermally oxidized to thermally grow the pad oxide film 2 to a thickness of about 150 GPa, and about 2000 GPa is deposited on the upper portion thereof by chemical vapor deposition (CVD). The nitride film 3 is deposited to a thickness of. Then, the nitride film 3 and the pad oxide film 2 are selectively etched and removed by a photolithography process, and the exposed silicon wafer 1 is etched to a predetermined depth to the device isolation region of the silicon wafer 1. Form the trench 4. Thereafter, the silicon wafer 1 having the trenches 4 formed thereon is cleaned, and the silicon wafer 1 is thermally oxidized in order to enhance the device isolation characteristics of the trenches 4 so as to have a thickness of about 270 mm on the inner wall of the trenches 4. The liner oxide film 5 is grown.
그 다음, 도 1b에 도시한 바와 같이 실리콘 웨이퍼(1) 전면에 상압 화학 기상 증착법(APCVD ; atmospheric pressure chemical vapor deposition)에 의해 산화막(6)을 두껍게 증착하여 트랜치(4)를 매립하고, 1000℃ 정도의 온도로 어닐링하여 트랜치(4)에 매립된 산화막(6)을 고밀도화(densify) 시킨다. 그리고, 포토리소그래피 공정에 의해 산화막(6)을 선택적으로 식각하여 실리콘 웨이퍼(1)의 트랜치(4) 영역 및 그 상부에만 산화막(6)이 남도록 한다.Next, as illustrated in FIG. 1B, the oxide film 6 is thickly deposited by APCVD (atmospheric pressure chemical vapor deposition) on the entire surface of the silicon wafer 1 to fill the trench 4, and the trench 4 is filled at 1000 ° C. Annealing at an appropriate temperature densify the oxide film 6 embedded in the trench 4. The oxide film 6 is selectively etched by the photolithography process so that the oxide film 6 remains only in the trench 4 region and the upper portion of the silicon wafer 1.
이후, 도 1c에 도시한 바와 같이 화학 기계적 연마(CMP ; chemical mechanical polishing) 공정에 의해 산화막(6)의 상부가 질화막(3) 상부와 평행이 되도록 평탄화하여 반도체 소자 분리를 위한 트랜치를 완성한다.Thereafter, as illustrated in FIG. 1C, the upper portion of the oxide layer 6 is planarized to be parallel to the upper portion of the nitride layer 3 by a chemical mechanical polishing (CMP) process, thereby completing a trench for semiconductor device isolation.
이와 같이 종래의 방법으로 반도체 소자 분리를 위한 트랜치를 제조하면 도 1b에서와 같이 포토리소그래피 공정에 의해 산화막을 패터닝한 경우, 패턴화된 산화막 상부 모서리 부분(도 1b의 7)이 각진 형태로 된다. 이 상태에서 화학 기계적 연마 공정에 의해 패턴화된 산화막을 평탄화할 경우, 이 각진 모서리 부분이 취약하여 연마 공정 중에 떨어져 나가 파티클 소스(particle source)로 작용하여 트랜치 영역의 산화막에 흠집(scratch)을 유발시킴으로써 후속 공정에서 단차에 의한 폴리 스트링거(poly stringer) 문제를 유발시키며, 심한 경우에는 엑티브 영역의 질화막(3)과 패드 산화막(2), 그리고 실리콘 웨이퍼(1)에 까지 흠집을 유발시켜 공정상의 오차를 발생함과 아울러 그에 따라 소자의 수율 및 신뢰성을 저하시키게 된다.As described above, when the trench for semiconductor device isolation is manufactured by the conventional method, when the oxide film is patterned by the photolithography process as shown in FIG. 1B, the upper edge portion of the patterned oxide film (7 in FIG. 1B) is angled. In this state, when the oxide film patterned by the chemical mechanical polishing process is planarized, the angular corner portions are fragile and fall off during the polishing process to act as a particle source, causing scratches on the oxide film in the trench region. This causes a poly stringer problem due to a step in a subsequent step, and in severe cases, scratches on the nitride layer 3, the pad oxide layer 2, and the silicon wafer 1 in the active region. In addition to this, the yield and reliability of the device are lowered accordingly.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 반도체 소자 분리를 위한 트랜치 제조 공정에서 화학 기계적 연마 공정 중에 트랜치 산화막 패턴의 상부 각진 모서리가 떨어져 나가 엑티브 영역이나 필드 영역의 흠집을 발생시키며, 파티클 소스로 작용하는 것을 방지하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to generate a scratch of an active region or a field region by falling off an upper angled corner of a trench oxide pattern during a chemical mechanical polishing process in a trench fabrication process for semiconductor device isolation. To prevent it from acting as a particle source.
도 1a 내지 도 1c는 종래의 반도체 소자 분리를 위한 트랜치를 제조하는 방법을 도시한 공정도이고,1A to 1C are process diagrams illustrating a method of manufacturing a trench for separating a conventional semiconductor device,
도 2a 내지 도 2e는 본 발명의 일 실시예에 따라 반도체 소자 분리를 위한 트랜치를 제조하는 방법을 도시한 공정도이다.2A through 2E are flowcharts illustrating a method of manufacturing a trench for semiconductor device isolation according to an embodiment of the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 트랜치를 매립한 산화막을 어느 정도 평탄하게 하여, 포토리소그래피 공정에 의해 산화막을 패터닝하는 경우 트랜치 산화막 패턴의 상부 각진 모서리 부분이 생기지 않도록 한 후, 화학 기계적 연마 공정을 하는 것을 특징으로 한다.In order to achieve the above object, the present invention is to flatten the oxide buried in the trench to some extent, so that when the oxide film is patterned by a photolithography process, the upper angled corner portion of the trench oxide pattern is not formed, and then the chemical mechanical It is characterized by performing a polishing process.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 일 실시예에 따른 반도체 소자 분리를 위한 트랜치를 제조하는 방법을 공정 순서에 따라 도시한 실리콘 웨이퍼의 단면도이다.2A through 2E are cross-sectional views of silicon wafers in a process sequence illustrating a method of manufacturing a trench for semiconductor device isolation according to an embodiment of the present invention.
먼저, 도 2a에 도시한 바와 같이 실리콘 웨이퍼(11)를 열산화하여 후속 공정에서 형성될 질화막과 실리콘 웨이퍼 사이에 발생하는 스트레스를 흡수하기 위한 패드 산화막(12)을 150Å 정도의 두께로 성장시키고, 그 상부에 화학 기상 증착법으로 질화막(13)을 2000Å 정도의 두께로 증착한다. 그리고, 패드 산화막(12)과 질화막(13)이 형성된 실리콘 웨이퍼(11) 상에 감광막을 도포하고, 트랜치 패턴이 형성된 마스크를 통해 감광막을 노광 현상하여 감광막 패턴을 형성한다. 이 후에, 감광막 패턴을 마스크로 하여 플라즈마 건식 식각 방법을 이용하여 질화막(13)과 패드 산화막(12)을 식각하여 제거하고, 드러난 실리콘 웨이퍼(11)를 일정 깊이로 식각하여 소자 분리 영역을 트랜치(14)로 형성한다. 그리고, 남은 감광막 패턴을 제거하고, 실리콘 웨이퍼(11)를 세정한 후, 트랜치(14)의 소자 분리 특성을 강화하기 위하여 실리콘 웨이퍼(11)를 열산화하여 트랜치(14)의 내벽에 라이너 산화막(15)을 270Å 정도의 두께로 성장시킨다.First, as shown in FIG. 2A, the silicon oxide film 11 is thermally oxidized to grow a pad oxide film 12 to absorb a stress generated between the nitride film and the silicon wafer to be formed in a subsequent process to a thickness of about 150 kPa. The nitride film 13 is deposited to a thickness of about 2000 kPa on the top thereof by chemical vapor deposition. Then, a photoresist film is coated on the silicon wafer 11 on which the pad oxide film 12 and the nitride film 13 are formed, and the photoresist film is exposed to light through a mask on which a trench pattern is formed to form a photoresist film pattern. Thereafter, the nitride film 13 and the pad oxide film 12 are etched and removed using the plasma dry etching method using the photoresist pattern as a mask, and the exposed silicon wafer 11 is etched to a predetermined depth to form a trench in the device isolation region. 14). After the remaining photoresist pattern is removed, the silicon wafer 11 is cleaned, and the silicon wafer 11 is thermally oxidized to enhance the device isolation characteristics of the trench 14. 15) is grown to a thickness of about 270Å.
그 다음, 도 2b에 도시한 바와 같이 실리콘 웨이퍼(11) 전면에 상압 화학 기상 증착법에 의해 산화막(16)을 두껍게 증착하여 트랜치(14)를 매립하고, 1000℃ 정도의 온도로 어닐링하여 트랜치(14)에 매립된 산화막(16)을 고밀도화 시킨다. 그리고, 산화막(16) 상부에 평탄화될 정도로 0.3 내지 1.5 ㎛ 정도의 두께로 감광막(17)을 도포한다.Next, as shown in FIG. 2B, the oxide film 16 is thickly deposited on the entire surface of the silicon wafer 11 by atmospheric pressure chemical vapor deposition, and the trench 14 is buried, and the trench 14 is annealed at a temperature of about 1000 ° C. The oxide film 16 embedded in the C) is densified. Then, the photosensitive film 17 is applied to a thickness of about 0.3 to 1.5 μm so as to be flattened on the oxide film 16.
그 다음, 도 2c에 도시한 바와 같이 감광막(17)과 산화막(16)의 식각율 선택비(etch rate selectivity)를 1 : 1 로 하고 탄소(C) 등을 식각 가스로 한 건식 에치 백(dry etch back)을 통해 감광막(17)과 산화막(16)을 식각하여 엑티브 영역 즉, 질화막(13) 상부의 산화막(16)의 두께가 0.3 내지 0.7 ㎛로 되도록 평탄화한다. 이때, 식각 정지점인 EOP(end of point)는 원하는 박막만을 식각시키기 위해 다른 박막이 드러날 때 플라즈마 분위기가 변하는 점으로 한다. 분위기가 변하는 점은 빛의 굴절 또는 가스의 파장으로 감지하는 데, 건식 에치 백에서 사용된 탄소와 탄화수소 화합물(CH) 가스의 파장을 이용하여 EOP를 결정하여 산화막(16)의 식각을 정지한다.Next, as illustrated in FIG. 2C, a dry etch bag having an etch rate selectivity of the photosensitive film 17 and the oxide film 16 as 1: 1 and carbon (C) as an etching gas is used. The photoresist film 17 and the oxide film 16 are etched through the etch back to planarize the active region, that is, the thickness of the oxide film 16 on the nitride film 13 to be 0.3 to 0.7 μm. In this case, the end point of EOP (EOP) is a point where the plasma atmosphere changes when another thin film is exposed to etch only a desired thin film. The change in the atmosphere is detected by the refraction of light or the wavelength of the gas. The EOP is determined using the wavelengths of the carbon and hydrocarbon compound (CH) gas used in the dry etch bag to stop the etching of the oxide layer 16.
그 다음, 도 2d에 도시한 바와 같이 산화막(16) 위에 감광막(18)을 도포하고, 트랜치 패턴과 반대 패턴이 형성된 리버스 마스크를 통해 감광막(18)을 노광 현상하여 감광막 패턴(18)을 형성한다. 그리고, 감광막 패턴(18)을 마스크로 하여 질화막(13)을 식각 정지막으로 산화막(16)을 식각함으로써 트랜치 영역 및 그 상부에만 산화막(16)이 남도록 한다. 이때, 도 2c에서와 같이 산화막(16)의 상부가 어느 정도 평탄화된 상태에서 식각을 하므로 종래와는 달리 트랜치 산화막 패턴의 상부 각진 모서리 부분이 생기지 않아(19), 후속 화학 기계적 연마 공정에서 모서리 부분이 떨어져 나가 파티클 소스로 작용하는 것을 방지한다.Next, as illustrated in FIG. 2D, the photosensitive film 18 is coated on the oxide film 16, and the photosensitive film 18 is exposed and developed through a reverse mask in which a pattern opposite to the trench pattern is formed to form the photosensitive film pattern 18. . The oxide film 16 is etched in the trench region and the upper portion by etching the oxide film 16 using the nitride film 13 as an etch stop film using the photosensitive film pattern 18 as a mask. At this time, since the upper portion of the oxide film 16 is etched to some extent as shown in FIG. 2C, unlike the conventional method, the upper angled corner portion of the trench oxide pattern does not occur (19), and thus, the edge portion in the subsequent chemical mechanical polishing process. This prevents it from falling out and acting as a particle source.
그 다음, 그림 2e에 도시한 바와 같이 마스크로 사용되었던 감광막(18)을 제거하고, 화학 기계적 연마 공정에 의해 산화막(16)의 상부가 질화막(13) 상부와 평행이 되도록 평탄화하여 반도체 소자 분리를 위한 트랜치를 완성한다.Then, as shown in Fig. 2E, the photoresist film 18 used as a mask is removed, and the semiconductor device is separated by planarizing the upper portion of the oxide film 16 in parallel with the upper nitride film 13 by a chemical mechanical polishing process. Complete the trench for
이와 같이 본 발명은 반도체 소자 분리를 위한 트랜치 제조 공정에서 트랜치 산화막 패턴의 상부 각진 모서리 부분(8)이 생기지 않도록 하여 화학 기계적 연마 공정시 깨어진 산화막 조각이 파티클 소스로 작용하여 공정 오차를 발생하는 것을 방지함으로써, 수율을 향상시킬 뿐만 아니라 소자의 신뢰성을 향상시킨다.As such, the present invention prevents the upper angular corner portion 8 of the trench oxide pattern from being formed in the trench fabrication process for semiconductor device isolation, thereby preventing the broken oxide fragment from acting as a particle source during the chemical mechanical polishing process to generate a process error. This improves the yield and improves the reliability of the device.
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