KR100315442B1 - Shallow trench manufacture method for isolating semiconductor devices - Google Patents
Shallow trench manufacture method for isolating semiconductor devices Download PDFInfo
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- KR100315442B1 KR100315442B1 KR1019990006525A KR19990006525A KR100315442B1 KR 100315442 B1 KR100315442 B1 KR 100315442B1 KR 1019990006525 A KR1019990006525 A KR 1019990006525A KR 19990006525 A KR19990006525 A KR 19990006525A KR 100315442 B1 KR100315442 B1 KR 100315442B1
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 238000002955 isolation Methods 0.000 claims abstract description 25
- 150000004767 nitrides Chemical class 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000007517 polishing process Methods 0.000 claims abstract description 13
- 239000000126 substance Substances 0.000 claims abstract description 13
- 238000001312 dry etching Methods 0.000 claims abstract description 7
- 238000011065 in-situ storage Methods 0.000 claims abstract description 5
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 62
- 235000012431 wafers Nutrition 0.000 description 20
- 238000005498 polishing Methods 0.000 description 10
- 239000007789 gas Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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Abstract
반도체 소자 분리를 위한 트렌치 제조 공정에서 화학 기계적 연마 공정 중에 트렌치 산화막 패턴의 상부 각진 모서리가 떨어져 나가 액티브 지역이나 필드 지역의 흠집을 발생시키며 파티클 소스로 작용하는 것을 방지할 뿐만 아니라 장시간의 화학 기계적 연마 공정에 의해 질화막이 과도하게 연마되는 것을 방지하기 위한 것으로, 트렌치가 형성된 실리콘웨이퍼 전면에 절연막을 두껍게 증착한 후, 감광막을 도포하고 건식 에치 백하여 절연막의 두께를 얇게 한다. 그리고, 건식 식각에 의한 이방성 식각으로 절연막을 패터닝한 후, 인 시투 공정에 의한 등방성 식각을 하여 패터닝된 절연막의 상부 에지를 라운딩되게 한 후, 감광막을 제거하고, 화학 기계적 연마 공정에 의해 평탄화하여 반도체 소자 분리를 위한 얕은 트렌치를 완성한다.In the trench fabrication process for semiconductor device isolation, the upper angular corners of the trench oxide pattern may fall off during the chemical mechanical polishing process, causing scratches in the active area or the field area and preventing the particle from acting as a particle source. In order to prevent the nitride film from being excessively polished, a thick insulating film is deposited on the entire surface of the silicon wafer on which the trench is formed, and then the photosensitive film is coated and dry etched back to reduce the thickness of the insulating film. After the insulating film is patterned by anisotropic etching by dry etching, isotropic etching is performed by in-situ process to round the upper edge of the patterned insulating film, and then the photoresist film is removed and flattened by a chemical mechanical polishing process. Complete the shallow trench for device isolation.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 더욱 상세하게는 반도체 소자 제조 공정중 반도체 소자와 소자 사이를 전기적으로 격리하기 위한 얕은 트렌치를 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a shallow trench for electrically isolating between a semiconductor device and the device during the semiconductor device manufacturing process.
일반적으로 반도체 소자 분리 방법으로 LOCOS(local oxidation of silicon) 소자 분리가 이용되어 왔다. LOCOS는 질화막을 마스크로 해서 실리콘웨이퍼 자체를 열산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막질이 좋다는 큰 이점이 있다.In general, local oxidation of silicon (LOCOS) device isolation has been used as a semiconductor device isolation method. Since LOCOS thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple, so there is a great advantage that the element stress problem of the oxide film is small, and the oxide film quality is good.
그러나, LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 차지하는 면적이 크기 때문에 미세화에 한계가 있을 뿐만 아니라 버즈 비크(bird's beak)가 발생한다.However, when the LOCOS device isolation method is used, the area occupied by the device isolation region is not only limited in miniaturization but also causes bird's beak.
이러한 것을 극복하기 위해 LOCOS를 대체하는 소자 분리 기술로서 트렌치 소자 분리가 있다.To overcome this, trench isolation is a device isolation technology that replaces LOCOS.
트렌치 소자 분리 방법은 반응성 이온 식각(RIE ; reactive ion etching)이나 플라즈마 식각과 같은 건식 식각 기술을 사용하여 좁고 깊은 트렌치를 만들고, 그 속에 잘연막을 채우는 방법으로, 실리콘웨이퍼에 트렌치를 만들어 절연물을 집어 넣기 때문에 버즈 비크와 관련된 문제가 없어진다. 또한, 절연막이 채워진 트렌치는 표면을 평탄하게 하므로 소자 분리 영역이 차지하는 면적이 작아서 미세화에 유리한 방법이다.The trench isolation method uses dry etching techniques such as reactive ion etching (RIE) or plasma etching to form narrow and deep trenches, and fills the well with smoke. This eliminates the problems associated with Buzz Beek. In addition, since the trench filled with the insulating film is flattened, the area occupied by the device isolation region is small, which is advantageous for miniaturization.
그러면, 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 종래의 방법을 첨부된 도 1a 내지 도 1c를 참조하여 설명한다.A conventional method of manufacturing a shallow trench for semiconductor device isolation is then described with reference to FIGS. 1A-1C.
먼저, 도 1a에 도시한 바와 같이, 실리콘웨이퍼(1)를 열산화하여 150Å 정도의 두께로 패드 산화막(2)을 열성장시키고, 그 상부에 2000Å 정도의 두께로 질화막(3)을 증착한다. 그리고, 트렌치 패턴이 형성된 마스크를 이용하여 질화막(3)과 패드 산화막(2)을 선택적으로 식각하여 제거하고, 드러난 실리콘웨이퍼(1)를 일정 깊이로 식각하여 실리콘웨이퍼(1)의 소자 분리 영역에 트렌치(4)를 형성한다. 이후, 트렌치(4)가 형성된 실리콘웨이퍼(1)를 세정하고, 트렌치(4)의 소자 분리 특성을 강화하기 위하여 질화막(3)을 마스크로 실리콘웨이퍼(1)를 열산화하여 트렌치(4)의 내벽에 270Å 정도의 두께로 라이너(liner) 산화막(5)을 성장시킨다.First, as shown in FIG. 1A, the silicon wafer 1 is thermally oxidized to thermally grow the pad oxide film 2 to a thickness of about 150 GPa, and the nitride film 3 is deposited to a thickness of about 2000 GPa on top thereof. The nitride film 3 and the pad oxide film 2 are selectively etched and removed using a mask on which a trench pattern is formed, and the exposed silicon wafer 1 is etched to a predetermined depth to the device isolation region of the silicon wafer 1. The trench 4 is formed. Subsequently, the silicon wafer 1 having the trench 4 formed therein is cleaned, and the silicon wafer 1 is thermally oxidized using the nitride film 3 as a mask to enhance the device isolation characteristics of the trench 4. On the inner wall, a liner oxide film 5 is grown to a thickness of about 270 Å.
그 다음, 도 1b에 도시한 바와 같이, 실리콘웨이퍼(1) 전면에 상압 화학 기상 증착법(APCVD ; atmospheric pressure chemical vapor deposition)에 의해 불순물이 도핑되지 않은 산화막에 의한 절연막(6)을 8500Å 내지 11000Å 정도의 두께로 증착하여 트렌치를 완전히 매립하고, 1000℃ 정도의 온도로 어닐링(annealing)하여 트렌치에 매립된 절연막(6)을 고밀도화(densify)시킨다. 그리고, 트렌치 패턴과 반대 패턴이 형성된 리벌스(reverse) 마스크를 이용한 포토리소그래피 공정에 의해 절연막(6)을 이방성 건식 식각하여 트렌치 영역 이외의 액티브 영역(반도체 소자 영역) 상부 즉, 질화막(3) 상부의 절연막을 제거한 후, 실리콘웨이퍼(1) 전면을 세정한다.Next, as shown in FIG. 1B, an insulating film 6 made of an oxide film which is not doped with impurities by atmospheric pressure chemical vapor deposition (APCVD) on the entire surface of the silicon wafer 1 is about 8500 kPa to 11000 kPa. The trench is completely deposited, and the trench is completely filled, and the trench is annealed at a temperature of about 1000 ° C. to densify the insulating film 6 embedded in the trench. Then, the insulating film 6 is anisotropically dry-etched by a photolithography process using a reverse mask in which a pattern opposite to the trench pattern is formed, and the upper portion of the active region (semiconductor element region) other than the trench region, that is, the upper portion of the nitride layer 3 After the insulating film was removed, the entire surface of the silicon wafer 1 was cleaned.
이후, 도 1c에 도시한 바와 같이, 화학 기계적 연마(CMP ; chemical mechanical polishing) 공정에 의해 절연막(6)의 상부가 질화막(3) 상부와 평행이 되도록 평탄화함으로써 반도체 소자 분리를 위한 얕은 트렌치를 완성한다.Thereafter, as illustrated in FIG. 1C, a shallow trench for semiconductor device isolation is completed by planarizing the upper portion of the insulating layer 6 to be parallel to the upper portion of the nitride layer 3 by a chemical mechanical polishing (CMP) process. do.
이와 같이 반도체 소자 분리를 위한 얕은 트렌치를 종래의 방법으로 제조할 경우, 도 1b에서와 같이 리벌스 패터닝에 의해 건식 식각된 절연막의 상부 모서리 부분(7)이 각진 형태로 된다. 이 상태에서 화학 기계적 연마 공정에 의해 절연막을 평탄화하면, 이 각진 모서리 부분이 취약하여 연마 공정 중에 떨어져 나가 파티클 소스(particle source)로 작용함으로써 트렌치 영역이나 액티브 영역에 스크래치(scratch)를 유발하여 후속 공정에서 단차에 의한 폴리 스트링거(poly stringer) 문제를 유발시키며, 심한 경우에는 액티브 영역의 질화막과 패드 산화막, 그리고 실리콘 웨이퍼에 까지 스크래치를 유발시켜 공정상의 오차를 발생함과아울러 그에 따라 소자의 수율 및 신뢰성을 저하시키게 된다.As described above, when the shallow trench for semiconductor device isolation is manufactured by the conventional method, as shown in FIG. 1B, the upper edge portion 7 of the dry-etched insulating film formed by the regression patterning becomes angular. In this state, when the insulating film is flattened by a chemical mechanical polishing process, the angular corner portions become weak and fall off during the polishing process to act as a particle source, causing scratches in the trench region or the active region, and subsequent processes. Step by step causes poly stringer problems and, in severe cases, scratches on the nitride, pad oxide, and silicon wafers in the active region, resulting in process errors as well as device yield and reliability. Will lower.
그리고, 화학 기게적 연마 공정시 패턴의 밀도가 조밀한 지역과 희박한 지역 사이의 연마율 차이에 의해, 패턴이 조밀한 지역을 기준으로 연마를 할 경우에는 패턴이 희박한 지역에서 질화막의 과도 식각으로 액티브 영역의 실리콘웨이퍼를 손상시킬 수 있고, 패턴이 희박한 지역을 기준으로 연마를 할 경우에는 패턴이 조밀한 지역에서 절연막이 완전히 제거되지 않고 남아 후속 습식 식각 공정에 의해 질화막을 제거시 질화막이 남게되는 문제점이 있다. 또한, 화학 기계적 연마 공정시 평탄화해야 할 산화막이 두꺼운 경우에는 장시간의 연마에 의해 질화막이 과도하게 연마되어 액티브 영역의 실리콘웨이퍼에 손상을 유발시키게 된다.In the chemical mechanical polishing process, due to the difference in the polishing rate between the areas with dense and sparse patterns, when the polishing is performed based on areas with dense patterns, the active layer is excessively etched in the region where the pattern is thin. If the silicon wafer in the region is damaged and the polishing is performed based on the region where the pattern is thin, the insulating layer is not completely removed in the region where the pattern is dense, and the nitride layer remains when the nitride layer is removed by the subsequent wet etching process. There is this. In addition, when the oxide film to be planarized in the chemical mechanical polishing process is thick, the nitride film is excessively polished by prolonged polishing, causing damage to the silicon wafer in the active region.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 반도체 소자 분리를 위한 트렌치 제조 공정에서 화학 기계적 연마 공정 중에 트렌치 산화막 패턴의 상부 각진 모서리가 떨어져 나가 액티브 지역이나 필드 지역의 흠집을 발생시키며 파티클 소스로 작용하는 것을 방지할 뿐만 아니라 장시간의 화학 기계적 연마 공정에 의해 질화막이 과도하게 연마되는 것을 방지하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is that the upper angled corners of the trench oxide pattern may fall off during the chemical mechanical polishing process in the trench fabrication process for semiconductor device isolation, causing scratches in the active region or the field region. In addition to preventing the source from acting as a source, the nitride film is prevented from being excessively polished by a long time chemical mechanical polishing process.
도 1a 내지 도 1c는 종래의 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 방법을 도시한 공정도이고,1A to 1C are process diagrams illustrating a method of manufacturing a shallow trench for separating a conventional semiconductor device,
도 2a 내지 도 2e는 본 발명의 일 실시예에 따라 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 방법을 도시한 공정도이다.2A-2E are process diagrams illustrating a method of manufacturing a shallow trench for semiconductor device isolation in accordance with one embodiment of the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 트렌치를 매입하기 위한 절연막의 증착 후, 감광막을 도포하고 건식 에치 백하여 절연막의 두께를 얇게 하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that after the deposition of the insulating film for embedding the trench, the photosensitive film is coated and dry etched back to reduce the thickness of the insulating film.
또한, 본 발명은 절연막의 패터닝시, 건식 식각에 의한 이방성 식각으로 절연막을 패터닝한 후, 인 시투 공정에 의한 등방성 식각을 하여 패터닝된 절연막의 상부 에지를 라운딩되게 하는 것을 특징으로 한다.In addition, the present invention is characterized in that during the patterning of the insulating film, the insulating film is patterned by anisotropic etching by dry etching, and then isotropically etched by an in-situ process to round the upper edge of the patterned insulating film.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 일 실시예에 따른 반도체 소자 분리를 위한 트렌치를 제조하는 방법을 공정 순서에 따라 도시한 실리콘웨이퍼의 단면도이다.2A to 2E are cross-sectional views of silicon wafers in a process sequence illustrating a method of manufacturing a trench for semiconductor device isolation in accordance with an embodiment of the present invention.
먼저, 도 2a에 도시한 바와 같이, 실리콘웨이퍼(11)를 열산화하여 후속 공정에서 형성될 질화막과 실리콘웨이퍼 사이에 발생하는 스트레스를 흡수하기 위한 패드 산화막(12)을 150Å 정도의 두께로 성장시키고, 그 상부에 질화막(13)을 2000Å 정도의 두께로 증착한다. 그리고, 질화막(13)과 패드 산화막(12)이 형성된 실리콘웨이퍼(11) 전면에 감광막을 도포하고, 트렌치 패턴이 형성된 마스크를 통해 노광 현상하여 트렌치 형성을 위한 감광막 패턴을 형성한다. 이 후, 감광막 패턴을 마스크로 건식 식각에 의해 드러난 질화막(13)과 패드 산화막(12)을 식각하여 제거하고, 다시 드러난 실리콘웨이퍼(11)를 일정 깊이로 식각하여 반도체 소자 분리 영역을 트렌치(14)로 형성한다(포토리소그래피 공정 ; photolithography). 그리고, 감광막 패턴을 제거하고 실리콘웨이퍼(11)를 세정한 후, 트렌치(14)의 소자 분리 특성을 강화하기 위하여 실리콘웨이퍼(11)를 열산화하여 트렌치(14)의 내벽에 270Å 정도의 두께로 라이너 산화막(15)을 성장시킨다.First, as shown in FIG. 2A, the silicon oxide 11 is thermally oxidized to grow a pad oxide layer 12 to absorb a stress generated between the nitride film and the silicon wafer to be formed in a subsequent process to a thickness of about 150 GPa. Then, a nitride film 13 is deposited on the upper portion with a thickness of about 2000 mW. Then, a photosensitive film is coated on the entire surface of the silicon wafer 11 having the nitride film 13 and the pad oxide film 12 formed thereon, and exposed to light through a mask on which the trench pattern is formed to form a photosensitive film pattern for forming a trench. Subsequently, the nitride film 13 and the pad oxide film 12 exposed by dry etching are removed using the photoresist pattern as a mask, and the exposed silicon wafer 11 is etched to a predetermined depth to trench the semiconductor device isolation region 14. ) (Photolithography step; photolithography). After removing the photoresist pattern and cleaning the silicon wafer 11, the silicon wafer 11 is thermally oxidized in order to enhance device isolation characteristics of the trench 14 to a thickness of about 270 에 on the inner wall of the trench 14. The liner oxide film 15 is grown.
그 다음, 도 2b에 도시한 바와 같이, 실리콘웨이퍼(11) 전면에 상압 화학 기상 증착법에 의해 절연막(16)을 8500Å 내지 11000Å 정도의 두께로 두껍게 증착하여 트렌치를 매립하고, 1000℃ 정도의 온도로 어닐링하여 트렌치에 매립된 절연막(16)을 고밀도화시킨다. 그리고, 절연막(16) 상부에 평탄화될 정도의 두께, 바람직하게는 3000Å 내지 15000Å 정도의 두께로 감광막(17)을 도포한다.Next, as shown in FIG. 2B, the insulating film 16 is thickly deposited to a thickness of about 8500 kPa to about 11000 kPa by the atmospheric pressure chemical vapor deposition method on the entire surface of the silicon wafer 11 to fill the trench, and the temperature is about 1000 ° C. Annealing to densify the insulating film 16 embedded in the trench. Then, the photosensitive film 17 is coated on the insulating film 16 to a thickness that is planarized, preferably about 3000 to 15000 mm.
그 다음, 도 2c에 도시한 바와 같이, 감광막(17)과 절연막(16)의 식각비가 1:1이 되도록 건식 에치 백(dry etch back)을 통해 감광막(17)과 절연막(16)을 식각한다. 이때, 건식 에치 백에서의 식각 정지점(EOP ; end of point)은 원하는 박막만을 식각시키기 위해 다른 박막이 드러날 때 식각 분위기가 변하는 점으로 하며, 분위기가 변화는 점의 가스 파장으로 감지하는 데, 건식 에치 백에서 사용된 탄소(C)와 탄화수소(CH) 화합물 가스의 파장으로 식각 정지점을 결정하여 절연막(16)의 식각을 정지함으로써, 질화막(3) 상부의 남은 절연막(16)이 평탄화되도록 하며, 바람직하게는 남은 절연막(16)의 두께가 3000Å 내지 5000Å이 되도록 평탄화한다. 그리고, 남은 감광막을 제거하고 실리콘웨이퍼(11) 전면을 세정한다.Next, as shown in FIG. 2C, the photosensitive film 17 and the insulating film 16 are etched through a dry etch back such that the etching ratio of the photosensitive film 17 and the insulating film 16 is 1: 1. . In this case, the end point of etching (EOP) in the dry etch bag is a point where the etching atmosphere changes when another thin film is exposed to etch only a desired thin film, and the atmosphere is detected by the gas wavelength of the point. The etch stop point is determined by the wavelengths of the carbon (C) and hydrocarbon (CH) compound gases used in the dry etch bag to stop the etching of the insulating film 16 so that the remaining insulating film 16 on the nitride film 3 is planarized. Preferably, the thickness of the remaining insulating film 16 is set to be 3000 kPa to 5000 kPa. Then, the remaining photoresist film is removed and the entire surface of the silicon wafer 11 is cleaned.
그 다음, 도 2d에 도시한 바와 같이, 평탄화된 절연막(16) 상부에 감광막을 도포하고, 트렌치 패턴과 반대 패턴이 형성된 리벌스 마스크를 통해 감광막을 노광 현상하여 트렌치 영역 상부에만 감광막이 남도록 감광막 패턴(18)을 형성한다. 이후, 감광막 패턴(18)을 마스크로 건식 식각에 의한 이방성 식각으로 드러난 절연막(16)을 식각하여 패터닝한다. 이때, 절연막(16)의 이방성 식각 정지점은 탄화질소(CN) 가스의 파장으로 결정하여 질화막(13)에서 식각을 멈춘다. 그리고, 인 시투(IN-SITU) 공정에 의한 등방성 식각으로 감광막 패턴(18)의 측면을 식각하여 감광막 패턴(18)의 폭을 일정 길이(20) 만큼 줄임과 동시에 절연막(16) 패턴의 상부 에지 부분(19)을 라운딩시킨다. 이때, 등방성 식각 공정에서 산소 가스를 과도하게 공급하여 감광막 패턴의 측면 식각을 활성화시킨다.Next, as shown in FIG. 2D, a photoresist film is coated on the planarized insulating film 16, and the photoresist film is exposed and developed through a rival mask formed with a pattern opposite to the trench pattern so that the photoresist film remains only on the trench region. (18) is formed. Subsequently, the insulating film 16 exposed by the anisotropic etching by dry etching is patterned by using the photoresist pattern 18 as a mask. At this time, the anisotropic etching stop point of the insulating film 16 is determined by the wavelength of the nitrogen carbide (CN) gas to stop the etching in the nitride film (13). Then, the side surface of the photoresist pattern 18 is etched by isotropic etching by an IN-SITU process to reduce the width of the photoresist pattern 18 by a predetermined length 20 and at the same time the upper edge of the insulation layer 16 pattern. Round the part 19. At this time, the oxygen gas is excessively supplied in the isotropic etching process to activate the side etching of the photoresist pattern.
그 다음, 도 2e에 도시한 바와 같이, 감광막 패턴을 제거하고, 실리콘웨이퍼(11)를 세정한 후, 화학 기계적 연마 공정에 의해 절연막(16)을 평탄화함으로써 반도체 소자 분리를 위한 얕은 트렌치를 완성한다. 이때, 종래와 달리, 절연막(16) 상부 에지 부분이 라운딩되어 있으므로 화학 기계 연마 공정 중에 상부 에지 부분이 떨어져 나가 파티클 소스로 작용하는 것을 방지할 수 있으며, 절연막(16)의 두께가 얇기 때문에 패턴이 조밀한 지역과 희박한 지역에서의 연마율이 거의 동일하게 되므로 질화막의 과도 연마뿐만 아니라 부족 연마에 의해 액티브 영역에 질화막이 남는 등의 문제를 미연에 방지할 수 있다.Next, as shown in FIG. 2E, the photoresist pattern is removed, the silicon wafer 11 is cleaned, and the insulating film 16 is planarized by a chemical mechanical polishing process to complete a shallow trench for semiconductor device isolation. . At this time, unlike the prior art, since the upper edge portion of the insulating layer 16 is rounded, it is possible to prevent the upper edge portion from falling off and acting as a particle source during the chemical mechanical polishing process, and the pattern of the insulating layer 16 is thin. Since the polishing rates in the dense and sparse regions are almost the same, problems such as over-polishing of the nitride film and leaving the nitride film in the active region due to insufficient polishing can be prevented in advance.
이와 같이 본 발명은 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 공정에서 트렌치를 매입하는 절연막 패턴의 화학 기계적 연마 공정 이전에 절연막 패턴의 상부 에지 부분을 라운딩되게 함으로써 절연막 조각이 깨어져 파티클 소스로 작용하는 것을 방지할 수 있을 뿐만 아니라 절연막 패턴의 두께를 얇게 한 다음 화학 기계적 연마 공정을 실시하므로 패턴 밀도에 의한 연마율 차이에 의해 질화막의 과도 연마나 부족 연마가 발생하는 것을 방지할 수 있어 공정 수율 및 반ㄷ체 소자의 신뢰성을 향상시킬 수 있다.As described above, the present invention is to make the upper edge portion of the insulating film pattern round before the chemical mechanical polishing process of the insulating film pattern to fill the trench in the process of manufacturing a shallow trench for semiconductor device isolation. In addition, the thickness of the insulating film pattern is reduced and then the chemical mechanical polishing process is performed. Therefore, excessive or insufficient polishing of the nitride film can be prevented from occurring due to the difference in polishing rate due to the pattern density. The reliability of the sieve element can be improved.
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