KR20010002305A - Shallow trench isolation manufacturing method - Google Patents

Abstract

In order to prevent deterioration of device isolation and leakage current due to weak corner rounding of the trench upper edge portion, a pad oxide film and a nitride film are formed on the silicon wafer, and a trench is formed by mort etching, followed by wet etching the silicon wafer. The silicon oxide sidewall of the trench upper edge portion may be etched to etch the silicon oxide sidewall of the trench, and the silicon wafer of the trench inner edge portion may be etched to wet the silicon oxide sidewall of the trench. Thereafter, the silicon wafer is thermally oxidized to grow a liner oxide film on the inner wall of the trench, an insulating film is deposited to fill the trench, and the nitride film is planarized with a buffer layer, and the nitride film is removed to complete the shallow trench for semiconductor device isolation. . In this way, the silicon wafer is wet-etched and thermally oxidized while the silicon wafer at the upper edge portion of the trench is rounded to thermally grow the liner oxide film on the inner wall of the trench, so that a good corner rounding profile at the upper edge of the trench can be obtained to concentrate the electric field. In addition, the reliability of the semiconductor device may be improved by preventing channel leakage and deterioration of device isolation characteristics, and the yield of the semiconductor device manufacturing process may be improved.

Description

Shallow trench manufacturing method for semiconductor device isolation {SHALLOW TRENCH ISOLATION MANUFACTURING METHOD}

The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a method of manufacturing a shallow trench isolation (STI) for electrically isolation between the semiconductor device and the device during the manufacturing process of the semiconductor device. .

In general, a method of separating a semiconductor device has been used a local oxidation of silicon (LOCOS) device separation method using a nitride film as a selective oxidation method.

Since the LOCOS device isolation method thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple and there is a great advantage that the device stress problem of the oxide film is small, and the oxide film produced is good.

However, when the LOCOS device isolation method is used, the area occupied by the device isolation region is not only limited in miniaturization but also causes a bird's beak.

In order to overcome this, a trench trench isolation (STI) technique is an alternative to the LOCOS isolation scheme. In trench device isolation, since trenches are made in silicon wafers to insulate the insulating material, the area occupied by device isolation regions is small, which is advantageous for miniaturization.

1A to 1D, a method of manufacturing a shallow trench for separating a conventional semiconductor device will be described.

First, as shown in FIG. 1A, the silicon wafer 1 is thermally oxidized to grow a pad oxide film 2, which is a thermal oxidation film, and the nitride film 3 is formed on the upper portion by chemical vapor deposition (CVD). Deposit. In addition, after forming a moat pattern for trench etching on the nitride layer 3, the nitride layer 3 and the pad oxide layer 2 exposed as a mask are etched and removed, and the silicon wafer 1 again exposed. ) Is etched to a target thickness by dry etching to form a shallow trench (mot etching) in the semiconductor device isolation region, and to remove the mott pattern on the nitride film.

1B, the silicon wafer 1 is thermally oxidized to form a liner oxide film 4, which is a thermal oxide film. At this time, in the silicon wafer of the active region where the nitride film 3 is formed, that is, the region in which the semiconductor device is to be formed, the liner oxide film, which is a thermal oxide film, cannot grow, and the liner oxide film, which is a thermal oxide film, is grown only on the inner wall of the trench where silicon is exposed.

Then, as shown in FIG. 1C, an insulating film 5 such as an oxide film is thickly deposited by atmospheric pressure chemical vapor deposition (APCVD) on the entire surface of the silicon wafer 1 to completely fill the trench, and to clean it. By removing impurities on the back surface of the silicon wafer 1 and then annealing to increase the density of the insulating film 5 to have an insulating property for semiconductor device isolation in an integrated circuit. Then, a pattern having a shape opposite to that of the mort pattern, that is, a reverse mort pattern is formed on the insulating layer 5, and the nitride film is exposed by etching the insulating layer 5 having the reverse mort pattern as a mask to expose the reverse mort. Remove the pattern.

Then, as shown in FIG. 1D, the insulating film 5 is planarized by a nitride film (3 in FIG. 1C) using a buffer layer by chemical mechanical polishing (CMP) process, and then remains on top of the active region silicon wafer. By removing the nitride film, a shallow trench for semiconductor device isolation is completed.

As described above, in a shallow trench for isolation of semiconductor devices manufactured by a conventional method, when a gate voltage is applied for operation of a semiconductor device, an electric field is concentrated on the upper edge portion of the trench, so channel channeling such as stress induced leakage (SILC) is performed. (channel leakage) occurs to reduce the reliability of the semiconductor device. Therefore, in order to prevent this, the trench upper edge portion is formed to be rounded, and particularly, in order to form a good profile of corner rounding, thermal oxidation including clorine (Cl) for thermal oxidation for liner oxide film growth is performed. Simultaneously with oxidation, the silicon wafer in the trench upper edge portion is etched to form corner rounding. However, this method has a problem that the rounding of the upper edge corner of the trench is insufficient, and chlorine remains at the interface between the silicon wafer and the liner oxide film, so that there is a problem that the chlorine is generated by contamination by chlorine when there is a subsequent thermal process.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to prevent degradation of device isolation characteristics and leakage current caused by weak corner rounding of the trench upper edge portion.

1A to 1D are process diagrams schematically illustrating a method of manufacturing a shallow trench for separating a conventional semiconductor device,

2A-2F are schematic diagrams illustrating a method of manufacturing a shallow trench for semiconductor device isolation in accordance with the present invention.

In order to achieve the above object, the present invention, after the trench etching, wet etching the silicon wafer to make the silicon wafer of the upper edge portion of the trench rounded, and then thermally oxidizes the silicon wafer to thermally grow the liner oxide film on the inner wall of the trench. It is characterized by.

The wet etch cleaning of the silicon wafer is characterized by etching the pad oxide film sidewall of the trench upper edge by wet etching the entire surface of the silicon wafer and etching the exposed silicon wafer of the inner wall of the trench by wet etching the silicon wafer.

The etching amount of the pad oxide layer etched by the oxide wet etching cleaning may be 500 kPa or less, and the etching amount of the silicon wafer etched by the silicon wet etching cleaning is 500 kPa or less.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2A-2F are schematic diagrams illustrating a method of manufacturing a shallow trench for semiconductor device isolation in accordance with the present invention.

First, as shown in FIG. 2A, the silicon wafer 11 is thermally oxidized to grow a pad oxide film 12, which is a thermal oxide film, and a nitride film 13 is deposited thereon by chemical vapor deposition. After forming a mort pattern for trench etching on the nitride layer 13, the nitride layer 13 and the pad oxide layer 12 exposed as the masks are etched and removed, and the exposed silicon wafer 11 is dried. By etching, the trench is etched to a target thickness to form a shallow trench in the semiconductor device isolation region (mot etching) to remove the mott pattern on the nitride film.

2B and 2C, the silicon wafer 11 is wet etched to etch the sidewalls of the silicon wafer 11 and the pad oxide layer 12 of the trench upper edge to round the trench upper edge. Form.

That is, as illustrated in FIG. 2B, the sidewalls of the pad oxide film 12 of the trench upper edge portion are wet-etched and removed by a predetermined width L by an oxide wet etching cleaning process. In this case, the pad oxide film 12 sidewall width L of the upper portion of the trench oxide that is removed by wet etching of the oxide film, that is, the etching amount of the pad oxide film that is etched by the oxide wet etching cleaning process may be 500 kPa or less. . Thereafter, as shown in FIG. 2C, the silicon wafer 11 is subjected to silicon wet etching cleaning. At this time, it is preferable that the etching amount of the silicon wafer removed by the silicon wet etching cleaning process is 500 kPa or less. Then, the trench inner wall and the pad oxide layer where the silicon is exposed are removed to wet-etch the silicon wafer of the trench edge portion where the silicon is exposed, so that the silicon wafer of the trench upper edge portion has a rounded profile unlike the related art.

Then, as shown in FIG. 2D, the silicon wafer 11 is thermally oxidized to form a liner oxide film 14 which is a thermal oxide film. At this time, in the silicon wafer of the active region where the nitride layer 13 is formed, that is, the region in which the semiconductor device is to be formed, the liner oxide layer, which is a thermal oxide film, cannot be grown, and the liner oxide layer, which is a thermal oxide film, is grown only in the trench inner wall where the silicon is exposed. Unlike in the prior art, since the liner oxide film is thermally grown in the state where the silicon wafer is rounded, the corner rounding profile in the trench upper edge portion is good.

Next, as shown in FIG. 2E, an insulating film 15 such as an oxide film is thickly deposited by atmospheric pressure chemical vapor deposition on the entire surface of the silicon wafer 11 to completely fill the trench, and to clean the impurities to back the silicon wafer 11. After removing the annealing, the annealing is performed to increase the density of the insulating layer 15 so as to have insulating characteristics for separating semiconductor elements from the integrated circuit. Then, a pattern having a shape opposite to that of the mort pattern, that is, a reverse mort pattern is formed on the insulating layer 15, and the insulating mortar pattern is exposed by etching the insulating mortar pattern to expose the nitride film, and then the reverse mort pattern is removed. do.

Then, as shown in FIG. 2F, the nitride film (13 in FIG. 2E) is planarized with a buffer layer, and the insulating film 15 is planarized by a chemical mechanical polishing process or the like, and then the semiconductor device is separated by removing the nitride film remaining on the active region silicon wafer. Complete the shallow trench for the

As described above, the present invention thermally grows the liner oxide film on the trench inner wall by thermally oxidizing the silicon wafer in the state where the silicon wafer of the trench upper edge is rounded by wet etching cleaning the silicon wafer after the trench etching. The corner rounding profile can be obtained to prevent channel package and device isolation characteristics from deteriorating due to electric field concentration, thereby improving the reliability of the semiconductor device and improving the yield of the semiconductor device manufacturing process.

Claims (4)

Thermally oxidizing the silicon wafer to form a pad oxide film, forming a nitride film thereon, patterning the nitride film and the pad oxide film through a mort pattern, and dry etching the exposed silicon wafer to a target thickness to form a trench; Wet etching the silicon wafer on which the trench is formed to round the silicon wafer of the upper edge portion of the trench; Thermally oxidizing the silicon wafer to grow a liner oxide layer on the inner wall of the trench; Depositing an insulating film on the entire surface of the silicon wafer to fill the trench; And planarizing the insulating film with the nitride film as a buffer layer, and then removing the nitride film. The method of claim 1, wherein the wet etching of the silicon wafer is performed to round the silicon wafer of the trench upper edge portion. Wet etching an oxide film on the entire surface of the silicon wafer to etch the sidewalls of the pad oxide layer of the upper edge portion of the trench; And wet etching the silicon wafer on the entire surface of the silicon wafer to etch the exposed silicon wafer on the inner wall of the trench by a predetermined amount of etching. The method of claim 2, wherein the etching amount of the pad oxide layer etched by the oxide wet etching cleaning is 500 kPa or less. The method of claim 2 or 3, wherein the etching amount of the silicon wafer etched by the silicon wet etch cleaning is 500 kPa or less.