CN113555414B - Groove type silicon carbide field effect transistor and preparation method thereof - Google Patents
Groove type silicon carbide field effect transistor and preparation method thereof Download PDFInfo
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- CN113555414B CN113555414B CN202110820925.0A CN202110820925A CN113555414B CN 113555414 B CN113555414 B CN 113555414B CN 202110820925 A CN202110820925 A CN 202110820925A CN 113555414 B CN113555414 B CN 113555414B
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 344
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 336
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 239000002184 metal Substances 0.000 claims abstract description 81
- 230000005669 field effect Effects 0.000 claims abstract description 62
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 114
- 229920005591 polysilicon Polymers 0.000 claims description 114
- 238000000034 method Methods 0.000 claims description 56
- 125000006850 spacer group Chemical group 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 50
- 239000012535 impurity Substances 0.000 claims description 36
- 230000008569 process Effects 0.000 claims description 36
- 238000005468 ion implantation Methods 0.000 claims description 27
- 230000007480 spreading Effects 0.000 claims description 23
- 238000003892 spreading Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 22
- 238000009413 insulation Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 11
- 239000012212 insulator Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 230000001413 cellular effect Effects 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 238000001465 metallisation Methods 0.000 claims description 4
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 12
- -1 silicon carbide metal-oxide Chemical class 0.000 abstract description 10
- 230000005684 electric field Effects 0.000 description 8
- 230000007704 transition Effects 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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Abstract
The invention relates to a groove type silicon carbide field effect transistor and a preparation method thereof. The cell groove comprises a cell first groove and a cell second groove corresponding to the cell first groove, a second conductive type inter-groove shielding connecting column on the second conductive type shielding layer stretches into the space between the cell first groove and the cell second groove, and the cell groove also comprises an inter-groove source connecting column electrically connected with a source electrode metal layer, wherein the inter-groove source connecting column is positioned between the cell first groove and the cell second groove, and the source electrode metal layer can be electrically connected with the second conductive type inter-groove shielding connecting column through the inter-groove source connecting column so as to enable the source electrode metal layer to be electrically connected with the second conductive type shielding layer. The invention can improve the reliability of the silicon carbide metal-oxide semiconductor field effect transistor, reduce on-resistance and switching loss, and improve the performance of the silicon carbide metal-oxide semiconductor field effect transistor.
Description
Technical Field
The invention relates to a field effect transistor and a preparation method thereof, in particular to a groove type silicon carbide field effect transistor and a preparation method thereof.
Background
The silicon carbide material is used as one representative of the third generation wide bandgap semiconductor material, and the high-voltage power device manufactured based on the silicon carbide material has excellent electric and thermal properties compared with the traditional silicon device, can meet more severe application environments, and is considered as the most potential material in the fields of high-power, high-temperature and high-frequency power electronics, such as power supply, photovoltaic power generation, electric automobile, aerospace and the like. Silicon carbide power metal-oxide semiconductor field effect transistors are becoming mature based on improvements in electrical performance, manufacturing process and reliability over the past few years. Silicon carbide power metal-oxide semiconductor field effect transistors have low on-resistance, low switching loss and good switching performance, and gradually become a new generation of mainstream low-loss power devices.
Currently, the gate electrodes of silicon carbide field effect transistors can be largely divided into two types: planar gates and trench gates. The groove gate silicon carbide field effect transistor can eliminate the JFET region existing in the planar gate, reduce the on-resistance of the device and improve the channel density. However, when the trench-gate silicon carbide field effect transistor is in a blocking state, the epitaxial layer at the bottom of the gate trench results in high electric field strength due to curvature effects. According to the gaussian theorem, at this time, the oxide layer at the bottom of the gate trench is subjected to an extreme electric field stress approximately 2.8 times higher than that of the silicon carbide material, thereby causing degradation of the quality of the gate oxide layer and degradation of the device performance. For the silicon carbide U-shaped groove gate field effect transistor, the stress at the bottom of the groove can be reduced through a smoother groove-shaped bottom structure, so that the reliability of the device is improved. However, the etching difficulty of the U-shaped groove is high, the process is complex, and the bottom is difficult to form a smooth structure morphology.
In addition, the bottom of the groove can be provided with a grounding shielding layer to improve reliability, the introduced shielding layer can widen a space charge region in the epitaxial layer, the electric field intensity of an oxide layer at the bottom of the groove can be effectively reduced through the space charge region withstand voltage, and the reliability of the device is improved. However, the ground shield layer may simultaneously introduce a new JFET region, resulting in an increase in the on-resistance of the fet. The conductivity type of the shielding layer is opposite to that of the epitaxial layer, and if the epitaxial layer is of an N type, the shielding layer is of a P type.
In summary, in the prior art, when the silicon carbide metal-oxide semiconductor field effect transistor is manufactured, the problem that the reliability of the gate oxide layer of the silicon carbide metal-oxide semiconductor field effect transistor is low is caused by the fact that the thickness of the oxide layer at the bottom of the trench is insufficient or the coverage of the oxide layer at the sharp corners of the bottom is insufficient, so that the breakdown of the gate oxide layer is easily generated due to the concentration of an electric field.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a groove type silicon carbide field effect transistor and a preparation method thereof, which can improve the reliability of the silicon carbide metal-oxide semiconductor field effect transistor, reduce on-resistance and switching loss and improve the performance of the silicon carbide metal-oxide semiconductor field effect transistor.
According to the technical scheme provided by the invention, the trench type silicon carbide field effect transistor comprises a first conductive type silicon carbide substrate, a first conductive type silicon carbide epitaxial layer arranged on the front surface of the first conductive type silicon carbide substrate and a source metal layer for forming a source electrode; arranging a plurality of cell in the first conductive type silicon carbide epitaxial layer, wherein the cell comprises a cell groove in the first conductive type silicon carbide epitaxial layer; a second conductive type shielding layer is arranged below the bottom of the cellular groove, and the second conductive type shielding layer covers the bottom of the cellular groove;
On the section of the field effect transistor, the cell groove comprises a cell first groove and a cell second groove corresponding to the cell first groove, a second conductive type inter-groove shielding connecting column on the second conductive type shielding layer stretches into the space between the cell first groove and the cell second groove, and the second conductive type inter-groove shielding connecting column is contacted with the side wall corresponding to the cell first groove and the cell second groove;
The inter-groove source electrode connecting column is electrically connected with the source electrode metal layer, the inter-groove source electrode connecting column is positioned between the first groove of the cell and the second groove of the cell, and the source electrode metal layer can be electrically connected with the inter-groove shielding connecting column of the second conductive type through the inter-groove source electrode connecting column so as to enable the source electrode metal layer to be electrically connected with the shielding layer of the second conductive type; the first conductive polysilicon of the grid in the first groove of the cell is insulated and isolated from the source electrode connecting column between the grooves through the first insulating isolator of the grid and the source electrode metal layer positioned above the first groove of the cell, and the second conductive polysilicon of the grid in the second groove of the cell is insulated and isolated from the source electrode connecting column between the grooves through the second insulating isolator of the grid and the source electrode metal layer positioned above the second groove of the cell; the top of the second conduction type inter-groove shielding connecting column between the first groove of the cell and the second groove of the cell is not lower than the corresponding bottom ends of the first conduction polysilicon of the grid and the second conduction polysilicon of the grid.
A second conduction type doped channel region and a second conduction type source region positioned on the second conduction type doped channel region are arranged on the second conduction type inter-slot shielding connecting column, and the second conduction type doped channel region is adjacent to the second conduction type source region and the second conduction type inter-slot shielding connecting column; the second conduction type source region is in ohmic contact with the inter-groove source connecting column, and the inter-groove source connecting column is electrically connected with the second conduction type inter-groove shielding connecting column through the second conduction type source region and the second conduction type doping channel region;
The second conduction type doped channel region and the second conduction type source region are respectively contacted with the corresponding side walls of the first cell groove and the second cell groove, and are isolated from the first conductive polysilicon of the grid in the first cell groove through the first insulating oxide layer of the grid covering the inner side wall and the bottom wall of the first cell groove; the second conduction type doped channel region and the second conduction type source region are isolated from the grid second conductive polysilicon in the cell second groove through a grid second insulating oxide layer covering the inner side wall and the bottom wall of the cell second groove;
The grid first insulating oxide layer is connected with the grid first insulating isolator so as to cover the grid first conductive polysilicon by using the grid first insulating oxide layer and the grid first insulating isolator; the grid electrode second insulating oxide layer is connected with the grid electrode second insulating isolator so that the grid electrode second conductive polysilicon can be covered by the grid electrode second insulating oxide layer and the grid electrode second insulating isolator.
The semiconductor device further comprises a mesa structure which is in contact with the corresponding outer side walls of the first cell groove and the second cell groove, wherein the mesa structure comprises a first conductive type current expansion layer arranged in the first conductive type silicon carbide epitaxial layer and a second conductive type silicon carbide base region positioned on the first conductive type current expansion layer, and the second conductive type silicon carbide base region is adjacent to the first conductive type current expansion layer;
and arranging a first conductive type silicon carbide source region and a second conductive type silicon carbide contact region on the second conductive type silicon carbide base region, wherein the first conductive type silicon carbide source region and the second conductive type silicon carbide contact region are adjacent, the source metal layer is in ohmic contact with the first conductive type silicon carbide source region and the second conductive type silicon carbide contact region, and the first conductive type silicon carbide source region, the first conductive type current expansion layer and the second conductive type silicon carbide base region are in contact with corresponding outer side walls of the first groove of the cell and the second groove of the cell.
And arranging a back drain metal on the back surface of the first conductive type silicon carbide substrate, wherein the back drain metal is in ohmic contact with the first conductive type silicon carbide substrate.
The second conduction type inter-groove shielding connecting column and the second conduction type shielding layer are the same process step layer; the second insulating isolator of the grid electrode and the first insulating isolator of the grid electrode are the same process step layer, and the second insulating isolator of the grid electrode and the first insulating isolator of the grid electrode are silicon dioxide.
The first insulating oxide layer of the grid electrode and the second insulating oxide layer of the grid electrode are the same process step layer; the thickness of the first grid insulation isolator and the second grid insulation isolator contacted with the source electrode connecting column between the grooves is larger than that of the first grid insulation oxide layer and the second grid insulation oxide layer.
A method of fabricating a trench silicon carbide field effect transistor, the method comprising:
Step 1, providing a first conductive type silicon carbide substrate and a first conductive type silicon carbide epitaxial layer arranged on the first conductive type silicon carbide substrate, preparing a second conductive type shielding layer, a cell groove and a mesa structure which is connected with the cell groove in an adapting way in the first conductive type silicon carbide epitaxial layer, wherein the cell groove comprises a cell first groove and a cell second groove, the second conductive type shielding layer covers the groove bottom outer wall corresponding to the cell first groove and the cell second groove, a second conductive type inter-groove shielding connecting column on the second conductive type shielding layer extends into the space between the cell first groove and the cell second groove, the second conductive type inter-groove shielding connecting column contacts with the side wall corresponding to the cell first groove and the cell second groove, and the mesa structure contacts with the outer side wall corresponding to the cell first groove and the cell second groove;
Step 2, arranging a grid first insulating oxide on the side wall and the bottom wall of the first cell groove, wherein the grid first insulating oxide covers the side wall and the bottom wall of the first cell groove, arranging a grid second insulating oxide on the side wall and the bottom wall of the second cell groove, and the grid second insulating oxide covers the side wall and the bottom wall of the second cell groove;
Step 3, depositing gate polysilicon to obtain polysilicon filling bodies filled in the first grooves of the cells and the second grooves of the cells;
Step 4, etching the polysilicon filling bodies in the first cell groove and the second cell groove to obtain grid first conductive polysilicon, grid first insulating spacer filling grooves and grid first insulating oxide layers in the first cell groove; meanwhile, gate second conductive polysilicon, a gate second insulating spacer filling groove and a gate second insulating oxide layer which are positioned in the cell second groove can be obtained;
Step 5, depositing an insulating isolation material to obtain a grid first insulating isolator and a grid second insulating isolator, wherein the grid first insulating isolator is filled in a grid first insulating isolator filling groove and can cover grid first conductive polysilicon, and the grid first insulating isolator is in contact with a grid first insulating oxide layer; the grid electrode second insulating isolator is filled in the grid electrode second insulating isolator filling groove and can cover the grid electrode second conductive polysilicon, and the grid electrode second insulating isolator is in contact with the grid electrode second insulating oxide layer;
Step 6, carrying out required groove etching to obtain a source electrode connecting column groove, wherein the source electrode connecting column groove is positioned between the first cell groove and the second source electrode groove, the side walls of the source electrode connecting column groove are respectively formed through the first grid insulating insulator and the second grid insulating insulator, and the groove bottom of the source electrode connecting column groove is level with the groove bottom of the filling groove of the first grid insulating insulator and the groove bottom of the filling groove of the second grid insulating insulator;
Step 7, implanting second conductivity type impurity ions right above the source electrode connecting column groove so as to obtain a second conductivity type doped channel region and a second conductivity type source region, wherein the second conductivity type doped channel region is adjacent to the second conductivity type source region and a shielding connecting column between the second conductivity type grooves, the second conductivity type source region is located right above the second conductivity type doped channel region, and the second conductivity type doped channel region and the second conductivity type source region are respectively contacted with corresponding side walls of the first groove of the cell and the second groove of the cell; the bottom of the second conduction type doped channel region is not lower than the bottoms of the first conduction polysilicon and the second conduction polysilicon of the grid electrode;
step 8, performing metal deposition right above the first conductive type silicon carbide epitaxial layer to obtain a source metal layer and an inter-groove source electrode connecting column filled in a source electrode connecting column groove, wherein the inter-groove source electrode connecting column is electrically connected with the source metal layer, the inter-groove source electrode connecting column is in ohmic contact with a second conductive type source region, grid first conductive polysilicon in a cell first groove is isolated from the inter-groove source electrode connecting column through a grid first insulating insulator and the source metal layer positioned above the cell first groove, and grid second conductive polysilicon in a cell second groove is isolated from the inter-groove source electrode connecting column through a grid second insulating insulator and the source metal layer positioned above the cell second groove;
and 9, manufacturing back drain metal on the back of the first conductive type silicon carbide substrate, wherein the back drain metal is in ohmic contact with the first conductive type silicon carbide substrate.
The step 1 specifically comprises the following steps:
step 1.1, providing a first conductive type silicon carbide substrate, and growing on the first conductive type silicon carbide substrate to obtain a first conductive type silicon carbide epitaxial layer;
step 1.2, performing first conductivity type impurity ion implantation above the first conductivity type silicon carbide epitaxial layer to obtain a first conductivity type current spreading base layer penetrating through the first conductivity type silicon carbide epitaxial layer in the first conductivity type silicon carbide epitaxial layer;
step 1.3, performing second conductivity type impurity ion implantation above the first conductivity type silicon carbide epitaxial layer to obtain a second conductivity type silicon carbide base layer, wherein the second conductivity type silicon carbide base layer is adjacent to the first conductivity type current expansion base layer;
step 1.4, carrying out second conductivity type impurity ion implantation to obtain a second conductivity type silicon carbide contact region in the second conductivity type silicon carbide region layer;
Step 1.5, implanting first conductivity type impurity ions to obtain a first conductivity type silicon carbide source region in the second conductivity type silicon carbide region layer, wherein the first conductivity type silicon carbide source region is adjacent to an adjacent second conductivity type silicon carbide contact region;
Step 1.6, after the groove is etched by utilizing a groove etching process, a cell groove is obtained, wherein the cell groove comprises a cell first groove and a cell second groove, the cell first groove and the cell second groove penetrate through a second conductive type silicon carbide base layer and a first conductive type current expansion base layer so as to respectively form a second conductive type silicon carbide base region and a first conductive type current expansion layer through the second conductive type silicon carbide base layer and the first conductive type current expansion base layer, the groove bottoms of the cell first groove and the cell second groove corresponding to the first conductive type current expansion layer are positioned below the first conductive type current expansion layer, and a mesa structure can be formed by utilizing the second conductive type silicon carbide base region, the first conductive type current expansion layer and a second conductive type silicon carbide contact region adjacent to the first conductive type silicon carbide source region on the second conductive type silicon carbide base region;
Step 1.7, a second conductive type shielding layer and a second conductive type inter-groove shielding connecting column connected with the second conductive type shielding layer can be obtained in the first conductive type silicon carbide epitaxial layer through a required ion implantation process and a pushing junction, the second conductive type shielding layer can cover cell first grooves and corresponding groove bottoms of the cell second grooves, the second conductive type inter-groove shielding connecting column can extend into the first grooves and the second grooves of the cell, and the second conductive type inter-groove shielding connecting column is in contact with corresponding side walls of the first grooves and the second grooves of the cell.
The step 1 specifically comprises the following steps:
step a, providing a first conductive type silicon carbide substrate, growing a first conductive type silicon carbide epitaxial layer on the first conductive type silicon carbide substrate, and implanting and pushing impurity ions of a second conductive type in the process of growing the first conductive type silicon carbide epitaxial layer so as to obtain a second conductive type shielding base layer in the first conductive type silicon carbide epitaxial layer;
step b, performing first conductivity type impurity ion implantation above the first conductivity type silicon carbide epitaxial layer to obtain a first conductivity type current expansion base layer penetrating through the first conductivity type silicon carbide epitaxial layer in the first conductivity type silicon carbide epitaxial layer;
C, carrying out second conductivity type impurity ion implantation above the first conductivity type silicon carbide epitaxial layer so as to obtain a second conductivity type silicon carbide base layer, wherein the second conductivity type silicon carbide base layer is adjacent to the first conductivity type current expansion base layer;
Step d, carrying out second conductivity type impurity ion implantation to obtain a second conductivity type silicon carbide contact region in the second conductivity type silicon carbide region layer;
Step e, implanting impurity ions of the first conductivity type to obtain a first conductivity type silicon carbide source region in the second conductivity type silicon carbide region layer, wherein the first conductivity type silicon carbide source region is adjacent to an adjacent second conductivity type silicon carbide contact region;
Step f, after the groove is etched by utilizing a groove etching process, a cell groove is obtained, wherein the cell groove comprises a cell first groove and a cell second groove, the cell first groove and the cell second groove penetrate through a second conductive type silicon carbide base layer and a first conductive type current expansion base layer so as to respectively form a second conductive type silicon carbide base region and a first conductive type current expansion layer through the second conductive type silicon carbide base layer and the first conductive type current expansion base layer, the groove bottoms of the cell first groove and the cell second groove are positioned below the first conductive type current expansion layer, and a mesa structure can be formed by utilizing the second conductive type silicon carbide base region, the first conductive type current expansion layer and a second conductive type silicon carbide contact region positioned on the second conductive type silicon carbide base region and adjacent to the first conductive type silicon carbide source region;
Meanwhile, the second conductive type shielding base layer can be used for forming a second conductive type shielding layer and second conductive type inter-groove shielding connecting columns, the second conductive type shielding layer can cover the bottoms of the first grooves of the cells and the corresponding grooves of the second grooves of the cells, the second conductive type inter-groove shielding connecting columns can extend into the first grooves of the cells and the second grooves of the cells, and the second conductive type inter-groove shielding connecting columns are in contact with the corresponding side walls of the first grooves of the cells and the corresponding side walls of the second grooves of the cells.
The first grid insulating isolator and the second grid insulating isolator are silicon dioxide.
The doping concentration of the second conductive type doped channel region is lower than the doping concentration of the second conductive type source region.
The first gate insulating oxide and the second gate insulating oxide are respectively grown in the first cell groove and the second cell groove through thermal oxidation; the thickness of the first grid insulation isolator and the second grid insulation isolator contacted with the source electrode connecting column between the grooves is larger than that of the first grid insulation oxide layer and the second grid insulation oxide layer.
In the "first conductivity type" and the "second conductivity type", for an N-type field effect transistor, the first conductivity type refers to an N-type, and the second conductivity type refers to a P-type; for a P-type field effect transistor, the first conductivity type and the second conductivity type refer to the type that is the opposite of an N-type power semiconductor device.
The invention has the advantages that: the inter-trench source connection column, the second conductivity type source region, the second conductivity type doped channel region, the second conductivity type inter-trench shield connection column and the second conductivity type shield layer can form a depletion type MOS transistor, so that the potential of the second conductivity type shield layer can be self-adjusted according to the gate potential of the field effect transistor.
When the field effect transistor works in a conducting state, the formed depletion type MOS transistor can be pinched off and closed according to the gate voltage state of the field effect transistor, the potential of the grounded second conductive type shielding layer is switched to a floating state, the potential of the second conductive type shielding layer is increased, the depletion layer in the first conductive type silicon carbide epitaxial layer is contracted, the field effect transistor has a larger current conducting area and stronger conducting capacity, and the conducting resistance is effectively reduced.
When the field effect transistor is in a blocking state, the depletion type MOS transistor can work in a conducting state according to the gate bias voltage of the field effect transistor, and the second conductive type shielding layer and the source metal layer are both at a common ground potential. The channel of the depletion type MOS tube is kept on, the second conductive type shielding layer is grounded, a body diode formed by the second conductive type shielding layer and the first conductive type silicon carbide epitaxial layer bears main blocking voltage, and a diode formed by the first conductive type silicon carbide epitaxial layer and the second conductive type silicon carbide region plays an auxiliary role. Since the second conductive type shielding layer and the source metal layer are grounded in common, an electric field of the gate first insulating oxide layer, the gate second insulating gate oxide layer corresponding to the bottom and corners can be effectively shielded. Meanwhile, the grounded second conductive type shielding layer can reduce the electric field strength through the electric potential of the side surfaces of the first insulating oxide layer and the second insulating oxide layer of the grid electrode, so that the first insulating oxide layer of the grid electrode in the first groove of the cell and the second insulating oxide layer of the grid electrode in the second groove of the cell are better protected. Meanwhile, the gate-drain charge of the field effect transistor is reduced due to the shielding effect of the ground second conductive type shielding layer. With the reduction of on-resistance and gate-drain charge, the high-frequency figure of merit obtained by the silicon carbide field effect transistor device of the present invention can reduce switching losses, which are significantly reduced compared with conventional silicon carbide trench gate metal-oxide semiconductor field effect transistor devices.
Drawings
Fig. 1 is a schematic structural view of the present invention.
FIGS. 2-17 are cross-sectional views of steps of an embodiment of the present invention, wherein
Fig. 2 is a cross-sectional view of the present invention after an N-type silicon carbide epitaxial layer is formed on an N-type silicon carbide substrate.
Fig. 3 is a cross-sectional view of the present invention after an N-type current spreading base layer is obtained.
Fig. 4 is a cross-sectional view of the P-type silicon carbide base layer obtained by the present invention.
Fig. 5 is a cross-sectional view of the present invention after a P + silicon carbide contact region has been made.
Fig. 6 is a cross-sectional view of the present invention after an n+ silicon carbide source region has been obtained.
FIG. 7 is a cross-sectional view of the present invention after a first trench of a cell and a second trench of a cell are obtained.
Fig. 8 is a cross-sectional view of the p+ shield layer and p+ inter-trench shield connection post of the present invention.
Fig. 9 is a cross-sectional view of the gate first insulating oxide and the gate second insulating oxide of the present invention.
Fig. 10 is a cross-sectional view of the polysilicon filling body obtained by the present invention.
Fig. 11 is a cross-sectional view of the present invention after the gate first insulating spacer filled trench and the gate second insulating spacer filled trench are obtained.
Fig. 12 is a cross-sectional view of the present invention after a gate first insulating spacer and a gate second insulating spacer are obtained.
Fig. 13 is a cross-sectional view of the present invention after source connection stud trench is formed.
Fig. 14 is a cross-sectional view of the p+ doped channel region of the present invention.
Fig. 15 is a cross-sectional view of the present invention after p+ source regions are obtained.
Fig. 16 is a cross-sectional view of the present invention after source metal layers and inter-trench source connection pillars are obtained.
Fig. 17 is a cross-sectional view of the present invention after back side drain metal is obtained.
Reference numerals illustrate: 1-back drain metal, 2-N silicon carbide substrate, 3-N silicon carbide epitaxial layer, 4-P+ shielding layer, 5-P+ doped channel region, 6-P+ source region, 7-grid first insulating oxide layer, 8-grid first conductive polysilicon, 9-grid first insulating spacer, 10-N current expansion layer, 11-P silicon carbide base region, 12-N+ silicon carbide source region, 13-P+ silicon carbide contact region, 14-source metal layer, 15-inter-channel source connection column, 16-grid second insulating spacer, 17-grid second conductive polysilicon, 18-grid second insulating oxide layer, 19-N current expansion base layer, 20-P silicon carbide base layer, 21-cell first trench, 22-cell second trench, 23-P+ inter-channel shielding connection column, 24-grid first insulating spacer filling trench, 25-grid second insulating spacer filling trench, 26-filling trench first transition region, 27-filling trench second transition region, 28-grid second insulating spacer 31-gate first insulating oxide layer, 30-gate first insulating spacer.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
As shown in fig. 1 and 17: in order to improve the reliability of the silicon carbide metal-oxide semiconductor field effect transistor, reduce on-resistance and switching loss, and improve the performance of the silicon carbide metal-oxide semiconductor field effect transistor, taking the first conductivity type as an N-type as an example, the invention comprises an N-type silicon carbide substrate 2, an N-type silicon carbide epitaxial layer 3 arranged on the front surface of the N-type silicon carbide substrate 2, and a source metal layer 14 for forming a source electrode; a plurality of cell units are arranged in the N-type silicon carbide epitaxial layer 3, and each cell unit comprises a cell unit groove positioned in the N-type silicon carbide epitaxial layer 3; a P+ shielding layer 4 is arranged below the bottom of the cellular groove, and the P+ shielding layer 4 coats the bottom of the cellular groove;
On the cross section of the field effect transistor, the cell groove comprises a cell first groove 21 and a cell second groove 22 corresponding to the cell first groove 21, a P+ inter-groove shielding connecting column 23 on the P+ shielding layer 4 stretches into the space between the cell first groove 21 and the cell second groove 22, and the P+ inter-groove shielding connecting column 23 contacts with the side walls corresponding to the cell first groove 21 and the cell second groove 22;
The semiconductor device further comprises an inter-groove source electrode connecting column 15 electrically connected with the source electrode metal layer 14, wherein the inter-groove source electrode connecting column 15 is positioned between the cell first groove 21 and the cell second groove 22, and the source electrode metal layer 14 can be electrically connected with the P+ inter-groove shielding connecting column 23 through the inter-groove source electrode connecting column 15 so as to enable the source electrode metal layer 14 to be electrically connected with the P+ shielding layer 4; the first conductive polysilicon 8 of the grid in the first groove 21 of the cell is insulated and isolated from the source electrode connecting column 15 between the grooves and the source metal layer 14 above the first groove 21 of the cell by the first insulating isolator 9 of the grid, the second conductive polysilicon 17 of the grid in the second groove 22 of the cell is insulated and isolated from the source electrode connecting column 15 between the grooves and the source metal layer 14 above the second groove 22 of the cell by the second insulating isolator 16 of the grid; the top of the p+ inter-trench shield connection column 23 between the cell first trench 21 and the cell second trench 22 is not lower than the corresponding bottom ends of the gate first conductive polysilicon 8 and the gate second conductive polysilicon 17.
Specifically, the N-type silicon carbide substrate 2 may take a conventional form, and the thickness and the like of the N-type silicon carbide substrate 2 may be selected as required. Of course, the N-type silicon carbide substrate 2 may also be made of a semiconductor material commonly used in the prior art, such as Si, ge, gaAs, gaN, alN, diamond GaO material, etc., and may be specifically selected according to the requirements. An N-type silicon carbide epitaxial layer 3 is arranged on the N-type silicon carbide substrate 2, and generally, the thickness of the N-type silicon carbide epitaxial layer 3 is smaller than that of the N-type silicon carbide substrate 2, and the doping concentration of the N-type silicon carbide epitaxial layer 3 is smaller than that of the N-type silicon carbide substrate 2; in addition, a source metal layer 14 is further disposed above the N-type silicon carbide epitaxial layer 3, the source metal layer 14 can be used to form a source electrode of the field effect transistor, and the manner of forming the source electrode by using the source metal layer 14 can be consistent with the prior art, which is well known in the art, and will not be repeated herein.
In the embodiment of the invention, the cells in the cell area adopt a groove structure, and specifically comprise cell grooves, a p+ shielding layer 4 is arranged below the bottoms of the cell grooves, the bottoms of the cell grooves can be covered by the p+ shielding layer 4, and of course, the outer walls of the bottoms of the cell grooves can be covered by the p+ shielding layer 4, namely, the width of the p+ shielding layer 4 is larger than that of the cell grooves, the p+ shielding layer 4 is contacted with the outer walls of the bottoms of the cell grooves, the upper end of the p+ shielding layer 4 is positioned above the bottoms of the cell grooves, and the specific action of the p+ shielding layer 4 and the matching relation between the p+ shielding layer and the cell grooves are consistent with the prior art, and are well known in the technical field and are not repeated herein.
In practical implementation, the cell trench includes a cell first trench 21 and a cell second trench 22, where the cell first trench 21 and the cell second trench 22 are obtained by the same process step, i.e., the cell first trench 21 and the cell second trench 22 have the same depth in the N-type silicon carbide epitaxial layer 3. When the first cell groove 21 and the second cell groove 22 are matched to form a cell groove, P+ inter-groove shielding connecting columns 23 are arranged on the P+ shielding layer 4, the P+ inter-groove shielding connecting columns 23 are vertically distributed, the P+ inter-groove shielding connecting columns 23 and the P+ shielding layer 4 are of the same process layer, the lower end of the P+ inter-groove shielding connecting columns 23 is connected with the P+ shielding layer 4, the top end of the P+ inter-groove shielding connecting columns 23 is positioned between the first cell groove 21 and the second cell groove 22, two sides of the P+ inter-groove shielding connecting columns 23 are respectively connected with corresponding side walls of the first cell groove 21 and the second cell groove 22, namely, the side edges of the P+ inter-groove shielding connecting columns 23 adjacent to the first cell groove 21 are in contact with the side walls of the second cell groove 21 adjacent to the second cell groove 22, and the side edges of the P+ inter-groove shielding connecting columns 23 adjacent to the second cell groove 22 are in contact with the side walls of the second cell groove 22 adjacent to the first cell groove 21.
In the embodiment of the invention, the inter-groove source electrode connecting column 15 is electrically connected with the source electrode metal layer 14, the inter-groove source electrode connecting column 15 is positioned below the source electrode metal layer 14, the inter-groove source electrode connecting column 15 and the source electrode metal layer 14 are the same process step layer, the inter-groove source electrode connecting column 15 also extends into the space between the cell first groove 21 and the cell second groove 22, wherein the inter-groove source electrode connecting column 15 corresponds to the upper parts of the cell first groove 21 and the cell second groove 22, and the P+ inter-groove shielding connecting column 23 corresponds to the bottoms of the cell first groove 21 and the cell second groove 22. The source connection posts 15 and the p+ shield connection posts 23 may be coaxially arranged. When the inter-trench source connection post 15 vertically extends into the cell first trench 21 and the cell second trench 22, the inter-trench source connection post 15 can be electrically connected with the p+ inter-trench shield connection post 23, and since the inter-trench source connection post 15 is electrically connected with the source metal layer 14 and the p+ inter-trench shield connection post 23 and the p+ shield layer 23 are the same process step layer, the source metal layer 14 can be electrically connected with the p+ shield layer 4.
The first conductive polysilicon 8 of the gate is disposed in the first trench 21 of the cell, the second conductive polysilicon 17 of the gate is disposed in the second trench 22 of the cell, the first conductive polysilicon 8 of the gate and the second conductive polysilicon 17 of the gate are two mutually independent conductive polysilicon, the first conductive polysilicon 8 of the gate and the second conductive polysilicon 17 of the gate can be connected with the gate electrode forming the field effect transistor, and the mode of forming the gate electrode by the first conductive polysilicon 8 of the gate and the second conductive polysilicon 17 of the gate is consistent with the prior art, and is specifically known to those skilled in the art and will not be repeated here.
When the inter-channel source connection 15 is located in the first cell trench 21 and the second cell trench 22, insulation isolation between the inter-channel source connection 15 and the first conductive polysilicon 8 and the second conductive polysilicon 17 is required. In implementation, the gate first conductive polysilicon 8 in the cell first trench 21 is isolated from the inter-trench source connection pillar 15 by the gate first insulator 9, and is isolated from the source metal layer 14 above the cell first trench 21 by the gate first insulator 9. Similarly, the gate second conductive polysilicon 17 within the cell second trench 22 is isolated from the inter-trench source connection pillars 15 by the gate second insulating spacers 16, and isolated from the source metal layer 14 over the cell second trench 22 by the gate second insulating spacers 16. In addition, the top of the p+ inter-trench shield connection column 23 between the first cell trench 21 and the second cell trench 22 is not lower than the bottom ends of the gate first conductive polysilicon 8 and the gate second conductive polysilicon 17, respectively.
Further, a p+ doped channel region 5 and a p+ source region 6 located on the p+ doped channel region 5 are disposed on the p+ inter-trench shield connection column 23, and the p+ doped channel region 5 is adjacent to the p+ source region 6 and the p+ inter-trench shield connection column 23; the P+ source region 6 is in ohmic contact with the inter-groove source connecting column 15, and the inter-groove source connecting column 15 is electrically connected with the P+ inter-groove shielding connecting column 23 through the P+ source region 6 and the P+ doped channel region 5;
the P+ doped channel region 5 and the P+ source region 6 are respectively contacted with the corresponding side walls of the first cell groove 21 and the second cell groove 22, and the P+ doped channel region 5 and the P+ source region 6 are isolated from the first grid conductive polysilicon 8 in the first cell groove 21 through the first grid insulating oxide layer 7 covering the inner side wall and the bottom wall of the first cell groove 21; the P+ doped channel region 5 and the P+ source region 6 are isolated from the grid second conductive polysilicon 17 in the cell second groove 21 through the grid second insulating oxide layer 18 covering the inner side wall and the bottom wall of the cell second groove 22;
The grid first insulating oxide layer 7 and the grid first insulating isolator 9 are connected mutually so that the grid first conductive polysilicon 8 can be coated by the grid first insulating oxide layer 7 and the grid first insulating isolator 9; the gate second insulating oxide 18 is interconnected with the gate second insulating spacer 16 so that the gate second conductive polysilicon 17 can be encapsulated by the gate second insulating oxide 18, the gate second insulating spacer 16.
In the embodiment of the invention, a p+ doped channel region 5 is arranged right above a p+ inter-trench shield connection column 23, and a p+ source region 6 is arranged right above the p+ doped channel region 5, wherein the p+ doped channel region 5 is adjacent to the p+ source region 6 above and the p+ inter-trench shield connection column 23 below, and the p+ source region 6 is in ohmic contact with the end of the inter-trench source connection column 15. The p+ source region 6, the p+ doped channel region 5, and the p+ inter-trench shield connection pillars 23 may be coaxially distributed. After the inter-trench source connection post 15 is in ohmic contact with the p+ source region 6, the inter-trench source connection post 15 can be electrically connected with the p+ inter-trench shield connection post 23 through the p+ source region 6 and the p+ doped channel region 5, i.e., the p+ inter-trench shield connection post 23 can be electrically connected with the inter-trench source connection post 15 through the p+ doped channel region 5 and the p+ source region 6, so that the reliability of the electrical connection between the p+ shield layer 4 and the source metal layer 14 is improved.
In the implementation, the p+ doped channel region 5 and the p+ source region 6 are in contact with the corresponding outer sidewalls of the first cell trench 21 and the second cell trench 22, and the description of the p+ inter-trench shielding connection column 23 and the corresponding outer sidewalls of the first cell trench 21 and the second cell trench 22 may be referred to specifically, and will not be repeated here. After the p+ constant state channel region 5 and the p+ source region 6 are contacted with the corresponding outer side walls of the first cell trench 21 and the second cell trench 22, the p+ doped channel region 5 and the p+ source region 6 are isolated from the first conductive polysilicon 8 of the gate in the first cell trench 21 through the first insulating oxide layer 7 of the gate covering the inner side wall and the bottom wall of the first cell trench 21; meanwhile, the p+ doped channel region 5 and the p+ source region 6 are isolated from the gate second conductive polysilicon 17 in the cell second trench 21 by a gate second insulating oxide layer 18 covering the inner sidewall and the bottom wall of the cell second trench 22. Of course, the p+ inter-trench shield connection post 23 is in corresponding contact with the gate first insulating oxide layer 7 and the gate second insulating oxide layer 18 so as to be isolated from the gate first conductive polysilicon 8 by the gate first insulating oxide layer 7 and isolated from the gate second conductive polysilicon 17 by the gate second insulating oxide layer 18.
In the embodiment, the first insulating oxide layer 7 and the second insulating oxide layer 18 are silicon dioxide layers, the first insulating oxide layer 7 grows on the side wall and the bottom wall of the first trench 21, and the second insulating oxide layer 18 grows on the side wall and the bottom wall of the second trench 22. The first gate insulating oxide layer 7 and the second gate insulating oxide layer 18 are the same process step layer, the second gate insulating spacer 16 and the first gate insulating spacer 9 are the same process step layer, and the second gate insulating spacer 16 and the first gate insulating spacer 9 are both silicon dioxide. The first grid insulating isolator 9 and the second grid insulating isolator 16 are prepared through a deposition process mode, the thickness of the first grid insulating isolator 9 is larger than that of the first grid insulating oxide layer 7, and the thickness of the second grid insulating isolator 16 is larger than that of the second grid insulating oxide layer 18.
In the first cell groove 21, the first gate insulating oxide layer 7 and the first gate insulating spacer 9 are connected to each other so that the first gate conductive polysilicon 8 can be covered by the first gate insulating oxide layer 7 and the first gate insulating spacer 9, and thus the first gate conductive polysilicon 8 can be completely surrounded; similarly, the gate second insulating oxide 18 is connected to the gate second insulating spacer 16, so that the gate second insulating oxide 18 and the gate second insulating spacer 16 can cover the gate second conductive polysilicon 17.
In implementation, the inter-channel source connection column 15, the p+ source region 6, the p+ doped channel region 5, the p+ inter-channel shield connection column 23 and the p+ shield layer 4 can form a depletion PMOS structure, and the potential of the p+ shield layer 4 can be self-adjusted according to the gate potential of the fet.
The self-adjustment process of the potential of the P+ shielding layer 4 according to the grid potential of the field effect transistor comprises the following steps: when the field effect transistor works in a conducting state, because the grid voltage of the field effect transistor is positive, the formed depletion type PMOS is pinched off and closed, the potential of the grounded P+ shielding layer 4 is switched to a floating state, so that the potential of the P+ shielding layer 4 is raised, the depletion layer in the N-type silicon carbide epitaxial layer 3 is contracted, the field effect transistor has larger current conducting area and stronger conducting capacity, and the conducting resistance is effectively reduced.
When the field effect transistor is turned into a blocking state, the gate bias voltage of the field effect transistor is lower than the pinch-off voltage of the depletion type PMOS, and the depletion type PMOS operates in a conducting state, and the p+ shielding layer 4 and the source metal layer 14 are both at the common ground potential. The depletion type PMOS channel is kept on, the P+ shielding layer 4 is grounded, a body diode formed by the P+ shielding layer 4 and the N-type silicon carbide epitaxial layer 3 bears main blocking voltage, and a diode formed by the N-type silicon carbide epitaxial layer 3 and the P-type silicon carbide base region 11 plays an auxiliary role. Since the p+ shield layer 4 and the source metal layer 14 are grounded in common, the electric fields of the corresponding bottoms and corners of the gate first insulating oxide layer 7 and the gate second insulating gate oxide layer 18 can be effectively shielded. At the same time, the grounded p+ shielding layer 4 also reduces the electric field strength by the electric potential on the sides of the first insulating oxide layer 7 and the second insulating oxide layer 18, and better improves the first insulating oxide layer 7 in the first trench 21 and the second insulating oxide layer 18 in the second trench 22. Meanwhile, the gate-drain charge of the field effect transistor is reduced due to the shielding effect of the ground p+ shielding layer 4. With the reduction of on-resistance and gate-drain charge, the high-frequency figure of merit obtainable by the silicon carbide field effect transistor device of the present invention is capable of reducing switching losses, which is significantly reduced compared to conventional silicon carbide trench gate metal-oxide semiconductor field effect transistor devices.
Further, the semiconductor device further comprises a mesa structure which is in contact with the corresponding outer side walls of the first cell groove 21 and the second cell groove 22, wherein the mesa structure comprises an N-type current expansion layer 10 arranged in the N-type silicon carbide epitaxial layer 3 and a P-type silicon carbide base region 11 positioned on the N-type current expansion layer 10, and the P-type silicon carbide base region 11 is adjacent to the N-type current expansion layer 10;
An n+ silicon carbide source region 12 and a p+ silicon carbide contact region 13 are disposed on the P-type silicon carbide base region 11, the n+ silicon carbide source region 12 and the p+ silicon carbide contact region 13 are adjacent, the source metal layer 14 is in ohmic contact with the n+ silicon carbide source region 12 and the p+ silicon carbide contact region 13, and the n+ silicon carbide source region 12, the N-type current spreading layer 10 and the P-type silicon carbide base region 11 are in contact with corresponding outer sidewalls of the cell first trench 21 and the cell second trench 22.
In the embodiment of the present invention, on the cross section of the field effect transistor, two sides of the cell have an adaptively connected mesa structure, wherein the mesa connector includes an N-type current expansion layer 10 and a P-type silicon carbide base region 11 located on the N-type current expansion layer 10, the P-type silicon carbide base region 11 is adjacent to the N-type circuit expansion layer 10, the N-type current expansion layer 10 is located above the bottoms of the first trench 21 and the second trench 22 of the cell, and generally, the bottom surface of the N-type current expansion layer 10 is not lower than the upper surface of the p+ source region 6. An N+ silicon carbide source region 12 and a P+ silicon carbide contact region 13 are arranged on the P-type silicon carbide base region 11, the N+ silicon carbide source region 12 and the P+ silicon carbide contact region 13 are adjacent to the P-type silicon carbide base region 11, and the P+ silicon carbide contact region 13 is adjacent to the N+ silicon carbide source region 12.
For the first cell groove 21, a mesa structure adapted to be connected with the first cell groove 21 is specifically connected with a sidewall of the first cell groove 21, which is correspondingly far away from the second cell groove 22; for the cell second trench 22, a mesa structure adapted to be connected to the cell second trench 22 is specifically connected to a sidewall of the cell second trench 22 corresponding to a sidewall remote from the cell first trench 21. In particular, in the mesa structure connected to the first cell trench 21, the N-type current spreading layer 10, the P-type silicon carbide base region 11, and the n+ silicon carbide source region 12 are all in contact with the outer sidewall of the first cell trench 21. In the mesa structure connected with the cell second trench 22, the N-type current spreading layer 10, the P-type silicon carbide base region 11 and the N+ silicon carbide source region 12 are all in contact with the outer sidewall of the cell second trench 22
Further, a back drain metal 1 is disposed on the back surface of the N-type silicon carbide substrate 2, and the back drain metal 1 is in ohmic contact with the N-type silicon carbide substrate 2. In the embodiment of the present invention, the back drain metal 1 may be of a conventional metal type, and the drain electrode of the field effect transistor may be formed by the back drain metal 1, and the manner of forming the drain electrode by using the back drain metal 1 is consistent with the conventional manner, which is well known to those skilled in the art, and will not be described herein.
The trench silicon carbide field effect transistor can be prepared by the following process steps, and the preparation method specifically comprises the following steps:
Step 1, providing an N-type silicon carbide substrate 2 and an N-type silicon carbide epitaxial layer 3 arranged on the N-type silicon carbide substrate 2, and preparing a P+ shielding layer 4, a cell groove and a mesa structure which is connected with the cell groove in an adapting way in the N-type silicon carbide epitaxial layer 3, wherein the cell groove comprises a cell first groove 21 and a cell second groove 22, the P+ shielding layer 4 covers the groove bottom outer walls of the cell first groove 21 and the cell second groove 21, a P+ inter-groove shielding connecting column 23 on the P+ shielding layer 4 stretches into a space between the cell first groove 21 and the cell second groove 22, the P+ inter-groove shielding connecting column 23 contacts with the side walls corresponding to the cell first groove 21 and the cell second groove 22, and the mesa structure contacts with the outer side walls corresponding to the cell first groove 21 and the cell second groove 22;
Specifically, the structure prepared in step 1 may be prepared by different process methods, as shown in fig. 2 to 8, which is a specific process, and specifically includes the following steps:
step 1.1, providing an N-type silicon carbide substrate 2, and growing an N-type silicon carbide epitaxial layer 3 on the N-type silicon carbide substrate 2;
As shown in fig. 2, a desired N-type silicon carbide substrate 2 is selected, and an N-type silicon carbide epitaxial layer 3 can be obtained by using a conventional epitaxial growth process, where the thickness of the N-type silicon carbide epitaxial layer 3 may be 12 μm, the doping concentration is 8×10 15cm-3, and the specific conditions of the N-type silicon carbide substrate 2 and the N-type silicon carbide epitaxial layer 3 may be selected according to actual needs, and are in particular consistent with the conventional one, and will not be repeated here.
Step 1.2, performing N-type impurity ion implantation above the N-type silicon carbide epitaxial layer 3 to obtain an N-type current expansion base layer 19 penetrating through the N-type silicon carbide epitaxial layer 3 in the N-type silicon carbide epitaxial layer 3;
Specifically, the N-type current spreading base layer 19 can be obtained by an impurity ion implantation process commonly used in the art, such as implanting phosphorus ions, and the N-type current spreading base layer 19 penetrates through the N-type silicon carbide epitaxial layer 3, as shown in fig. 3. The thickness of the N-type current spreading substrate 19 may be 0.4 μm, the doping concentration may be 1×10 17cm-3, and of course, the specific thickness and doping concentration of the N-type current spreading substrate 19 may be selected according to actual needs, which will not be described herein.
Step 1.3, performing P-type impurity ion implantation above the N-type silicon carbide epitaxial layer 3 to obtain a P-type silicon carbide base layer 20, wherein the P-type silicon carbide base layer 20 is adjacent to the N-type current expansion base layer 19;
Specifically, the P-type impurity ion implantation is performed by using an impurity ion process commonly used in the art, and the P-type impurity ion may be boron ion, so that a P-type silicon carbide base layer 20 can be obtained in the N-type current spreading base layer 19, and after the P-type silicon carbide base layer 20 is obtained, the P-type silicon carbide base layer 20 and the N-type current spreading base layer 19 are adjacent to each other, as shown in fig. 4.
Step 1.4, performing P-type impurity ion implantation to obtain a p+ silicon carbide contact region 13 in the P-type silicon carbide base region layer 20;
Specifically, the p+ silicon carbide contact region 13 can be obtained by using a conventional ion implantation process, where the doping concentration of the p+ silicon carbide contact region 13 is greater than that of the P-type silicon carbide base region layer 20, as shown in fig. 5. In the preparation of the p+ silicon carbide contact region 13, a mask is specifically required, that is, the p+ silicon carbide contact region 13 needs to be implanted and formed in a desired location area, and specific processes are well known to those skilled in the art and will not be described herein.
Step 1.5, implanting N-type impurity ions to obtain an N+ silicon carbide source region 12 positioned in the P-type silicon carbide base region layer 20, wherein the N+ silicon carbide source region 12 is adjacent to an adjacent P+ silicon carbide contact region 13;
Specifically, by using an ion implantation method commonly used in the art, the n+ silicon carbide source region 12 can be obtained, and the n+ silicon carbide source region 12 is adjacent to the p+ silicon carbide contact region 13, as shown in fig. 6, that is, when the n+ silicon carbide source region 12 is obtained, a mask is also required, and a specific process is well known to those skilled in the art and is not repeated herein.
Step 1.6, after the groove is etched by using a groove etching process, a cell groove is obtained, wherein the cell groove comprises a cell first groove 21 and a cell second groove 22, the cell first groove 21 and the cell second groove 22 penetrate through a P-type silicon carbide base region layer 20 and an N-type current expansion base layer 19 so as to respectively form a P-type silicon carbide base region 11 and an N-type current expansion layer 10 through the P-type silicon carbide base region layer 20 and the N-type current expansion base layer 19, the bottoms of the cell first groove 21 and the cell second groove 22 corresponding to the groove are positioned below the N-type current expansion layer 10, and a mesa structure can be formed by using the P-type silicon carbide base region 11, the N-type current expansion layer 10 and a P+ silicon carbide contact region 13 adjacent to the N+ silicon carbide source region 12 on the P-type silicon carbide base region 11;
Specifically, the trench etching process is used to perform trench etching to obtain the required cell trench, that is, the cell first trench 21 and the cell second trench 22 can be obtained simultaneously, and the process of obtaining the cell first trench 21 and the cell second trench 22 by trench etching is consistent with the existing process, which is well known to those skilled in the art, and will not be repeated here. The respective depths of the first cell grooves 21 and the second cell grooves 22 may be 1.8 μm, and the respective widths may be 1.2 μm, and of course, the respective dimensions may be selected according to actual needs, which will not be described herein.
In the embodiment of the invention, the bottoms of the first cell grooves 21 and the second cell grooves 22 are positioned below the N-type current spreading base layer 19, i.e., the first cell grooves 21 and the second cell grooves 22 vertically extend in the N-type silicon carbide epitaxial layer 3 and penetrate through the P-type silicon carbide base layer 20 and the N-type current spreading base layer 19. When the first cell trench 21 and the second cell trench 22 are used to form the P-type silicon carbide base layer 20 and the N-type current spreading base layer 19, the P-type silicon carbide base layer 20 and the N-type current spreading base layer 19 can be divided, and after the division, the N-type current spreading layer 10 and the P-type silicon carbide base region 11 can be formed, wherein the N-type current spreading layer 10 can be obtained by dividing the N-type current spreading base layer 19, and the P-type silicon carbide base region 11 can be obtained by dividing the P-type silicon carbide base layer 20. The N-type current spreading layer 10, the P-type silicon carbide base region 11 on the N-type current spreading layer 10, and the p+ silicon carbide contact region 13 located on the P-type silicon carbide base region 11 and adjacent to the n+ silicon carbide source region 12 can form a mesa structure, as shown in fig. 7.
In the formed mesa structure, the N-type current spreading layer 10, the P-type silicon carbide base region 11, and the n+ silicon carbide source region 12 can be in contact with the corresponding outer sidewalls of the first cell trench 21 and the second cell trench 22, and the connection and matching between the mesa structure and the first cell trench 21 and the second cell trench 22 may be referred to the above description, and will not be repeated here.
Step 1.7, the p+ shielding layer 4 and the p+ inter-groove shielding connection column 23 connected with the p+ shielding layer 4 can be obtained in the N-type silicon carbide epitaxial layer 3 through the required ion implantation process and junction pushing, the p+ shielding layer 4 can cover the bottoms of the corresponding first groove 21 and the corresponding second groove 22 of the cell, the p+ inter-groove shielding connection column 23 can extend into the space between the first groove 21 and the second groove 22 of the cell, and the p+ inter-groove shielding connection column 23 contacts with the corresponding side walls of the first groove 21 and the second groove 22 of the cell.
In the embodiment of the invention, the p+ shielding layer 4 and the p+ inter-slot shielding connection column 23 can be prepared by utilizing the conventional P-type ion implantation and high-temperature junction pushing, the p+ inter-slot shielding connection column 23 is vertically distributed, the p+ inter-slot shielding connection column 23 enters between the first cell groove 21 and the second cell groove 22, and the top end of the p+ inter-slot shielding connection column 23 is positioned above the corresponding bottoms of the first cell groove 21 and the second cell groove 22. The p+ shielding layer 4 and the p+ inter-groove shielding connection column 23 are formed by the same process, and the p+ shielding layer 4 and the p+ inter-groove connection column 23 can cover the corresponding ancient corners at the bottoms of the first groove 21 and the second groove 22 of the cell, as shown in fig. 8. The process for preparing the p+ shield layer 4 and the p+ inter-trench shield connection post 23 is well known to those skilled in the art, and will not be described herein.
In addition, the step 1 may be implemented in another manner, and specifically includes the following steps:
Step a, providing an N-type silicon carbide substrate 2, and growing an N-type silicon carbide epitaxial layer 3 on the N-type silicon carbide substrate 2, wherein in the process of growing the N-type silicon carbide epitaxial layer 3, P-type impurity ions are injected and pushed to form a P+ shielding base layer in the N-type silicon carbide epitaxial layer 3;
Specifically, the specific case of the N-type silicon carbide substrate 2 may refer to the above description, and the p+ shielding base layer may be prepared by performing P-type impurity ions and junction pushing in the N-type silicon carbide epitaxial layer 3 before the N-type silicon carbide epitaxial layer 3 is grown to a desired height, and the manner of preparing the p+ shielding base layer is consistent with the existing manner, which is well known to those skilled in the art, and is not repeated herein. After the p+ shielding base layer is prepared, the required epitaxial growth process is continued, and the N-type silicon nitride epitaxial layer 3 is manufactured to the required thickness, which is consistent with the prior art, and is not repeated here.
Of course, the thickness of the p+ shield base layer is generally consistent with the thickness of the p+ shield layer 4 prepared later, so that the p+ shield layer 4 and the p+ inter-slot shield connection post 23 can be obtained through the p+ shield base layer.
Step b, performing N-type impurity ion implantation above the N-type silicon carbide epitaxial layer 3 to obtain an N-type current expansion base layer 19 penetrating through the N-type silicon carbide epitaxial layer 3 in the N-type silicon carbide epitaxial layer 3;
specifically, the manner and process of obtaining the N-type current spreading base layer 19 may refer to the above description, and will not be repeated here.
Step c, performing P-type impurity ion implantation above the N-type silicon carbide epitaxial layer 3 to obtain a P-type silicon carbide base layer 20, wherein the P-type silicon carbide base layer 20 is adjacent to the N-type current expansion base layer 19;
Specifically, the process and manner of obtaining the P-type silicon carbide base layer 20 may refer to the above description, and will not be repeated here.
Step d, P-type impurity ion implantation is carried out so as to obtain a P+ silicon carbide contact region 13 in the P-type silicon carbide base region layer 20;
Specifically, the process and manner of preparing the p+ silicon carbide contact region 13 may refer to the above description, and will not be repeated here.
Step e, implanting N-type impurity ions to obtain an N+ silicon carbide source region 12 positioned in the P-type silicon carbide base region layer 20, wherein the N+ silicon carbide source region 12 is adjacent to an adjacent P+ silicon carbide contact region 13;
specifically, the process and manner of preparing the n+ silicon carbide source region 12 may be referred to in the above description, and will not be described herein.
Step f, after the groove etching process is utilized to obtain a cell groove, the cell groove comprises a cell first groove 21 and a cell second groove 22, wherein the cell first groove 21 and the cell second groove 22 penetrate through the P-type silicon carbide base region layer 20 and the N-type current expansion base layer 19 so as to respectively form a P-type silicon carbide base region 11 and an N-type current expansion layer 10 through the P-type silicon carbide base region layer 20 and the N-type current expansion base layer 19, the corresponding groove bottoms of the cell first groove 21 and the cell second groove 22 are positioned below the N-type current expansion layer 10, and a mesa structure can be formed by utilizing the P-type silicon carbide base region 11, the N-type current expansion layer 10 and a P+ silicon carbide contact region 13 positioned on the P-type silicon carbide base region 11 and adjacent to the N+ silicon carbide source region 12;
Meanwhile, the P+ shielding base layer is utilized to form a P+ shielding layer 4 and a P+ inter-groove shielding connecting column 23, the P+ shielding layer 4 can cover the bottoms of the corresponding first groove 21 and the corresponding second groove 22, the P+ inter-groove shielding connecting column 23 can extend into the space between the first groove 21 and the second groove 22, and the P+ inter-groove shielding connecting column 23 is contacted with the corresponding side walls of the first groove 21 and the second groove 22.
Specifically, the specific process of etching the grooves and the like may refer to the above description, when the grooves are etched to obtain the first cell groove 21 and the second cell groove 22, the positions and depths of the first cell groove 21 and the second cell groove 22 can be matched with the p+ shielding base layer, and the bottoms of the first cell groove 21 and the second cell groove 22 are located in the p+ shielding base layer, so that the p+ shielding base layer can be used to form the p+ shielding layer 4 and the p+ inter-groove shielding connection column 23, and the specific relationship between the p+ shielding layer 4 and the p+ inter-groove shielding connection column 23 and the first cell groove 21 and the second cell groove 22 may refer to the above description, which is not repeated herein.
In addition, the mesa structure and the specific matching forms with the first cell trench 21 and the second cell trench 22 are also referred to the above description, and will not be described herein.
Step 2, disposing a gate first insulating oxide 29 on the side wall and the bottom wall of the first cell trench 21, wherein the gate first insulating oxide 29 covers the side wall and the bottom wall of the first cell trench 21, disposing a gate second insulating oxide 30 on the side wall and the bottom wall of the second cell trench 22, and the gate second insulating oxide 30 covers the side wall and the bottom wall of the second cell trench 22;
Specifically, the gate first insulating oxide 29 and the gate second insulating oxide 30 are silicon dioxide layers, and may be obtained by conventional thermal oxidation growth, as shown in fig. 9. The thickness of the gate first insulating oxide 29 and the gate second insulating oxide 30 may be 40nm, and the specific thickness may be selected according to needs, which will not be described here.
Step 3, depositing gate polysilicon to obtain polysilicon filling bodies 31 filled in the first cell grooves 21 and the second cell grooves 22;
Specifically, a common polysilicon deposition process is adopted to obtain a polysilicon filling body 31, and the polysilicon filling body 31 can be filled in the first cell trench 21 and the second cell trench 22, and of course, the polysilicon filling body 31 also covers the upper surface of the N-type silicon carbide epitaxial layer 3.
Step 4, etching the polysilicon filling body 31 in the first cell trench 21 and the second cell trench 22 to obtain the first conductive polysilicon 8, the first insulating spacer filling trench 24 and the first insulating oxide layer 7; at the same time, gate second conductive polysilicon 17, gate second insulating spacer fill trench 25 and gate second insulating oxide 18 within cell second trench 22 can be obtained;
Specifically, the polysilicon filling body 31 is filled by a conventional etching process, so that the polysilicon filling body 31 located only in the cell first trench 21 and the cell second trench 22 can be obtained, as shown in fig. 10.
Thereafter, etching is continued on the corresponding polysilicon filling 31 in the cell first trench 21, the cell second trench 22, so as to obtain the gate first conductive polysilicon 8 located in the cell first trench 21 and the gate second conductive polysilicon 17 located in the cell second trench 22. Meanwhile, the gate first insulating oxide layer 7 can be obtained by using the gate first insulating oxide 29 in the cell first trench 21, and the gate second insulating oxide layer 18 can be obtained by using the gate second insulating oxide 30 in the cell second trench 22.
In addition, during etching, the polysilicon filling body 31 and the gate first insulating oxide 29 on the side adjacent to the cell second trench 22 in the cell first trench 21 are etched away to form the gate first insulating spacer filling groove 24, and similarly, the gate second insulating spacer filling groove 25 is obtained in the cell second trench 22, as shown in fig. 11. The top end of the first conductive polysilicon 8 is located below the notch of the first cell trench 21, and the top end of the second conductive polysilicon 17 is located below the notch of the second cell trench 22, that is, when the first insulating spacer filling trench 24 is etched to obtain the first insulating spacer filling trench 24, the top end of the polysilicon filling body 31 in the first cell trench 21 is etched to obtain the first conductive polysilicon 8; the situation of the gate second conductive polysilicon 17 in the cell second trench 22 corresponds to the situation of the gate first conductive polysilicon 8 in the cell first trench 21, and will not be described here again.
Of course, the bottom of the gate first insulating spacer filled trench 24 has a filled trench first transition region 26, and the filled trench first transition region 26 is arcuate. The bottom of the gate second insulating spacer filling groove 25 is provided with a second transition area 27 in the filling groove, and the second transition area 27 in the filling groove is also arc-shaped.
Step 5, depositing an insulating isolation material to obtain a grid first insulating isolator 9 and a grid second insulating isolator 16, wherein the grid first insulating isolator 9 is filled in a grid first insulating isolator filling groove 24 and can cover grid first conductive polysilicon 8, and the grid first insulating isolator 9 is in contact with a grid first insulating oxide layer 7; the gate second insulating spacer 16 is filled in the gate second insulating spacer filling groove 25 and can cover the gate second conductive polysilicon 17, and the gate second insulating spacer 16 is in contact with the gate second insulating oxide layer 18;
specifically, the insulating isolation material is typically silicon dioxide, the gate first insulating isolator 9 is filled in the gate first insulating isolator filling groove 24, and after the gate first insulating isolator 9 is filled in the gate first insulating isolator filling groove 24, the corresponding side surface of the gate first conductive polysilicon 8 and the upper surface of the gate first conductive polysilicon 8 can be covered by the gate first insulating isolator 9; similarly, the gate second insulating spacers 16 can cover the respective sides of the gate second conductive polysilicon 16 and the upper surface of the gate second conductive polysilicon 16.
In the embodiment of the invention, the first grid insulating isolator 9 is contacted with the first grid insulating oxide layer 7, and the first grid conductive polysilicon 8 can be effectively covered by the first grid insulating isolator 9 and the first grid insulating oxide layer 7; similarly, effective coverage of the gate second conductive polysilicon 17 can be achieved by the gate second insulating spacer 16 and the gate second insulating oxide layer 18, as shown in fig. 12.
Step 6, performing required trench etching to obtain a source connection column groove 28, wherein the source connection column groove 28 is positioned between the cell first trench 21 and the source second trench 22, the side walls of the source connection column groove 28 are respectively formed through the grid first insulating isolator 9 and the grid second insulating isolator 16, and the bottom of the source connection column groove 28 is level with the bottom of the grid first insulating isolator filling groove 24 and the grid second insulating isolator filling groove 25;
Specifically, during etching, the area between the first cell trench 21 and the second cell trench 22 needs to be etched to obtain source connection pillars 28, where the source connection pillars 28 are vertically distributed, and the depth of the source connection pillars 28 is generally the same as the corresponding depth of the gate first insulating spacer filling trench 24 and the gate second insulating spacer filling trench 25. After etching, the first gate insulating spacer 9 and the second gate insulating spacer 16 respectively form sidewalls of the source connecting pillar trench 28, and the bottoms of the source connecting pillar trench 28 are flush with the bottoms of the first gate insulating spacer 9 and the second gate insulating spacer 16, as shown in fig. 13.
Step 7, implanting P-type impurity ions right above the source connection column groove 28 to obtain a p+ doped channel region 5 and a p+ source region 6, wherein the p+ doped channel region 5 is adjacent to the p+ source region 6 and the p+ inter-groove shielding connection column 23, the p+ source region 6 is located right above the p+ doped channel region 5, and the p+ doped channel region 5 and the p+ source region 6 are respectively contacted with the corresponding side walls of the cell first groove 21 and the cell second groove 22; the bottom of the P+ doped channel region 5 is not lower than the bottoms of the grid first conductive polysilicon 8 and the grid second conductive polysilicon 17;
Specifically, a conventional P-type impurity ion implantation may be used to align the bottom of the source connection pillar trench 28 during the implantation, so as to form the p+ doped channel region 5 and the p+ source region 6 directly below the bottom of the source connection pillar trench 28, wherein the doping concentration of the p+ source region 6 is greater than that of the p+ doped channel region 5, and of course, in order to form the p+ doped channel region 5 and the p+ source region 6, a two-step doping process is required, as shown in fig. 14 and 15.
The lower part of the P+ doped channel region 5 is connected with the top end of the P+ inter-groove shielding connecting column 23, the upper end of the P+ doped channel region 5 is contacted with the P+ source region 6, and the P+ source region 6 is connected with the bottom of the source connecting column groove 28. The P+ doped channel region 5 and the P+ source region 6 are respectively contacted with the corresponding side walls of the cell first groove 21 and the cell second groove 22; the bottom of the P+ doped channel region 5 is not lower than the bottoms of the grid first conductive polysilicon 8 and the grid second conductive polysilicon 17; the p+ doped channel region 5 is isolated from the gate first conductive polysilicon 8 by the gate first insulating oxide 7 and the p+ doped channel region 5 is isolated from the gate second conductive polysilicon 17 by the gate second insulating oxide 18. Similarly, the p+ source region 6 is isolated from the gate first conductive polysilicon 8 by the gate first insulating oxide 7, and the p+ source region 6 is isolated from the gate second conductive polysilicon 17 by the gate second insulating oxide 18.
Step 8, performing metal deposition right above the N-type silicon carbide epitaxial layer 3 to obtain a source metal layer 14 and an inter-channel source connection post 15 filled in a source connection post groove 28, wherein the inter-channel source connection post 15 is electrically connected with the source metal layer 14, the inter-channel source connection post 15 is in ohmic contact with the p+ source region 6, the gate first conductive polysilicon 8 in the cell first groove 21 is insulated and isolated from the inter-channel source connection post 15 and the source metal layer 14 above the cell first groove 21 through a gate first insulating isolator 9, and the gate second conductive polysilicon 17 in the cell second groove 22 is insulated and isolated from the inter-channel source connection post 15 and the source metal layer 14 above the cell second groove 22 through a gate second insulating isolator 16;
Specifically, the source metal layer 14 and the inter-trench source connection pillars 15 can be obtained by a metal deposition process commonly used in the art, wherein the inter-trench source connection pillars 15 are filled in the source connection pillar trenches 28, and the source metal layer 14 is located above the corresponding notches of the cell first trench 21 and the cell second trench 22. The inter-trench source connection pillars 15 can be in ohmic contact with the p+ source regions 6 after filling the source connection pillar trenches 28. The gate first conductive polysilicon 8 in the first cell trench 21 is insulated from the inter-channel source connection pillars 15 by the gate first insulating spacers 9 and the source metal layer 14 above the first cell trench 21, and the gate second conductive polysilicon 17 in the second cell trench 22 is insulated from the inter-channel source connection pillars 15 by the gate second insulating spacers 16 and the source metal layer 14 above the second cell trench 22, as shown in fig. 16.
In particular, the thicknesses of the first gate insulating spacer 9 and the second gate insulating spacer 16 in contact with the inter-trench source connection pillar 15 are greater than the thicknesses of the first gate insulating oxide layer 7 and the second gate insulating oxide layer 18.
In addition, the source metal layer 14 is in ohmic contact with the p+ silicon carbide contact region 13 and the n+ silicon carbide source region 12, and a source electrode of the field effect transistor can be formed by using the source metal layer 14. Of course, the gate electrode of the field effect transistor can be formed by using the first polysilicon 8 and the second polysilicon 17 in cooperation with the gate metal layer, which is consistent with the prior art, and will not be described herein.
And 9, manufacturing a back drain metal 1 on the back of the N-type silicon carbide substrate 2, wherein the back drain metal 1 is in ohmic contact with the N-type silicon carbide substrate 2.
Specifically, the common technical means commonly used in the technical field are adopted to obtain the back drain metal 1, the back drain metal 1 is in ohmic contact with the N-type silicon carbide substrate 2, the drain electrode of the field effect transistor can be obtained by utilizing the back drain metal 1, and the method is consistent with the prior art, and is not repeated here.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (12)
1. A trench type silicon carbide field effect transistor includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide epitaxial layer disposed on a front surface of the first conductivity type silicon carbide substrate, and a source metal layer for forming a source electrode; arranging a plurality of cell in the first conductive type silicon carbide epitaxial layer, wherein the cell comprises a cell groove in the first conductive type silicon carbide epitaxial layer; a second conductive type shielding layer is arranged below the bottom of the cellular groove, and the second conductive type shielding layer covers the bottom of the cellular groove; the method is characterized in that:
On the section of the field effect transistor, the cell groove comprises a cell first groove and a cell second groove corresponding to the cell first groove, a second conductive type inter-groove shielding connecting column on the second conductive type shielding layer stretches into the space between the cell first groove and the cell second groove, and the second conductive type inter-groove shielding connecting column is contacted with the side wall corresponding to the cell first groove and the cell second groove;
The inter-groove source electrode connecting column is electrically connected with the source electrode metal layer, the inter-groove source electrode connecting column is positioned between the first groove of the cell and the second groove of the cell, and the source electrode metal layer can be electrically connected with the inter-groove shielding connecting column of the second conductive type through the inter-groove source electrode connecting column so as to enable the source electrode metal layer to be electrically connected with the shielding layer of the second conductive type; the first conductive polysilicon of the grid in the first groove of the cell is insulated and isolated from the source electrode connecting column between the grooves through the first insulating isolator of the grid and the source electrode metal layer positioned above the first groove of the cell, and the second conductive polysilicon of the grid in the second groove of the cell is insulated and isolated from the source electrode connecting column between the grooves through the second insulating isolator of the grid and the source electrode metal layer positioned above the second groove of the cell; the top of the second conduction type inter-groove shielding connecting column between the first cell groove and the second cell groove is not lower than the corresponding bottom ends of the first grid conduction polysilicon and the second grid conduction polysilicon;
A second conduction type doped channel region and a second conduction type source region positioned on the second conduction type doped channel region are arranged on the second conduction type inter-slot shielding connecting column, and the second conduction type doped channel region is adjacent to the second conduction type source region and the second conduction type inter-slot shielding connecting column; the second conduction type source region is in ohmic contact with the inter-groove source connecting column, and the inter-groove source connecting column is electrically connected with the second conduction type inter-groove shielding connecting column through the second conduction type source region and the second conduction type doping channel region;
the second conduction type doped channel region and the second conduction type source region are respectively contacted with the corresponding side walls of the first cell groove and the second cell groove, and are isolated from the first conductive polysilicon of the grid in the first cell groove through the first insulating oxide layer of the grid covering the inner side wall and the bottom wall of the first cell groove; the second conduction type doped channel region and the second conduction type source region are isolated from the grid second conductive polysilicon in the cell second groove through a grid second insulating oxide layer covering the inner side wall and the bottom wall of the cell second groove.
2. The trench silicon carbide field effect transistor according to claim 1, wherein: the grid first insulating oxide layer is connected with the grid first insulating isolator so as to cover the grid first conductive polysilicon by using the grid first insulating oxide layer and the grid first insulating isolator; the grid electrode second insulating oxide layer is connected with the grid electrode second insulating isolator so that the grid electrode second conductive polysilicon can be covered by the grid electrode second insulating oxide layer and the grid electrode second insulating isolator.
3. The trench silicon carbide field effect transistor according to claim 1 or 2, wherein: the semiconductor device further comprises a mesa structure which is in contact with the corresponding outer side walls of the first cell groove and the second cell groove, wherein the mesa structure comprises a first conductive type current expansion layer arranged in the first conductive type silicon carbide epitaxial layer and a second conductive type silicon carbide base region positioned on the first conductive type current expansion layer, and the second conductive type silicon carbide base region is adjacent to the first conductive type current expansion layer;
and arranging a first conductive type silicon carbide source region and a second conductive type silicon carbide contact region on the second conductive type silicon carbide base region, wherein the first conductive type silicon carbide source region and the second conductive type silicon carbide contact region are adjacent, the source metal layer is in ohmic contact with the first conductive type silicon carbide source region and the second conductive type silicon carbide contact region, and the first conductive type silicon carbide source region, the first conductive type current expansion layer and the second conductive type silicon carbide base region are in contact with corresponding outer side walls of the first groove of the cell and the second groove of the cell.
4. The trench silicon carbide field effect transistor according to claim 1 or 2, wherein: and arranging a back drain metal on the back surface of the first conductive type silicon carbide substrate, wherein the back drain metal is in ohmic contact with the first conductive type silicon carbide substrate.
5. The trench silicon carbide field effect transistor according to claim 1 or 2, wherein: the second conduction type inter-groove shielding connecting column and the second conduction type shielding layer are the same process step layer; the second insulating isolator of the grid electrode and the first insulating isolator of the grid electrode are the same process step layer, and the second insulating isolator of the grid electrode and the first insulating isolator of the grid electrode are silicon dioxide.
6. The trench silicon carbide field effect transistor according to claim 2, wherein: the first insulating oxide layer of the grid electrode and the second insulating oxide layer of the grid electrode are the same process step layer; the thickness of the first grid insulation isolator and the second grid insulation isolator contacted with the source electrode connecting column between the grooves is larger than that of the first grid insulation oxide layer and the second grid insulation oxide layer.
7. The preparation method of the trench silicon carbide field effect transistor is characterized by comprising the following steps of:
Step 1, providing a first conductive type silicon carbide substrate and a first conductive type silicon carbide epitaxial layer arranged on the first conductive type silicon carbide substrate, preparing a second conductive type shielding layer, a cell groove and a mesa structure which is connected with the cell groove in an adapting way in the first conductive type silicon carbide epitaxial layer, wherein the cell groove comprises a cell first groove and a cell second groove, the second conductive type shielding layer covers the groove bottom outer wall corresponding to the cell first groove and the cell second groove, a second conductive type inter-groove shielding connecting column on the second conductive type shielding layer extends into the space between the cell first groove and the cell second groove, the second conductive type inter-groove shielding connecting column contacts with the side wall corresponding to the cell first groove and the cell second groove, and the mesa structure contacts with the outer side wall corresponding to the cell first groove and the cell second groove;
Step 2, arranging a grid first insulating oxide on the side wall and the bottom wall of the first cell groove, wherein the grid first insulating oxide covers the side wall and the bottom wall of the first cell groove, arranging a grid second insulating oxide on the side wall and the bottom wall of the second cell groove, and the grid second insulating oxide covers the side wall and the bottom wall of the second cell groove;
Step 3, depositing gate polysilicon to obtain polysilicon filling bodies filled in the first grooves of the cells and the second grooves of the cells;
Step 4, etching the polysilicon filling bodies in the first cell groove and the second cell groove to obtain grid first conductive polysilicon, grid first insulating spacer filling grooves and grid first insulating oxide layers in the first cell groove; meanwhile, gate second conductive polysilicon, a gate second insulating spacer filling groove and a gate second insulating oxide layer which are positioned in the cell second groove can be obtained;
Step 5, depositing an insulating isolation material to obtain a grid first insulating isolator and a grid second insulating isolator, wherein the grid first insulating isolator is filled in a grid first insulating isolator filling groove and can cover grid first conductive polysilicon, and the grid first insulating isolator is in contact with a grid first insulating oxide layer; the grid electrode second insulating isolator is filled in the grid electrode second insulating isolator filling groove and can cover the grid electrode second conductive polysilicon, and the grid electrode second insulating isolator is in contact with the grid electrode second insulating oxide layer;
step 6, carrying out required groove etching to obtain a source electrode connecting column groove, wherein the source electrode connecting column groove is positioned between the first cell groove and the second cell groove, the side walls of the source electrode connecting column groove are respectively formed through the first grid insulating isolator and the second grid insulating isolator, and the groove bottom of the source electrode connecting column groove is flush with the groove bottom of the filling groove of the first grid insulating isolator and the groove bottom of the filling groove of the second grid insulating isolator;
Step 7, implanting second conductivity type impurity ions right above the source electrode connecting column groove so as to obtain a second conductivity type doped channel region and a second conductivity type source region, wherein the second conductivity type doped channel region is adjacent to the second conductivity type source region and a shielding connecting column between the second conductivity type grooves, the second conductivity type source region is located right above the second conductivity type doped channel region, and the second conductivity type doped channel region and the second conductivity type source region are respectively contacted with corresponding side walls of the first groove of the cell and the second groove of the cell; the bottom of the second conduction type doped channel region is not lower than the bottoms of the first conduction polysilicon and the second conduction polysilicon of the grid electrode;
step 8, performing metal deposition right above the first conductive type silicon carbide epitaxial layer to obtain a source metal layer and an inter-groove source electrode connecting column filled in a source electrode connecting column groove, wherein the inter-groove source electrode connecting column is electrically connected with the source metal layer, the inter-groove source electrode connecting column is in ohmic contact with a second conductive type source region, grid first conductive polysilicon in a cell first groove is isolated from the inter-groove source electrode connecting column through a grid first insulating insulator and the source metal layer positioned above the cell first groove, and grid second conductive polysilicon in a cell second groove is isolated from the inter-groove source electrode connecting column through a grid second insulating insulator and the source metal layer positioned above the cell second groove;
and 9, manufacturing back drain metal on the back of the first conductive type silicon carbide substrate, wherein the back drain metal is in ohmic contact with the first conductive type silicon carbide substrate.
8. The method for manufacturing a trench silicon carbide field effect transistor according to claim 7, wherein the step 1 specifically comprises the following steps:
step 1.1, providing a first conductive type silicon carbide substrate, and growing on the first conductive type silicon carbide substrate to obtain a first conductive type silicon carbide epitaxial layer;
step 1.2, performing first conductivity type impurity ion implantation above the first conductivity type silicon carbide epitaxial layer to obtain a first conductivity type current spreading base layer penetrating through the first conductivity type silicon carbide epitaxial layer in the first conductivity type silicon carbide epitaxial layer;
step 1.3, performing second conductivity type impurity ion implantation above the first conductivity type silicon carbide epitaxial layer to obtain a second conductivity type silicon carbide base layer, wherein the second conductivity type silicon carbide base layer is adjacent to the first conductivity type current expansion base layer;
step 1.4, carrying out second conductivity type impurity ion implantation to obtain a second conductivity type silicon carbide contact region in the second conductivity type silicon carbide region layer;
Step 1.5, implanting first conductivity type impurity ions to obtain a first conductivity type silicon carbide source region in the second conductivity type silicon carbide region layer, wherein the first conductivity type silicon carbide source region is adjacent to an adjacent second conductivity type silicon carbide contact region;
Step 1.6, after the groove is etched by utilizing a groove etching process, a cell groove is obtained, wherein the cell groove comprises a cell first groove and a cell second groove, the cell first groove and the cell second groove penetrate through a second conductive type silicon carbide base layer and a first conductive type current expansion base layer so as to respectively form a second conductive type silicon carbide base region and a first conductive type current expansion layer through the second conductive type silicon carbide base layer and the first conductive type current expansion base layer, the groove bottoms of the cell first groove and the cell second groove corresponding to the first conductive type current expansion layer are positioned below the first conductive type current expansion layer, and a mesa structure can be formed by utilizing the second conductive type silicon carbide base region, the first conductive type current expansion layer and a second conductive type silicon carbide contact region adjacent to the first conductive type silicon carbide source region on the second conductive type silicon carbide base region;
Step 1.7, a second conductive type shielding layer and a second conductive type inter-groove shielding connecting column connected with the second conductive type shielding layer can be obtained in the first conductive type silicon carbide epitaxial layer through a required ion implantation process and a pushing junction, the second conductive type shielding layer can cover cell first grooves and corresponding groove bottoms of the cell second grooves, the second conductive type inter-groove shielding connecting column can extend into the first grooves and the second grooves of the cell, and the second conductive type inter-groove shielding connecting column is in contact with corresponding side walls of the first grooves and the second grooves of the cell.
9. The method for manufacturing a trench silicon carbide field effect transistor according to claim 7, wherein the step 1 specifically comprises the following steps:
step a, providing a first conductive type silicon carbide substrate, growing a first conductive type silicon carbide epitaxial layer on the first conductive type silicon carbide substrate, and implanting and pushing impurity ions of a second conductive type in the process of growing the first conductive type silicon carbide epitaxial layer so as to obtain a second conductive type shielding base layer in the first conductive type silicon carbide epitaxial layer;
step b, performing first conductivity type impurity ion implantation above the first conductivity type silicon carbide epitaxial layer to obtain a first conductivity type current expansion base layer penetrating through the first conductivity type silicon carbide epitaxial layer in the first conductivity type silicon carbide epitaxial layer;
C, carrying out second conductivity type impurity ion implantation above the first conductivity type silicon carbide epitaxial layer so as to obtain a second conductivity type silicon carbide base layer, wherein the second conductivity type silicon carbide base layer is adjacent to the first conductivity type current expansion base layer;
Step d, carrying out second conductivity type impurity ion implantation to obtain a second conductivity type silicon carbide contact region in the second conductivity type silicon carbide region layer;
Step e, implanting impurity ions of the first conductivity type to obtain a first conductivity type silicon carbide source region in the second conductivity type silicon carbide region layer, wherein the first conductivity type silicon carbide source region is adjacent to an adjacent second conductivity type silicon carbide contact region;
Step f, after the groove is etched by utilizing a groove etching process, a cell groove is obtained, wherein the cell groove comprises a cell first groove and a cell second groove, the cell first groove and the cell second groove penetrate through a second conductive type silicon carbide base layer and a first conductive type current expansion base layer so as to respectively form a second conductive type silicon carbide base region and a first conductive type current expansion layer through the second conductive type silicon carbide base layer and the first conductive type current expansion base layer, the groove bottoms of the cell first groove and the cell second groove are positioned below the first conductive type current expansion layer, and a mesa structure can be formed by utilizing the second conductive type silicon carbide base region, the first conductive type current expansion layer and a second conductive type silicon carbide contact region positioned on the second conductive type silicon carbide base region and adjacent to the first conductive type silicon carbide source region;
Meanwhile, the second conductive type shielding base layer can be used for forming a second conductive type shielding layer and second conductive type inter-groove shielding connecting columns, the second conductive type shielding layer can cover the bottoms of the first grooves of the cells and the corresponding grooves of the second grooves of the cells, the second conductive type inter-groove shielding connecting columns can extend into the first grooves of the cells and the second grooves of the cells, and the second conductive type inter-groove shielding connecting columns are in contact with the corresponding side walls of the first grooves of the cells and the corresponding side walls of the second grooves of the cells.
10. The method of manufacturing a trench silicon carbide field effect transistor according to claim 7, wherein the gate first insulating spacer and the gate second insulating spacer are both silicon dioxide.
11. The method of any of claims 7 to 10, wherein the doping concentration of the second conductivity type doped channel region is lower than the doping concentration of the second conductivity type source region.
12. The method of manufacturing a trench silicon carbide field effect transistor according to any of claims 7 to 10, wherein the gate first insulating oxide and the gate second insulating oxide are grown in the first trench and the second trench, respectively, by thermal oxidation; the thickness of the first grid insulation isolator and the second grid insulation isolator contacted with the source electrode connecting column between the grooves is larger than that of the first grid insulation oxide layer and the second grid insulation oxide layer.
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| CN102280487A (en) * | 2011-08-22 | 2011-12-14 | 无锡新洁能功率半导体有限公司 | Power MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) device of novel groove structure and manufacture method thereof |
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