CN112635548A - Terminal structure of trench MOSFET device and manufacturing method - Google Patents
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Abstract
The invention relates to a terminal structure of a trench MOSFET device, which comprises a terminal protection area, wherein the terminal protection area comprises a first conductive type substrate and a first conductive type drift area positioned on the first conductive type substrate; according to the invention, the terminal structure is improved, and the graded junction second conduction type well region is adopted for voltage division, so that the voltage resistance of the device can be improved, the width of the terminal can be reduced, the area of an active region is increased, the on-resistance of the device is further reduced, and the reliability of the whole device is improved.
Description
Technical Field
The invention relates to a terminal structure of a semiconductor device and a manufacturing method thereof, in particular to a terminal structure of a trench MOSFET device and a manufacturing method thereof, belonging to the technical field of manufacturing of semiconductor devices.
Background
In the Field of power Semiconductor devices, a Trench structure is generally used as a terminal protection region in an existing Trench Metal-Oxide-Semiconductor Field Effect Transistor (Trench MOSFET), as shown in fig. 1, and the terminal protection region of the conventional structure is provided with at least one gate Trench 20 on a first conductive type drift region 2, and utilizes the voltage division Effect of a plurality of gate trenches 20 to improve the local electric Field concentration Effect at the periphery of a chip, so as to improve the breakdown voltage and reliability of the chip, although the Trench structure can effectively improve the terminal withstand voltage, for a Trench MOSFET device with a medium voltage of 120V to 150V, the number of trenches needs to be increased to further improve the withstand voltage, so that the width of the terminal is larger, the area of an active region is reduced, which is not beneficial to reducing the on-resistance, if the number of trenches is not increased, when the breakdown voltage reaches above 120V, the obvious phenomenon of weak terminal voltage resistance is shown in particular to the problems of low terminal breakdown voltage, poor avalanche capability, reduced reliability and the like, which are all related to the weak voltage resistance of the terminal structure, namely the weak terminal phenomenon.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a terminal structure of a trench MOSFET device and a manufacturing method thereof.
In order to achieve the technical purpose, the technical scheme of the invention is as follows: a terminal structure of a trench MOSFET device comprises a terminal protection area, wherein the terminal protection area surrounds a cell area, the terminal protection area comprises a semiconductor substrate, the semiconductor substrate comprises a first conductive type substrate and a first conductive type drift area located on the first conductive type substrate, the terminal structure is characterized in that the terminal protection area is internally provided with a transition area groove adjacent to the cell area and a stop groove located at the edge of the terminal protection area, a graded junction second conductive type well area is arranged between the transition area groove and the stop groove, an insulating medium covers the graded junction second conductive type well area, a source electrode metal covers the insulating medium, and the source electrode metal penetrates through the insulating medium to be in ohmic contact with the graded junction second conductive type well area.
Furthermore, in the terminal protection region, in a direction from the transition region trench to the stop trench, the depth of the graded junction second conductivity type well region is gradually reduced to form a gradual gradient.
Furthermore, a gate oxide layer and gate conductive polysilicon surrounded by the gate oxide layer are arranged in the transition region groove.
Furthermore, a cut-off oxide layer and a cut-off polysilicon layer surrounded by the cut-off oxide layer are arranged in the cut-off groove, a cut-off ring metal is arranged on the cut-off groove, and the cut-off ring metal penetrates through the insulating medium to be in contact with the first conduction type drift region.
Furthermore, in the cell region, a second conductive type body region, a first conductive type source region located in the second conductive type body region, and a gate trench located between the second conductive type body regions are arranged in the first conductive type drift region, a gate oxide layer and gate conductive polysilicon surrounded by the gate oxide layer are arranged in the gate trench, an insulating medium covers the conductive polysilicon, a source metal covers the insulating medium, and the source metal penetrates through the insulating medium and is in ohmic contact with the second conductive type body region and the first conductive type source region respectively.
In order to achieve the technical purpose, the invention further provides a manufacturing method of the terminal structure of the trench MOSFET device, which is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region and a first conduction type substrate positioned below the first conduction type drift region, the upper surface of the first conduction type drift region is a first main surface of the semiconductor substrate, and the lower surface of the first conduction type substrate is a second main surface of the semiconductor substrate;
depositing an oxide layer on the first main surface, and etching the oxide layer to form a patterned masking window I;
etching the first conduction type drift region under the shielding of the patterned masking window to obtain a transition region groove and a stop groove, and removing the patterned masking window;
thermally growing an oxide layer on the first main surface, the transition region groove and the stop groove, and continuously depositing polycrystalline silicon on the oxide layer;
etching the polycrystalline silicon and the oxide layer in sequence, removing the oxide layer and the polycrystalline silicon on the first main surface to obtain a gate oxide layer and a grid conductive polycrystalline silicon which are positioned in the transition region groove, and simultaneously obtaining a stop oxide layer and a stop polycrystalline silicon which are positioned in the stop groove;
depositing an oxide layer on the first main surface, and etching the oxide layer to obtain a second graphical masking window;
injecting second conductive type ions into the first main surface under the shielding of the second graphical masking window, pushing a trap, activating and diffusing the second conductive type ions into a whole, forming a graded junction second conductive type well region positioned in the terminal protection region and a second conductive type body region positioned in the cellular region in the first conductive type drift region, and then removing the second graphical masking window;
depositing an oxide layer on the first main surface, and etching the oxide layer to obtain a third graphical masking window;
injecting first conductive type ions into the first main surface under the shielding of the third graphical masking window, and annealing to obtain a first conductive type source region positioned in the second conductive type body region;
step ten, depositing an insulating medium on the first main surface and etching the insulating medium to obtain a metal contact hole;
step eleven, depositing metal on the insulating medium and in the metal contact hole, and etching the metal to obtain source metal and stop ring metal
And step twelve, depositing metal on the second main surface to form drain metal.
Further, in the sixth step, in a direction from the transition region trench to the stop trench, the width of the second patterned masking window gradually decreases, and the sum of the width of each masking window and the distance between adjacent masking windows is the same.
Further, in the seventh step, in a direction from the transition region trench to the stop trench, the depth of the graded junction second conductivity type well region is gradually reduced to form a gradual gradient.
Further, for an N-type trench MOSFET device, the first conductivity type is N-type and the second conductivity type is P-type; for a P-type trench MOSFET device, the first conductivity type is P-type and the second conductivity type is P-type.
Compared with the traditional trench gate power semiconductor device terminal, the invention has the following advantages:
1) the invention applies the withstand voltage principle of the graded junction, designs a second graphical masking window with gradually reduced width as an injection mask, injects ions and pushes a trap, so that all injection areas are mutually connected into a piece to form a second conductive type well region of the graded junction with gradually reduced depth and certain gradient change; when the device is reversely biased, the depth of the second conduction type well region of the graded junction is changed in a certain gradient manner, so that the second conduction type well region of the graded junction in the terminal region is almost completely exhausted, the voltage resistance of the terminal of the device is greatly improved, the avalanche capability of the device is enhanced, and the reliability of the device is improved;
2) compared with the existing trench gate MOSFET, the invention improves the withstand voltage of the terminal on the premise of not increasing the width of the terminal, thereby increasing the effective area of a cellular region, further reducing the on-resistance of the device and reducing the on-loss of the device;
3) the method does not increase any process difficulty and is compatible with the existing semiconductor process.
Drawings
Fig. 1 is a schematic cross-sectional view of a terminal protection region of a conventional trench gate MOSFET.
Fig. 2 is a schematic cross-sectional view of a terminal protection region of a trench gate MOSFET according to embodiment 1 of the present invention.
Fig. 3 is a schematic cross-sectional structural diagram of forming a drift region of a first conductivity type in embodiment 1 of the present invention.
Fig. 4 is a schematic cross-sectional structural diagram of forming a first patterned masking window in embodiment 1 of the present invention.
Fig. 5 is a schematic cross-sectional structural view of forming a transition region trench and a stop trench in embodiment 1 of the present invention.
Fig. 6 is a schematic cross-sectional structural view after forming an oxide layer and depositing polysilicon in embodiment 1 of the present invention.
Fig. 7 is a schematic cross-sectional structural view of forming a gate oxide layer, a gate conductive polysilicon, a stop oxide layer and a stop polysilicon in embodiment 1 of the present invention.
Fig. 8 is a schematic cross-sectional structural view of forming a second patterned masking window in embodiment 1 of the present invention.
Fig. 9 is a schematic cross-sectional structure diagram after P-type ions are implanted in embodiment 1 of the present invention.
Fig. 10 is a schematic cross-sectional view of forming a P-type body region and a graded junction P-type well region in embodiment 1 of the invention.
Fig. 11 is a schematic cross-sectional structural diagram of forming a patterned masking window three and an N-type source region in embodiment 1 of the present invention.
FIG. 12 is a schematic cross-sectional view of the formation of insulating dielectric and metal contact holes in accordance with example 1 of the present invention.
Fig. 13 is a schematic cross-sectional structure diagram of forming a source metal and a stop ring metal in embodiment 1 of the present invention. Description of reference numerals: 1-N type substrate; 2-an N-type drift region; 3-transition region trench; 4-closing the trench; 5, a P-type well region of a graded junction; 6-insulating medium; 7-source metal; 8-gate oxide layer; 9-grid conductive polysilicon; 10-cut off oxide layer; 11-cutting off the polysilicon; 12-stop ring metal; 13-P-type body region; 14-N-type source region; 15-a patterned masking window one; 16-a second graphical masking window; 17-graphical masking window three; 18-metal contact holes; 19-drain metal; 20-a gate trench; 001 — first major face; 002 — second major surface.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
The present invention is not limited to the following embodiments, and the drawings referred to in the following description are provided to make the content of the present invention understandable, that is, the present invention is not limited to the device structures exemplified in the drawings, and is applicable to all trench gate type MOS.
Example 1:
taking an N-type trench gate MOSFET semiconductor device as an example, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity;
a terminal structure of a trench MOSFET device comprises a terminal protection area, wherein the terminal protection area surrounds a cellular area;
as shown in fig. 2, in the terminal protection region, the terminal protection region includes a semiconductor substrate, the semiconductor substrate includes an N-type substrate 1 and an N-type drift region 2 located on the N-type substrate 1, and is characterized in that, in the terminal protection region, a transition region trench 3 adjacent to the cell region and a stop trench 4 located at the edge of the terminal protection region are arranged in the N-type drift region 2, a graded junction P-type well region 5 is arranged between the transition region trench 3 and the stop trench 4, an insulating medium 6 covers the graded junction P-type well region 5, a source metal 7 covers the insulating medium 6, and the source metal 7 passes through the insulating medium 6 to make ohmic contact with the graded junction P-type well region 5; in the direction from the transition region trench 3 to the stop trench 4, the depth of the graded junction P-type well region 5 is gradually reduced to form a gradual gradient.
A gate oxide layer 8 and gate conductive polycrystalline silicon 9 surrounded by the gate oxide layer 8 are arranged in the transition region groove 3; a cut-off oxide layer 10 and a cut-off polysilicon 11 surrounded by the cut-off oxide layer 10 are arranged in the cut-off trench 4, a cut-off ring metal 12 is arranged on the cut-off trench 4, and the cut-off ring metal 12 penetrates through the insulating medium 6 to be in contact with the N-type drift region 2.
In the cell region, a P-type body region 13, an N-type source region 14 located in the P-type body region 13, and a gate trench located between the P-type body regions 13 are arranged in the N-type drift region 2, a gate oxide layer 8 and a gate conductive polysilicon 9 surrounded by the gate oxide layer 8 are arranged in the gate trench, the gate conductive polysilicon 9 is covered with an insulating medium 6, the insulating medium 6 is covered with a source metal 7 and a gate metal, the source metal 7 penetrates through the insulating medium 6 to be in ohmic contact with the P-type body region 13 and the N-type source region 14 respectively, the gate metal is isolated from the source metal 7, and the gate metal is in ohmic contact with the gate conductive polysilicon 9, as is well known to those skilled in the art, and is not described herein again;
the method for manufacturing the terminal structure of the trench MOSFET device in the embodiment 1 of the invention is characterized by comprising the following steps:
as shown in fig. 3, a semiconductor substrate is provided, the semiconductor substrate includes an N-type drift region 2 and an N-type substrate 1 located below the N-type drift region 2, an upper surface of the N-type drift region 2 is a first main surface 001 of the semiconductor substrate, and a lower surface of the N-type substrate 1 is a second main surface 002 of the semiconductor substrate;
depositing an oxide layer on the first main surface 001, and etching the oxide layer to form a first patterned masking window 15;
etching the N-type drift region 2 under the shielding of the patterned masking window 15 to obtain a transition region groove 3 and a stop groove 4, and removing the patterned masking window 15;
as shown in fig. 6, a fourth step is to thermally grow an oxide layer on the first main surface 001, the transition region trench 3 and the stop trench 4, and continuously deposit polysilicon on the oxide layer;
as shown in fig. 7, step five, the polysilicon and the oxide layer are sequentially etched, and the oxide layer and the polysilicon on the first main surface 001 are removed, so as to obtain a gate oxide layer 8 and a gate conductive polysilicon 9 in the transition region trench 3, and simultaneously obtain a stop oxide layer 10 and a stop polysilicon 11 in the stop trench 4;
depositing an oxide layer on the first main surface 001, and etching the oxide layer to obtain a second patterned masking window 16;
in the direction from the transition region groove 3 to the stop groove 4, the width of the second patterned masking window 16 is gradually reduced, and the sum of the width of each masking window and the distance between the adjacent masking windows is the same;
implanting P-type ions into the first main surface 001 under the shielding of the second patterned masking window 16, pushing a well, activating and diffusing the P-type ions to form a piece, forming a graded junction P-type well region 5 located in the terminal protection region and a P-type body region 13 located in the cellular region in the N-type drift region 2, and then removing the second patterned masking window 16;
in the direction from the transition region groove 3 to the stop groove 4, the depth of the graded junction P-type well region 5 is gradually reduced to form a gradual gradient, and a second graphical masking window 16 is removed;
depositing an oxide layer on the first main surface 001, and etching the oxide layer to obtain a third patterned masking window 17;
step nine, under the shielding of the third patterned masking window 17, injecting N-type ions into the first main surface 001, and annealing to obtain an N-type source region 14 located in the P-type body region 13;
as shown in fig. 12, a tenth step is to deposit an insulating medium 6 on the first main surface 001 and etch the insulating medium 6 to obtain a metal contact hole 18;
and step eleven, as shown in FIG. 13, depositing metal on the insulating medium 6 and in the metal contact hole 18, and etching the metal to obtain the source metal 7 and the stop ring metal 12
Step twelve, as shown in fig. 2, a metal is deposited on the second major surface 002 to form the drain metal 19, completing the fabrication of the termination structure.
According to the invention, a second graphical masking window with gradually reduced width is designed to be used as an injection mask, injection is carried out and a trap is pushed, so that all injection regions are connected into a whole to form a slowly-varying junction P-type well region 5 with certain gradient change in depth; when the device is reversely biased, the depth of the graded junction P-type well region 5 is changed in a certain gradient manner, so that the graded junction P-type well region 5 of the terminal region is almost completely exhausted, the voltage resistance of the terminal of the device is greatly improved, the avalanche capability of the device is enhanced, and the reliability of the device is improved;
compared with the existing trench gate MOSFET, the invention improves the voltage resistance of the terminal on the premise of not increasing the width of the terminal, thereby increasing the effective area of a cellular region, further reducing the on-resistance of the device and reducing the on-loss of the device; the method does not increase any process difficulty and process cost, and is compatible with the existing semiconductor process.
The present invention and its embodiments have been described above, and the description is not intended to be limiting, and the embodiments shown in the drawings are only one embodiment of the present invention, and the actual structure is not limited thereto. In summary, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A terminal structure of a trench MOSFET device comprises a terminal protection area, wherein the terminal protection area surrounds a cell area, the terminal protection area comprises a semiconductor substrate, the semiconductor substrate comprises a first conductive type substrate (1) and a first conductive type drift area (2) located on the first conductive type substrate (1), the terminal structure is characterized in that the terminal protection area is provided with a transition area groove (3) adjacent to the cell area and a cut-off groove (4) located at the edge of the terminal protection area in the first conductive type drift area (2), a graded junction second conductive type well area (5) is arranged between the transition area groove (3) and the cut-off groove (4), an insulating medium (6) covers the graded junction second conductive type well area (5), a source metal (7) covers the insulating medium (6) and the graded junction second conductive type well area (5), and the source metal (7) penetrates through the insulating medium (6) and the graded junction second conductive type well area (5) And (5) ohmic contact.
2. A termination structure for a trench MOSFET device according to claim 1, wherein: in the terminal protection area, the depth of the second conductive type well region (5) of the gradual change junction is gradually reduced from the transition area groove (3) to the stop groove (4) to form a gradual change gradient.
3. A termination structure for a trench MOSFET device according to claim 1, wherein: and a gate oxide layer (8) and grid conductive polycrystalline silicon (9) surrounded by the gate oxide layer (8) are arranged in the transition region groove (3).
4. A termination structure for a trench MOSFET device according to claim 1, wherein: a cut-off oxide layer (10) and a cut-off polysilicon (11) surrounded by the cut-off oxide layer (10) are arranged in the cut-off groove (4), a cut-off ring metal (12) is arranged on the cut-off groove (4), and the cut-off ring metal (12) penetrates through an insulating medium (6) to be in contact with the first conduction type drift region (2).
5. A termination structure for a trench MOSFET device according to claim 1, wherein: in the cellular region, a second conductive type body region (13), a first conductive type source region (14) located in the second conductive type body region (13) and a grid groove located between the second conductive type body regions (13) are arranged in the first conductive type drift region (2), a grid oxide layer (8) and grid conductive polycrystalline silicon (9) surrounded by the grid oxide layer (8) are arranged in the grid groove, an insulating medium (6) covers the conductive polycrystalline silicon (8), a source metal (7) covers the insulating medium (6), and the source metal (7) penetrates through the insulating medium (6) and is in ohmic contact with the second conductive type body region (13) and the first conductive type source region (14).
6. A method for manufacturing a terminal structure of a trench MOSFET device is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region (2) and a first conduction type substrate (1) positioned below the first conduction type drift region (2), the upper surface of the first conduction type drift region (2) is a first main surface (001) of the semiconductor substrate, and the lower surface of the first conduction type substrate (1) is a second main surface (002) of the semiconductor substrate;
depositing an oxide layer on the first main surface (001), and etching the oxide layer to form a first graphical masking window (15);
etching the first conduction type drift region (2) under the shielding of the patterned masking window (15) to obtain a transition region groove (3) and a cut-off groove (4), and removing the patterned masking window (15);
thermally growing an oxide layer on the first main surface (001), the transition region groove (3) and the stop groove (4), and continuously depositing polycrystalline silicon on the oxide layer;
etching the polycrystalline silicon and the oxide layer in sequence, removing the oxide layer and the polycrystalline silicon on the first main surface (001), obtaining a gate oxide layer (8) and gate conductive polycrystalline silicon (9) which are positioned in the transition region groove (3), and simultaneously obtaining a stop oxide layer (10) and stop polycrystalline silicon (11) which are positioned in the stop groove (4);
depositing an oxide layer on the first main surface (001), and etching the oxide layer to obtain a second graphical masking window (16);
injecting second conductive type ions into the first main surface (001) under the shielding of the second patterned masking window (16), pushing a trap, activating and diffusing the second conductive type ions into a whole, forming a graded junction second conductive type well region (5) positioned in the terminal protection region and a second conductive type body region (13) positioned in the cellular region in the first conductive type drift region (2), and then removing the second patterned masking window (16);
depositing an oxide layer on the first main surface (001), and etching the oxide layer to obtain a third graphical masking window (17);
step nine, under the shielding of the third patterned masking window (17), first conductive type ions are injected into the first main surface (001), and annealing is carried out, so that a first conductive type source region (14) located in the second conductive type body region (13) is obtained;
step ten, depositing an insulating medium (6) on the first main surface (001) and etching the insulating medium (6) to obtain a metal contact hole (18);
step eleven, depositing metal on the insulating medium (6) and in the metal contact hole (18), and etching the metal to obtain source metal (7) and stop ring metal (12)
And a step twelve, depositing metal on the second main surface (002) to form drain metal (19).
7. The method of claim 6, wherein: in the sixth step, in the direction from the transition region groove (3) to the stop groove (4), the width of the second patterned masking window (16) is gradually reduced, and the sum of the width of each masking window and the distance between adjacent masking windows is the same.
8. The method of claim 6, wherein: in the seventh step, in a direction from the transition region trench (3) to the stop trench (4), the depth of the graded junction second conductivity type well region (5) is gradually reduced to form a gradient.
9. The termination structure and fabrication method of a trench MOSFET device as claimed in claim 1 or 6, wherein: for an N-type trench MOSFET device, the first conductivity type is N-type, and the second conductivity type is P-type; for a P-type trench MOSFET device, the first conductivity type is P-type and the second conductivity type is P-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011598537.4A CN112635548A (en) | 2020-12-29 | 2020-12-29 | Terminal structure of trench MOSFET device and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011598537.4A CN112635548A (en) | 2020-12-29 | 2020-12-29 | Terminal structure of trench MOSFET device and manufacturing method |
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| CN112635548A true CN112635548A (en) | 2021-04-09 |
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| CN113948577A (en) * | 2021-10-15 | 2022-01-18 | 捷捷微电(无锡)科技有限公司 | High-reliability MOSFET integrated circuit chip and preparation method thereof |
| CN117637831A (en) * | 2023-11-20 | 2024-03-01 | 海信家电集团股份有限公司 | Semiconductor device and method for manufacturing semiconductor device |
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| CN103887331A (en) * | 2012-12-21 | 2014-06-25 | 微机电科技香港有限公司 | High-voltage IGBT (Insulated Gate Bipolar Transistor) device VLD terminal and manufacturing method thereof |
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| CN103887331A (en) * | 2012-12-21 | 2014-06-25 | 微机电科技香港有限公司 | High-voltage IGBT (Insulated Gate Bipolar Transistor) device VLD terminal and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113948577A (en) * | 2021-10-15 | 2022-01-18 | 捷捷微电(无锡)科技有限公司 | High-reliability MOSFET integrated circuit chip and preparation method thereof |
| CN117637831A (en) * | 2023-11-20 | 2024-03-01 | 海信家电集团股份有限公司 | Semiconductor device and method for manufacturing semiconductor device |
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