CN210156383U - Super junction power semiconductor device - Google Patents
Super junction power semiconductor device Download PDFInfo
- Publication number
- CN210156383U CN210156383U CN201921422126.2U CN201921422126U CN210156383U CN 210156383 U CN210156383 U CN 210156383U CN 201921422126 U CN201921422126 U CN 201921422126U CN 210156383 U CN210156383 U CN 210156383U
- Authority
- CN
- China
- Prior art keywords
- type
- semiconductor device
- conductivity type
- power semiconductor
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 210000000746 body region Anatomy 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims description 25
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 16
- 239000000463 material Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 11
- 239000012535 impurity Substances 0.000 description 9
- 230000005670 electromagnetic radiation Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000010355 oscillation Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The utility model relates to the field of semiconductor technology, specifically disclose a surpass knot power semiconductor device, include: the semiconductor device comprises a first conductive type substrate and a first conductive type drift region positioned on the first conductive type substrate, wherein a first conductive type column, a second conductive type first column and second conductive type second columns are arranged in the first conductive type drift region, and two sides of each second conductive type second column are adjacent to the second conductive type first column; a second conductive type body region is arranged on the second conductive type first column; a first gate electrode is arranged above the second conductive type body region, a second gate electrode is arranged above the second conductive type second column, and the first gate electrode and the second gate electrode are separated by a second insulating medium layer and are electrically connected. The utility model provides a super junction power semiconductor device can improve super junction semiconductor device's switching characteristic.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a super junction power semiconductor device.
Background
In the field of medium-high voltage power semiconductor devices, a Super Junction structure (Super Junction) is widely adopted, and compared with a traditional power MOSFET device, the Super Junction structure MOSFET device can obtain a more excellent compromise relationship between the withstand voltage and the on-resistance of the device. The super-junction structure is formed in a drift region of the semiconductor device, the super-junction structure formed in the drift region comprises an N-type conductive column (N column) and a P-type conductive column (P column), and a plurality of P-N column pairs formed by alternately adjacently arranging the N column and the P column form the super-junction structure. The N column has N conductive type impurities, the P column has P conductive type impurities, and the impurity amount of the N column is consistent with that of the P column. When the MOSFET device with the super-junction structure is cut off, the N columns and the P columns in the super-junction structure are respectively depleted, depletion layers extend from a P-N junction interface between each N column and each P column, and the depletion layers extend and completely deplete the N columns and the P columns due to the fact that the impurity amount in the N columns and the impurity amount in the P columns are equal, and therefore the device is supported to be resistant to voltage; when the device is turned on, the resistivity of the drift region of the super junction device is lower, so that the on-resistance of the super junction device can be greatly reduced compared with that of a common device, and the on-resistance of the super junction MOSFET device can be reduced by about 70% compared with that of a common VDMOS device.
In the switching process of the device, the P column and the N column in the super-junction structure can be respectively depleted only by needing lower drain withstand voltage (Vds), so that the Miller capacitance (Cgd) of the super-junction MOSFET is sharply reduced under the drain-source voltage of tens of volts, a small value is maintained, and the Miller capacitance has obvious nonlinear characteristics as a whole. The nonlinear characteristic of the miller capacitance of the super-junction MOSFET is easy to cause grid voltage oscillation in the switching process of the device, the oscillation can influence the stability and the EMI characteristic of a system, and the wide-range use of the super-junction MOSFET and other devices is limited.
In the practical application of the super-junction MOSFET, in order to improve the switching characteristics of the super-junction MOSFET, the switching speed of the super-junction device is generally reduced by increasing discrete resistors, capacitors and the like around the super-junction MOSFET, but these methods increase the switching loss of the device on one hand, and increase of peripheral devices on the other hand may cause an increase in system cost and also reduce system reliability.
Therefore, how to improve the switching characteristics of the superjunction semiconductor device becomes a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The utility model provides a super junction power semiconductor device solves the problem of the switching characteristic who surpasses junction semiconductor device who exists among the correlation technique.
As a first aspect of the present invention, there is provided a super junction power semiconductor device, including: a semiconductor base plate comprising a first conductivity type substrate and a first conductivity type drift region located on the first conductivity type substrate, a surface of the first conductivity type drift region facing away from the first conductivity type substrate being a first main surface of the semiconductor base plate, a surface of the first conductivity type substrate facing away from the first conductivity type drift region being a second main surface of the semiconductor base plate, wherein,
a super junction structure is arranged in the first conduction type drift region and comprises a first conduction type column, a second conduction type first column and a second conduction type second column, the first conduction type column, the second conduction type first column and the second conduction type second column extend along the direction from the first main face to the second main face, two sides of each second conduction type second column are adjacent to the second conduction type first column and are spaced by the first conduction type columns, and the second conduction type first columns are electrically connected with the second conduction type second columns;
a second conductive type body region is arranged on the second conductive type first column and is positioned in the first conductive type drift region;
a first gate electrode is arranged above the second conductive type body region and is surrounded by a gate dielectric layer and a second insulating dielectric layer, a second gate electrode is arranged above the second conductive type column, the second gate electrode is surrounded by a first insulating dielectric layer and a second insulating dielectric layer, the first gate electrode and the second gate electrode are separated by the second insulating dielectric layer and are electrically connected, and the thickness of the first insulating dielectric layer is not less than that of the gate dielectric layer.
Further, the first insulating medium layer is arranged above the second conductive type second column and is in contact with the second conductive type second column.
Further, a first conductive type source region is arranged in the second conductive type body region, source metal is arranged on the second insulating medium layer, and ohmic contact is formed between the second conductive type body region and the source metal and between the first conductive type source region and the source metal.
Further, a drain metal is provided on the second main surface, and ohmic contact is made between the first conductivity-type substrate and the drain metal.
Further, a surface of the first conductivity type drift region facing away from the first main face is in contact with a surface of the first conductivity type substrate facing away from the second main face.
Further, the first gate electrode includes a planar gate electrode or a trench gate electrode.
Further, the number of the second conductive-type first pillars is not less than the number of the second conductive-type second pillars.
Further, the super-junction power semiconductor device comprises an N-type super-junction power semiconductor device and a P-type super-junction power semiconductor device, when the super-junction power semiconductor device is the N-type super-junction power semiconductor device, the first conduction type is N-type, the second conduction type is P-type, and when the super-junction power semiconductor device is the P-type super-junction power semiconductor device, the first conduction type is P-type, and the second conduction type is N-type.
By the super junction power semiconductor device, due to the interval design of the first gate electrode and the second gate electrode and the introduction of the first insulating medium layer, the gate-to-drain capacitance at low drain voltage is effectively reduced; when the drain voltage is high, the second conductive type second columns are fully exhausted, no second conductive type impurities remain at corresponding positions, the capacitance of the corresponding region of the second gate electrode and the drain is converted into gate leakage capacitance, and the gate leakage capacitance is increased under the high drain voltage, so that the gate leakage capacitance from the low drain voltage to the high drain voltage in the switching process of the device is effectively reduced, namely the variation range of the miller capacitance, the gate oscillation can be effectively reduced, and the electromagnetic radiation of the device during working is reduced. In addition, when the drain voltage is low, the capacitance between the second conductive type second column and the second gate electrode is the gate-source capacitance, so that the input capacitance of the device can be properly increased, the switching speed can be adjusted, and the electromagnetic radiation of the device during operation can be reduced. Therefore, the utility model provides a super junction power semiconductor device has reached and has improved the purpose of super junction power semiconductor device's switching characteristic under the prerequisite that does not increase cost and not increase the loss.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional structure diagram of a super junction power semiconductor device provided by an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional structural diagram of forming a hard mask opening according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional structural diagram of forming the first deep trench and the second deep trench according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional structural diagram of forming a first column of a second conductivity type and a second column of the second conductivity type according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional structural diagram of forming a second conductive type body region according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional structural diagram of forming a first insulating medium layer according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional structural diagram of forming a gate dielectric layer and a gate material layer according to an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional structural diagram of forming the first gate electrode and the second gate electrode according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional structural diagram of forming a first conductive type source region according to an embodiment of the present invention.
Fig. 10 is a schematic cross-sectional structural diagram of forming a second insulating dielectric layer and a source metal according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances for purposes of describing the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In this embodiment, a super junction power semiconductor device is provided, fig. 1 is a schematic cross-sectional structure diagram of a super junction power semiconductor device provided according to an embodiment of the present invention, as shown in fig. 1, including: a semiconductor base plate comprising a first conductivity type substrate 02 and a first conductivity type drift region 01 located on the first conductivity type substrate 02, a surface of the first conductivity type drift region 01 facing away from the first conductivity type substrate 02 being a first main surface 001 of the semiconductor base plate, a surface of the first conductivity type substrate 02 facing away from the first conductivity type drift region 01 being a second main surface 002 of the semiconductor base plate, wherein,
a super junction structure is arranged in the first conductivity type drift region 01, and the super junction structure includes a first conductivity type column 12, a second conductivity type first column 11a, and a second conductivity type second column 11b, the first conductivity type column 12, the second conductivity type first column 11a, and the second conductivity type second column 11b all extend along a direction in which the first main surface 001 points to the second main surface 002, two sides of each second conductivity type second column 11b are adjacent to the second conductivity type first column 11a and are spaced by the first conductivity type column 12, and the second conductivity type first column 11a and the second conductivity type second column 11b are electrically connected;
a second conductive type body region 13 is arranged on the second conductive type first pillar 11a, and the second conductive type body region 13 is located in the first conductive type drift region 01;
a first gate electrode 16a is arranged above the second conductive type body region 13, the first gate electrode 16a is surrounded by a gate dielectric layer 15 and a second insulating dielectric layer 18, a second gate electrode 16b is arranged above the second pillar 11b of the second conductive type, the second gate electrode 16b is surrounded by a first insulating dielectric layer 14 and a second insulating dielectric layer 18, the first gate electrode 16a and the second gate electrode 16b are separated by the second insulating dielectric layer 18 and are electrically connected, and the thickness of the first insulating dielectric layer 14 is not less than that of the gate dielectric layer 15
By the super junction power semiconductor device, due to the interval design of the first gate electrode and the second gate electrode and the introduction of the first insulating medium layer, the gate-to-drain capacitance at low drain voltage is effectively reduced; when the drain voltage is high, the second conductive type second columns are fully exhausted, no second conductive type impurities remain at corresponding positions, the capacitance of the corresponding region of the second gate electrode and the drain is converted into gate leakage capacitance, and the gate leakage capacitance is increased under the high drain voltage, so that the gate leakage capacitance from the low drain voltage to the high drain voltage in the switching process of the device is effectively reduced, namely the variation range of the miller capacitance, the gate oscillation can be effectively reduced, and the electromagnetic radiation of the device during working is reduced. In addition, when the drain voltage is low, the capacitance between the second conductive type second column and the second gate electrode is the gate-source capacitance, so that the input capacitance of the device can be properly increased, the switching speed can be adjusted, and the electromagnetic radiation of the device during operation can be reduced. Therefore, the super junction power semiconductor device provided by the embodiment achieves the purpose of improving the switching characteristics of the super junction power semiconductor device on the premise of not increasing the cost and the loss.
Specifically, as shown in fig. 1, the first insulating medium layer 14 is disposed over the second conductive-type second pillars 11b and is in contact with the second conductive-type second pillars 11 b.
Specifically, a first conductive type source region 17 is disposed in the second conductive type body region 13, a source metal 19 is disposed on the second insulating dielectric layer 18, and ohmic contacts are formed between the second conductive type body region 13 and the first conductive type source region 17 and between the source metal 19.
Specifically, as shown in fig. 1, a drain metal 20 is provided on the second main surface 002, and ohmic contact is made between the first conductivity type substrate 02 and the drain metal 20.
Specifically, a surface of the first conductivity type drift region 01 facing away from the first main face 001 is in contact with a surface of the first conductivity type substrate 02 facing away from the second main face 002.
Preferably, the first gate electrode 16a includes a planar gate electrode or a trench gate electrode.
Specifically, the number of the second conductivity type first pillars 11a is not less than the number of the second conductivity type second pillars 11 b.
Preferably, the super junction power semiconductor device includes an N-type super junction power semiconductor device and a P-type super junction power semiconductor device, when the super junction power semiconductor device is the N-type super junction power semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type, when the super junction power semiconductor device is the P-type super junction power semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
It should be noted that the present embodiment includes the drawings, which are described by taking the power semiconductor device as an N-type super junction power semiconductor device as an example.
The super junction power semiconductor device and the operating principle provided in this embodiment will be described in detail with reference to fig. 1.
As shown in fig. 1, taking an N-type planar gate super junction power semiconductor device as an example, the super junction power semiconductor device includes a cell region and a terminal protection region, the cell region is located in a central region of the device, the terminal protection region surrounds the cell region, the cell region includes a semiconductor substrate, the semiconductor substrate includes an N + -type substrate 02 and an N-type drift region 01 located on and adjacent to the N + -type substrate 02, an upper surface of the N-type drift region 01 is a first main surface 001 of the semiconductor substrate, and a lower surface of the N + -type substrate 02 is a second main surface 002 of the semiconductor substrate;
on the cross section of the device, a super junction structure is arranged in the N-type drift region 01, the super junction structure is formed by alternately arranging N-type columns 12, P-type first columns 11a and P-type second columns 11b, the N-type columns 12, the P-type first columns 11a and the P-type second columns 11b extend along the direction from the first main surface 001 to the second main surface 002, two sides of any one P-type second column 11b are adjacent to the P-type first column 11a and are separated by the N-type columns 12, and the P-type first columns 11a are electrically communicated with the P-type second columns 11 b; a P-type body region 13 is arranged on the P-type first column 11a in the N-type drift region 01, the P-type body region 13 is arranged in the N-type drift region 01, and an N + type source region 17 is arranged in the P-type body region 13; a first gate electrode 16a surrounded by a gate dielectric layer 15 and a second insulating dielectric layer 18 is arranged above the P type body region 13, a second gate electrode 16b surrounded by a first insulating dielectric layer 14 and a second insulating dielectric layer 18 is arranged above the P type second column 11b, and the first gate electrode 16a and the second gate electrode 16b are separated by the second insulating dielectric layer 18 and are electrically communicated; the thickness of the first insulating dielectric layer 14 is not less than that of the gate dielectric layer 15.
Specifically, the P-type body region 13 and the N + -type source region 17 are in ohmic contact with the source metal 19, and the N + -type substrate 02 is in ohmic contact with the drain metal 20.
In the cross-sectional direction, the number of the P-type first columns 11a is equal to or greater than the number of the P-type second columns 11 b.
Preferably, the super junction power semiconductor device comprises a MOS device or an IGBT device
As another embodiment of the present invention, there is provided a method for manufacturing a super junction power semiconductor device, wherein as shown in fig. 2 to 10, taking the formation of an N-type super junction power semiconductor device as an example, the method for manufacturing a super junction power semiconductor device includes:
as shown in fig. 2, step one, referring to a first conductivity type substrate 02, growing a first conductivity type drift region 01 on the first conductivity type substrate 02, wherein a surface of the first conductivity type drift region 01 facing away from the first conductivity type substrate 02 is a first main surface 001, and a surface of the first conductivity type substrate 02 facing away from the first conductivity type drift region 01 is a second main surface 002;
specifically, a semiconductor substrate is provided, the semiconductor substrate comprises an N + -type substrate 02 and an N-type drift region 01 located on and adjacent to the N + -type substrate 02, the upper surface of the N-type drift region 01 is a first main surface 001 of the semiconductor substrate, and the lower surface of the N + -type substrate 02 is a second main surface 002 of the semiconductor substrate; a hard mask layer 21 is deposited on the first main surface 001 and the hard mask layer 21 is selectively etched to form a plurality of hard mask windows for trench etching.
Preferably, the material of the hard mask layer comprises LPTEOS or SiO2Or Si3N4。
It should be understood that the material of the hard mask layer is not limited to the above-mentioned materials, and may also include other realizable materials, which are not limited herein.
As shown in fig. 3, step two, depositing a mask layer on the first main surface 001, selectively etching the mask layer to form a plurality of mask windows for trench etching, forming a plurality of first trenches 21a and second trenches 21b in the first conductivity type drift region through the mask windows, where the first trenches 21a and the second trenches 21b extend from the first main surface 001 to the first conductivity type drift region 01, and the second trenches 21b are disposed adjacent to the two first trenches 21 a;
specifically, by masking with a hard mask layer, etching is performed on the surface of the first main surface by using an anisotropic etching method, and a plurality of first trenches 21a and second trenches 21b are formed in the N-type drift region 01, the first trenches 21a and the second trenches 21b extend from the first main surface 001 to the N-type drift region 01 to form first trenches 21a and second trenches 21b, and the second trenches 21b are adjacent to the two first trenches 21 a; the first trenches 21a and the second trenches 21b have the same depth, width and pitch.
As shown in fig. 4, step three, filling a second conductive type material in both the first trench 21a and the second trench 21b, forming a second conductive type first pillar 11a in the first conductive type drift region 01 in the first trench 21a, and forming a second conductive type second pillar 11b in the second trench 21 b;
specifically, a P-type semiconductor material is filled in the first trench 21a and the second trench 21b, and then the hard mask layer 21 is removed, so that a P-type first pillar 11a and a P-type second pillar 11b are formed in the N-type drift region 01.
As shown in fig. 5, a fourth step of selectively implanting second conductivity type ions into the first main surface 001 to form a second conductivity type body region 13 above the second conductivity type first pillars 11 a;
specifically, P-type ions are selectively implanted into the first main surface 001 of the semiconductor substrate by masking with a reticle, and then a well is driven, thereby forming a P-type body region 13 above the P-type first pillar 11a
As shown in fig. 6, step five, forming a first insulating dielectric layer 14 over the second conductive type second pillars 11 b;
specifically, a first insulating dielectric layer 14 is formed on the first main surface 001 of the semiconductor substrate by using a well-known semiconductor process such as thermal oxidation, deposition, etching and the like, and the material of the first insulating dielectric layer 14 comprises SiO2。
Step six, as shown in fig. 7, forming a gate dielectric layer 15 and a gate material layer 16 on the first main surface 001;
specifically, a gate dielectric layer 15 and a gate material layer 16 are formed on the first main surface 001 of the semiconductor substrate; typically, the gate dielectric layer 15 may be SiO2, and the gate material layer 16 may be doped polysilicon or the like.
As shown in fig. 8, in a seventh step, the gate dielectric layer 15 and the gate material layer 16 are etched to form a first gate electrode 16a and a second gate electrode 16 b;
specifically, the gate dielectric layer 15 and the gate material layer 16 on the first main surface are etched through the shielding of the reticle, so as to form a first gate electrode 16a and a second gate electrode 16 b.
As shown in fig. 9, step eight, implanting first conductivity type ions into the second conductivity type body region 13 to form a first conductivity type source region 17;
specifically, N-type ions are implanted into the P-type body region 13 through the mask of the reticle, thereby forming an N + -type source region 17.
As shown in fig. 10, a ninth step of depositing an insulating dielectric layer to form a second insulating dielectric layer 18, etching the second insulating dielectric layer 18, forming contact holes on the first conductive type source region 17 and the second conductive type body region 13, filling metal in the contact holes, and forming a source metal 19; depositing metal on the second main surface 002 to form a drain metal 20;
specifically, an insulating dielectric layer is deposited on the surface to form a second insulating dielectric layer 18, and the material of the second insulating dielectric layer 18 is SiO2 or BPSG; and etching the second insulating medium layer through the shielding of the photoetching plate, forming contact holes on the first conduction type source region and the second conduction type body region, filling metal in the contact holes to form source metal 19, and depositing metal on the second main surface of the semiconductor substrate to form drain metal 20.
According to the super junction power semiconductor device manufactured by the manufacturing method of the super junction power semiconductor device, due to the interval design of the first gate electrode and the second gate electrode and the introduction of the first insulating medium layer, the gate-drain capacitance at low drain voltage is effectively reduced; when the drain voltage is high, the second conductive type second columns are fully exhausted, no second conductive type impurities remain at corresponding positions, the capacitance of the corresponding region of the second gate electrode and the drain is converted into gate leakage capacitance, and the gate leakage capacitance is increased under the high drain voltage, so that the gate leakage capacitance from the low drain voltage to the high drain voltage in the switching process of the device is effectively reduced, namely the variation range of the miller capacitance, the gate oscillation can be effectively reduced, and the electromagnetic radiation of the device during working is reduced. In addition, when the drain voltage is low, the capacitance between the second conductive type second column and the second gate electrode is the gate-source capacitance, so that the input capacitance of the device can be properly increased, the switching speed can be adjusted, and the electromagnetic radiation of the device during operation can be reduced.
The first gate electrode in this embodiment is a planar gate structure, and it should be noted that this embodiment is also applicable to a trench gate device power MOSFET structure or an IGBT semiconductor device other than a MOSFET device.
The utility model provides a super junction power semiconductor device, because the separation design of first gate electrode 16a and second gate electrode 16b and the introduction of first insulating medium layer 14, the gate leakage electric capacity when effectively having reduced low drain voltage; when the drain voltage is high, the P-type second column 11b is fully exhausted, no P-type impurity is left at the corresponding position, the capacitance of the corresponding region of the second gate electrode 16b and the drain is converted into the gate leakage capacitance, so that the gate leakage capacitance is increased under the high drain voltage, the gate leakage capacitance from the low drain voltage to the high drain voltage in the switching process of the device is effectively reduced, namely the variation range of the miller capacitance, the gate oscillation can be effectively reduced, and the electromagnetic radiation of the device during working is reduced. In addition, at low drain voltage, the capacitance between the P-type second pillar 11b and the second gate electrode 16b is a gate-source capacitance, which can properly increase the input capacitance of the device, adjust the switching speed, and also help to reduce the electromagnetic radiation when the device operates. Through simulation analysis, in high-voltage device, because the utility model provides a channel density that surpasses knot power semiconductor device and cause reduces the influence to device on-resistance negligible basically.
It is to be understood that the above embodiments are merely exemplary embodiments that have been employed to illustrate the principles of the present invention, and that the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (8)
1. A super junction power semiconductor device comprising: a semiconductor substrate including a first conductivity type substrate and a first conductivity type drift region located on the first conductivity type substrate, a surface of the first conductivity type drift region facing away from the first conductivity type substrate being a first main surface of the semiconductor substrate, a surface of the first conductivity type substrate facing away from the first conductivity type drift region being a second main surface of the semiconductor substrate,
a super junction structure is arranged in the first conduction type drift region and comprises a first conduction type column, a second conduction type first column and a second conduction type second column, the first conduction type column, the second conduction type first column and the second conduction type second column extend along the direction from the first main face to the second main face, two sides of each second conduction type second column are adjacent to the second conduction type first column and are spaced by the first conduction type columns, and the second conduction type first columns are electrically connected with the second conduction type second columns;
a second conductive type body region is arranged on the second conductive type first column and is positioned in the first conductive type drift region;
a first gate electrode is arranged above the second conductive type body region and is surrounded by a gate dielectric layer and a second insulating dielectric layer, a second gate electrode is arranged above the second conductive type column, the second gate electrode is surrounded by a first insulating dielectric layer and a second insulating dielectric layer, the first gate electrode and the second gate electrode are separated by the second insulating dielectric layer and are electrically connected, and the thickness of the first insulating dielectric layer is not less than that of the gate dielectric layer.
2. The super junction power semiconductor device according to claim 1, wherein the first insulating dielectric layer is disposed over and in contact with the second conductivity type second pillar.
3. The super junction power semiconductor device according to claim 1, wherein a first conductivity type source region is provided in the second conductivity type body region, a source metal is provided on the second insulating dielectric layer, and ohmic contacts are provided between the second conductivity type body region and the source metal, and between the first conductivity type source region and the source metal.
4. The super junction power semiconductor device according to claim 1, wherein a drain metal is provided on the second main face, and an ohmic contact is made between the first conductivity type substrate and the drain metal.
5. The super junction power semiconductor device according to claim 1, wherein a surface of the first conductivity type drift region facing away from the first main face is in contact with a surface of the first conductivity type substrate facing away from the second main face.
6. The super junction power semiconductor device according to any one of claims 1 to 5, wherein the first gate electrode comprises a planar gate electrode or a trench gate electrode.
7. The super junction power semiconductor device according to any one of claims 1 to 5, wherein the number of the second conductivity type first pillars is not less than the number of the second conductivity type second pillars.
8. The super-junction power semiconductor device according to any one of claims 1 to 5, wherein the super-junction power semiconductor device comprises an N-type super-junction power semiconductor device and a P-type super-junction power semiconductor device, when the super-junction power semiconductor device is the N-type super-junction power semiconductor device, the first conductivity type is N-type, the second conductivity type is P-type, when the super-junction power semiconductor device is the P-type super-junction power semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921422126.2U CN210156383U (en) | 2019-08-29 | 2019-08-29 | Super junction power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921422126.2U CN210156383U (en) | 2019-08-29 | 2019-08-29 | Super junction power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210156383U true CN210156383U (en) | 2020-03-17 |
Family
ID=69767321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921422126.2U Withdrawn - After Issue CN210156383U (en) | 2019-08-29 | 2019-08-29 | Super junction power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210156383U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416309A (en) * | 2019-08-29 | 2019-11-05 | 无锡新洁能股份有限公司 | A kind of Superjunction power semiconductor device and preparation method thereof |
-
2019
- 2019-08-29 CN CN201921422126.2U patent/CN210156383U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416309A (en) * | 2019-08-29 | 2019-11-05 | 无锡新洁能股份有限公司 | A kind of Superjunction power semiconductor device and preparation method thereof |
| CN110416309B (en) * | 2019-08-29 | 2024-04-09 | 无锡新洁能股份有限公司 | Super junction power semiconductor device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9461127B2 (en) | Vertical power MOSFET having planar channel and its method of fabrication | |
| CN109065542B (en) | Shielded gate power MOSFET device and manufacturing method thereof | |
| US7504307B2 (en) | Semiconductor devices including voltage-sustaining space-charge zone and methods of manufacture thereof | |
| CN107342326B (en) | Power semiconductor device capable of reducing on-resistance and manufacturing method thereof | |
| US20110298042A1 (en) | Power semiconductor device with trench bottom polysilicon and fabrication method thereof | |
| CN103035721B (en) | Super junction device and manufacturing method thereof | |
| CN111816707B (en) | Equipotential drop field device for eliminating in-vivo curvature effect and manufacturing method thereof | |
| CN104332494A (en) | Insulated-gate bipolar transistor and manufacturing method thereof | |
| CN112382658B (en) | Low gate charge device with stepped discrete shield trenches and method of making the same | |
| JPWO2003065459A1 (en) | Semiconductor device | |
| CN110518059B (en) | Longitudinal floating field plate device with charge balance voltage-resisting layer and manufacturing method thereof | |
| CN111081779A (en) | Shielding gate trench type MOSFET and manufacturing method thereof | |
| CN106711191B (en) | Super junction semiconductor device with termination protection region and method of manufacturing the same | |
| US20220052170A1 (en) | Mosfet with distributed doped p-shield zones under trenches | |
| CN106129105B (en) | Trench gate power MOSFET and manufacturing method | |
| CN105529262A (en) | Vertical double diffused metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN114823872A (en) | Full-isolation substrate voltage-resistant power semiconductor device and manufacturing method thereof | |
| CN114188410A (en) | Shielding gate groove type power MOSFET device | |
| CN106158927B (en) | super junction semiconductor device with optimized switching characteristics and manufacturing method | |
| CN110416309B (en) | Super junction power semiconductor device and manufacturing method thereof | |
| CN107546274B (en) | LDMOS device with step-shaped groove | |
| CN210156383U (en) | Super junction power semiconductor device | |
| CN111916502B (en) | Split-gate power MOSFET device with high-doping layer and preparation method thereof | |
| CN116978928A (en) | Power semiconductor device based on active depletion mechanism and manufacturing method | |
| CN110212026A (en) | Superjunction MOS device structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20200317 Effective date of abandoning: 20240409 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20200317 Effective date of abandoning: 20240409 |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |