CN110212026A - Superjunction MOS device structure and preparation method thereof - Google Patents
Superjunction MOS device structure and preparation method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Abstract
The present invention provides a kind of superjunction MOS device structure and preparation method thereof.Superjunction MOS device structure includes the first conductivity type substrate；First conductive type epitaxial layer；Multiple second conductivity type columns；Multiple second conduction type well regions；First conduction type source region；Second conductive type of trap draw-out area；Grid；Gate spacer layer is located in grid, including spacer insulator layer and spaced metallization, spacer insulator layer are located at the upper surface of the first conductivity type columns, and spaced metallization is located at the upper surface of spacer insulator layer；Source metal, positioned at the surface of the second conductive type of trap draw-out area and the surface of the first conduction type source region；Drain metal layer, the surface positioned at the first conductivity type substrate far from the first conductive type epitaxial layer.The reverse recovery time that the present invention can be effectively reduced the intracorporal reverse recovery charge of superjunction MOS device, shorten superjunction devices reduces the noise jamming in switching process, further promotes superjunction devices performance thus, it is possible to reduce device loss.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, more particularly to a kind of superjunction MOS device structure and its preparation side
Method.
Background technique
Since latter stage eighties superjunction transistor (Super-Junction MOS, abbreviation SJ-MOS) structure is put forward for the first time
Since, superjunction MOS device is just small with its conducting resistance, the fast advantages such as low with switching loss of conducting speed and cause the wide of industry
General concern, structure are also constantly optimised.It is handed in existing superjunction transistor using by a series of p-types and N-type semiconductor thin layer
Traditional VDMOS (Vertical double-diffused MOSFET, vertical double diffusion are replaced for the doped region rearranged
Metal-oxide semiconductor (MOS)) the single drift region being lightly doped in device.In off-state, due to the depletion region in p-type and N-type layer
Electric field generation mutually compensates effect, and the doping concentration of p-type and N-type layer is allow to be made height without causing device electric breakdown strength
Decline；When conducting, the doping of this high concentration can turn it on resistance and be remarkably decreased.Because this special structure, makes
The performance for obtaining superjunction MOS device is better than traditional LDMOS device.
As previously mentioned, superjunction MOS device mutually compensates effect and reality using the depletion region electric field generation in p-type and N-type layer
Existing charge balance, thus to improve the breakdown voltage of superjunction devices, it is often desirable that superjunction devices has biggish thickness and lower
Doping concentration, but the area of this P-N junction that will lead to superjunction devices compare traditional power device, such as plane double diffusion
The big many of MOSFET (Planar DMOS), so that superjunction devices is during the work time, the intracorporal parasitic body diode of device exists
After conducting, biggish carrier injects so that reverse recovery charge Qrr and Reverse recovery peak point current Irrm is increased.Such as schemed
1 show the reverse recovery characteristic curve graph of common super-junction MOSFET device and planar MOSFET devices, it can be seen that in phase
Under same operating condition (such as identical operating temperature and current changing rate), super-junction MOSFET device compares planar MOSFET devices
Reverse recovery current it is bigger (the Reverse recovery peak point current of super node MOSFET be 14.1A and planar MOSFET devices it is reversed
Recovery peak point current is 12.6A).This causes the power loss in superjunction MOS device reversely restoring process to increase, and then leads to device
The deterioration of part performance and service life decline.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of superjunction MOS device structure and
Preparation method, for solving existing superjunction MOS device structure due to existing reverse recovery current is big caused by power damage
The problems such as device performance degradation and service life that consumption increases and thus causes decline.
In order to achieve the above objects and other related objects, the present invention provides a kind of superjunction MOS device structure comprising:
First conductivity type substrate；
First conductive type epitaxial layer, positioned at the surface of first conductivity type substrate；
Multiple second conductivity type columns are spaced apart in first conductive type epitaxial layer, each described second
It is separated out the first conductivity type columns between conductivity type columns and forms super-junction structure, the second conduction type is different from the first conductive-type
Type；
Multiple second conduction type well regions are located in first conductive type epitaxial layer, and it is conductive to be located at described second
The upper surface of type column；
First conduction type source region is located in the second conduction type well region；
Second conductive type of trap draw-out area, be located at the second conduction type well region in, and with first conduction type
Source region is disposed adjacent；
Grid, including gate oxide, grid conducting layer and interlayer dielectric layer；Wherein, the gate oxide is located at described the
The portion of upper surface of the upper surface of one conductivity type columns and the second conduction type well region；The grid conducting layer is located at described
The upper surface of gate oxide；The interlayer dielectric layer is located at upper surface and the side wall of the grid conducting layer；
Gate spacer layer is located in the grid, and the gate spacer layer includes spacer insulator layer and spaced metallization, institute
The upper surface that spacer insulator layer is located at first conductivity type columns is stated, the spaced metallization is located at the spacer insulator layer
The grid conducting layer is partitioned at least two parts by surface, the gate spacer layer；
Source metal, surface and the first conduction type source region positioned at second conductive type of trap draw-out area
Surface；
Drain metal layer, the surface positioned at first conductivity type substrate far from first conductive type epitaxial layer.
Optionally, there is spacing between the lower surface of second conductivity type columns and first conductivity type substrate,
There is spacing between the lower surface of the first conduction type source region and the lower surface of the second conduction type well region.
Optionally, the gate oxide is connected with the spacer insulator layer.
Optionally, first conduction type is N-type and second conduction type is p-type or first conductive-type
Type is p-type and second conduction type is N-type.
Optionally, the width of the spaced metallization is not more than the upper surface width of first conductivity type columns.
Optionally, the width of the spaced metallization is 2~3 μm.
Optionally, the material of the spacer insulator layer includes high K dielectric material.
Optionally, the spaced metallization is connected with the source metal.
Optionally, the doping concentration of the doping concentration of first conductivity type substrate and the first conduction type source region
Doping concentration that is identical and being greater than first conductive type epitaxial layer, the doping concentration of second conductive type of trap draw-out area
Greater than the doping concentration of second conductivity type columns.
The present invention also provides a kind of preparation method of superjunction MOS device structure, can be used for preparing as in aforementioned either a program
The superjunction MOS device structure, the preparation method comprising steps of
The first conductivity type substrate is provided, the first conductivity type substrate surface Yu Suoshu forms the first conduction type extension
Layer；
In forming multiple grooves being spaced apart in first conductive type epitaxial layer, multiple grooves are described
Multiple first conductivity type columns are separated out between in one conductive type epitaxial layer；
The groove is filled to form multiple second conductivity type columns, second conductivity type columns and described
One conductivity type columns form super-junction structure, and the second conduction type is different from the first conduction type；
Gate oxide and grid conducting layer are sequentially formed, the gate oxide is located at the upper table of first conductivity type columns
Face, the grid conducting layer are located at the upper surface of the gate oxide；
Second conductivity type columns are carried out ion implanting and carry out high temperature to push away trap in second conductivity type columns
Top form the second conduction type well region, the second conduction type well region extends to the lower surface of the gate oxide, shape
At the groove for running through the grid conducting layer, the upper surface of Yu Suoshu grid conducting layer and side wall form interlayer dielectric layer；
In forming the first conduction type source region and the second conductive type of trap draw-out area, institute in the second conduction type well region
It states the second conductive type of trap draw-out area and the first conduction type source region is disposed adjacent；
Source metal, spaced metallization and drain metal layer are formed, the source metal covering described second is conductive
The surface of type trap draw-out area and the surface of the first conduction type source region, the spaced metallization fill up the Gate Electrode Conductive
Groove in layer, the drain metal layer are located at first conductivity type substrate far from first conductive type epitaxial layer
Surface.
Optionally, the groove through the grid conducting layer also extends to the surface of first conductivity type columns, thus
Further include the steps that before forming the spaced metallization in the groove in formation spacer insulator layer in the groove, it is described
Spacer insulator layer is located at the surface of first conductivity type columns.
As described above, superjunction MOS device structure and preparation method thereof of the invention, has the advantages that the present invention
Introduce spacer insulator layer and spaced metallization in conventional gate structure to separate gate structure, the spaced metallization and
Spacer insulator layer and the first conductivity type columns of super-junction structure form MIS diode in the longitudinal direction, due to opening for MIS diode
Speed is closed picosecond magnitude (and the switching speed of general-purpose diode is nanosecond order), therefore superjunction MOS device can be effectively reduced
Intracorporal reverse recovery charge (Qrr), the reverse recovery time (Trr) for shortening superjunction devices are reversed thus, it is possible to reduce device
Loss in recovery process, reduce switching process in noise jamming, further promoted superjunction devices performance, improve device and
Using the stability of the system of the device, extend device service life.In addition, Schottky diode is compared, MIS diode
Reverse leakage is smaller, is conducive to the breakdown reverse voltage for further increasing device.
Detailed description of the invention
Fig. 1 is shown as the reverse recovery characteristic curve of super-junction MOSFET device in the prior art and planar MOSFET devices
Figure.
Fig. 2 is shown as the structural schematic diagram of the superjunction MOS device structure of the embodiment of the present invention one, and Fig. 2 is shown as simultaneously
The structural schematic diagram finally prepared according to the preparation method of embodiment two.
Fig. 3 is shown as the flow chart of the preparation method of the superjunction MOS device structure of the embodiment of the present invention two.
What each step of preparation method that Fig. 4~Fig. 7 is shown as the superjunction MOS device structure of the embodiment of the present invention two was presented
Structural schematic diagram.
Component label instructions
11 first conductivity type substrates
12 first conductive type epitaxial layers
13 second conductivity type columns
14 first conductivity type columns
15 second conduction type well regions
16 first conduction type source regions
17 second conductive type of trap draw-out areas
19 grids
191 gate oxides
192 grid conducting layers
193 interlayer dielectric layers
20 source metals
21 drain metal layers
22 gate spacer layers
221 spacer insulator layers
222 spaced metallizations
31 grooves
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to Fig. 2~Fig. 7.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in diagram then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
As shown in Fig. 2, the present embodiment provides a kind of superjunction MOS device structures comprising: the first conductivity type substrate 11；
First conductive type epitaxial layer 12, positioned at the surface of first conductivity type substrate 11；Multiple second conductivity type columns 13,
Every being distributed in first conductive type epitaxial layer 12, led with being separated out first between each second conductivity type columns 13
Electric type column 14 and be alternately arranged by first conductivity type columns 14 and second conductivity type columns 13 and formed super-junction structure,
Second conduction type is different from the first conduction type；Multiple second conduction type well regions 15 are located at outside first conduction type
Prolong in layer 12, and is located at the upper surface of second conductivity type columns 13, and the second conduction type well region 15 preferably extends over
The extremely portion of upper surface of first conductivity type columns 14, thus the upper surface width of first conductivity type columns 14 is less than it
Lower surface width；First conduction type source region 16 is located in the second conduction type well region 15；Second conductive type of trap is drawn
Area 17 is located in the second conduction type well region 15, and is disposed adjacent with the first conduction type source region 16；Grid 19,
Including gate oxide 191, grid conducting layer 192 and interlayer dielectric layer 193；Wherein, the gate oxide 191 is located at described first
The portion of upper surface of the upper surface of conductivity type columns 14 and the second conduction type well region 15, and the gate oxide 191 is excellent
Choosing and 16 part of the first conduction type source region contact；The grid conducting layer 192 is located at the upper table of the gate oxide 191
Face；The interlayer dielectric layer 193 is located at upper surface and the side wall of the grid conducting layer 192；Gate spacer layer 22 is located at described
In grid 19, the gate spacer layer 22 includes spacer insulator layer 221 and spaced metallization 222, the spacer insulator layer 221
In the upper surface of first conductivity type columns 14, the spaced metallization 222 is located at the surface of the spacer insulator layer 221,
The grid conducting layer 193 is partitioned at least two parts by the gate spacer layer 22；Source metal 20 is located at described second
The surface of conductive type of trap draw-out area 17 and the surface of the first conduction type source region 16；Drain metal layer 21 is located at described
Surface of first conductivity type substrate 11 far from first conductive type epitaxial layer 12.
The present invention introduces spacer insulator layer 221 and interval metal in 19 structure of grid of conventional superjunction MOS device
Layer 222 is with by 19 structure of grid, the especially described grid conducting layer 193 is spaced apart, the spaced metallization 222 and spacer insulator layer
221 and the first conductivity type columns 14 of super-junction structure form MIS diode (metal Metal- insulator in the longitudinal direction
Insulator- semiconductor Semiconductor), since the switching speed of MIS diode is in picosecond magnitude (and general-purpose diode
Switching speed be nanosecond order), therefore can be effectively reduced the intracorporal reverse recovery charge of superjunction MOS device (Qrr), shorten it is super
The reverse recovery time (Trr) of junction device reduces in switching process thus, it is possible to reduce the loss in device reversely restoring process
Noise jamming, further promote superjunction devices performance, improve the stability of device and the system using the device.This
Outside, Schottky diode is compared, the reverse leakage of MIS diode is smaller, is conducive to the reverse breakdown electricity for further increasing device
Pressure.
It should be noted that first conductive type epitaxial layer 12 in the present invention is by multiple second conduction types
Column 13 has been separated into multiple first conductivity type columns 14, and first conductivity type columns 14 and second conductivity type columns 13 are handed over
For being arranged to make up super-junction structure, thus first conductivity type columns, 14 essence is the one of first conductive type epitaxial layer 12
Its independent label is illustrated in the present embodiment by part, but super-junction structure in order to facilitate understanding.
Conduction type determines and adulterating different types of foreign atom in neutral radical bottom, such as toward the half of germanium silicon class
The group-v element (can provide electronics) that such as nitrogen, phosphorus, arsenic etc are adulterated in conductor substrate can form N-type conduction type；It mixes all
As the group iii elements (providing hole) of boron, aluminium etc can form P-type conduction type.As an example, N-type can be selected in the present embodiment
Semiconductor substrate, for example be doped with such as silicon substrate of the group-v element of nitrogen, phosphorus, arsenic etc or germanium substrate and led as described first
Electric type substrates 11, second conductivity type columns 13 are P-type conduction column at this time, such as to be doped with such as boron, aluminium etc
The polysilicon of group iii elements；Certainly, in another example, P-type semiconductor substrate can also be selected as first conductive-type
Type substrate 11, then second conductivity type columns 13 are N-type column, according to different needs can flexible choice, in the present embodiment not
Do stringent limitation.Certainly, in actual application, preferably N-type semiconductor substrate, such as silicon substrate or germanium substrate using N-type
NMOS tube is formed, because its conducting resistance is smaller, and manufacturing process is simpler.First conductivity type substrate 11 is highly doped
Substrate, doping concentration are usually 1019cm-3More than.The doping concentration of first conductive type epitaxial layer 12 is usually less than institute
The doping concentration of the first conductivity type substrate 11 is stated, for example is 1015~5*1016cm-3.First conductive type epitaxial layer 12
Thickness determine the breakdown voltage of device, thus it is theoretically more thicker better, but if too thick, will lead to the volume mistake of device
Greatly, in terms of comprehensive, the thickness of first conductive type epitaxial layer 12 is preferably between 20~60 μm.As an example, described
The width of two conductivity type columns 13 is 2~6um, doping concentration 3*1015cm-3.Certainly, it is designed according to different structures, it is above-mentioned
Parameter can also have other settings, not considered critical in the present embodiment.
In one example, the super junction device structure further includes the first conductive type buffer layer (not shown), is located at described
Between first conductivity type substrate 11 and first conductive type epitaxial layer 12, the doping of first conductive type buffer layer
Concentration can between first conductivity type substrate 11 and the doping concentration of first conductive type epitaxial layer 12, by
This can prevent the foreign atom of the first conductivity type substrate 11 described in elevated temperature processes from diffusing to first conductive-type
In type epitaxial layer 12, first conductive type epitaxial layer 12 is avoided (especially to correspond to the area of first conductivity type columns 14
Domain) doping concentration improve and cause the breakdown voltage of device to reduce.
In another example, between the lower surface of second conductivity type columns 13 and first conductivity type substrate 11
With spacing, described first between the lower surface of second conductivity type columns 13 and first conductivity type substrate 11 is led
Electric type epitaxial layer 12 acts as the effect of buffer layer, thus may not need in addition production buffer layer.
As an example, the following table of the lower surface of the first conduction type source region 16 and the second conduction type well region 15
There is spacing, which forms the channel of the second conduction type well region 15 between face.
As an example, the grid conducting layer 193 is partitioned at least two parts by the gate spacer layer 22；When the grid
When the grid conducting layer 193 is partitioned into two parts by interpolar interlayer 22, the gate spacer layer 22 is preferably placed at two parts institute
The middle of grid conducting layer 193 is stated, i.e., two-part 193 preferred size of the grid conducting layer is consistent, reversed extensive to ensure
Equalizing charge during multiple improves device performance.Certainly, in other examples, the gate spacer layer 22 can also be by institute
It is even more at three parts to state 193 uniform intervals of grid conducting layer, but the gate spacer layer 22 is preferably all located at described first
The upper surface of conductivity type columns 14.
As an example, the width of the spaced metallization 222 is not more than the upper surface of first conductivity type columns 14 (i.e.
The surface that the two is in contact) width and its width be preferably no greater than the grid conducting layer 192 width half, in order to avoid
Influence the performance of the grid 19.In a preferable example, the width of the spaced metallization 222 is 2~3 μm, more preferably
It is 2.5 μm, because inventor is verified discovery repeatedly, when the width of the spaced metallization 222 is at this section, by described
The MIS diode that spaced metallization 222, the spacer insulator layer 221 and first conductivity type columns 14 are formed in the longitudinal direction
It is showed on the reverse recovery characteristic for improving the superjunction MOS device especially prominent, the superjunction MOS device can be significantly reduced
Maximum reverse restoring current and reverse recovery time (shortening 20% or more).
As an example, the spaced metallization 222 is connected with the source metal 20, it can be ensured that device performance
Connection is good, meanwhile, the spaced metallization 222 and the source metal 20 can be used identical material and can be in same works
It is formed in skill, is conducive to simplify manufacture craft.
As an example, the doping concentration of first conductivity type substrate 11 and the first conduction type source region 16 are mixed
Miscellaneous concentration is identical and is greater than the doping concentration of first conductive type epitaxial layer 12, second conductive type of trap draw-out area 17
The doping concentration in area is greater than the doping concentration of second conductivity type columns 13.
As an example, the source metal 20 is preferably but not limited to aluminium layer, the source metal 20 is usually also located at
The surface of the interlayer dielectric layer 193 is to ensure the electric connection of device；The spaced metallization 222 equally can be aluminium layer；
The drain metal layer 21 can be one of titanium layer, nickel layer and silver layer or a variety of.
As an example, the preferred polysilicon layer of the grid conducting layer 192 because polysilicon is more resistant to high temperature, and with the grid
The boundary defect of oxide layer 191 is small, furthermore can change its work function by the impurity of doping opposed polarity to reduce device
Critical voltage.When selecting polysilicon layer to do the grid conducting layer 192, the thickness of the grid conducting layer 192 is preferably
3000~5000 angstroms；The gate oxide 191 is for realizing the grid conducting layer 192 and the second conduction type well region 15
Isolation, for the pressure resistance for guaranteeing the grid conducting layer 192, the thickness of the gate oxide 191 is preferably greater than 500 angstroms, material
It is of fine quality to select silica, it can specifically be realized by thermal oxidation technology；The interlayer dielectric layer 193 can be silicon nitride；It is described
Spacer insulator layer 221 is also possible to silica, but more preferably high K dielectric material, such as Al2O3, be conducive to further drop
The Leakage Current of low device improves its breakdown voltage.Certainly, in other examples, the material of each structure sheaf can also have other
Selection, such as the grid conducting layer 192 can be metal layer or metal silicide, specific unlimited.
Embodiment two
As shown in figure 3, can be used for preparing embodiment the present invention also provides a kind of preparation method of superjunction MOS device structure
Superjunction MOS device structure in one, thus the present embodiment is also applied for mutually isostructural associated description in embodiment one, for
It is not repeated one by one in succinct purpose the present embodiment.The preparation method of the superjunction MOS device structure of the present embodiment includes at least such as
Lower step:
Step S1: providing the first conductivity type substrate 11, and 11 surface of the first conductivity type substrate of Yu Suoshu forms first and leads
Electric type epitaxial layer 12；
Multiple grooves being spaced apart, multiple ditches are formed in S2: Yu Suoshu first conductive type epitaxial layer 12 of step
Slot in first conductive type epitaxial layer 12 between be separated out multiple first conductivity type columns 14；
Step S3: the groove is filled to form multiple second conductivity type columns 13, second conduction type
Column 13 and first conductivity type columns 14 form super-junction structure, and the second conduction type is different from the first conduction type；
Step S4: sequentially forming gate oxide 191 and grid conducting layer 192, and the gate oxide 191 is located at described first
The upper surface of conductivity type columns 14, the grid conducting layer 192 are located at the upper surface of the gate oxide 191；
Step S5: second conductivity type columns 13 are carried out ion implanting and carry out high temperature to push away trap to lead in described second
Second conduction type well region 15 is formed at the top of electric type column 13, and the second conduction type well region 15 extends to the gate oxidation
Layer 191 lower surface, formed run through the grid conducting layer 192 groove 31, the upper surface of Yu Suoshu grid conducting layer 192 and
Side wall forms interlayer dielectric layer 193；
The first conduction type source region 16 and the second conduction type are formed in S6: Yu Suoshu second conduction type well region 15 of step
Trap draw-out area 17, second conductive type of trap draw-out area 17 and the first conduction type source region 16 are disposed adjacent；
Step S7: source metal 20, spaced metallization 222 and drain metal layer 21, the source metal 20 are formed
Cover the surface of second conductive type of trap draw-out area 17 and the surface of the first conduction type source region 16, the interval gold
Belong to layer 222 and fill up the groove 31 in the grid conducting layer 192, the drain metal layer 21 is located at first conduction type lining
Surface of the bottom 11 far from first conductive type epitaxial layer 12.
Conduction type determines and adulterating different types of foreign atom in neutral radical bottom, such as toward the half of germanium silicon class
The group-v element (can provide electronics) that such as nitrogen, phosphorus, arsenic etc are adulterated in conductor substrate can form N-type conduction type；It mixes all
As the group iii elements (providing hole) of boron, aluminium etc can form P-type conduction type.As an example, N-type can be selected in the present embodiment
Semiconductor substrate, for example be doped with such as silicon substrate of the group-v element of nitrogen, phosphorus, arsenic etc or germanium substrate and led as described first
Electric type substrates 11, second conductivity type columns 13 are P-type conduction column at this time, such as to be doped with such as boron, aluminium etc
The polysilicon of group iii elements；Certainly, in another example, P type substrate can also be selected as first conductivity type substrate
11, then second conductivity type columns 13 are N-type column, according to different needs can flexible choice, do not do in the present embodiment stringent
Limitation.Certainly, in actual application, preferred N-type semiconductor substrate, for example NMOS is formed using N-type silicon substrate or germanium substrate
Pipe, because its conducting resistance is smaller, and manufacturing process is simpler.First conductivity type substrate 11 is highly doped substrate,
Doping concentration is usually 1019cm-3More than.The doping concentration of first conductive type epitaxial layer 12 is usually less than described first
The doping concentration of conductivity type substrate 11, for example be 1015~5*1016cm-3.The thickness of first conductive type epitaxial layer 12
Determine the breakdown voltage of device, thus it is theoretically more thicker better, and but if too thick, the volume that will lead to device is excessive, comprehensive
For, the thickness of first conductive type epitaxial layer 12 is preferably between 20~60 μm.As an example, second conductive-type
The width of type column 13 is 2~6um, doping concentration 3*1015cm-3.Certainly, it is designed according to different structures, above-mentioned parameter may be used also
To there is other settings, not considered critical in the present embodiment.
As an example, the method for forming first conductive type epitaxial layer 12 is preferably vapor-deposited, during the deposition process
By adjusting the foreign atom concentration of incorporation to realize required doping concentration, the doping of first conductive type epitaxial layer 12
Concentration is preferably smaller than the doping concentration of first conductivity type substrate 11.
As an example, in the step S2, it is different according to the specific material of first conductive type epitaxial layer 12, it is optional
The groove is formed with wet process or dry etching.Certainly, it will be appreciated to those of skill in the art that the step usually requires to borrow
It helps photomask to carry out photoetching to define the location and shape of groove, the groove is just formed by etching later.The present embodiment
In, the depth of the groove is less than the thickness of first conductive type epitaxial layer 12, thus the groove and described first is led
There is spacing, first conductive type epitaxial layer 12 between the spacing will be used as subsequent shape between electric type substrates 11
At first conductivity type columns 14 and first conductivity type substrate 11 between buffer layer.Certainly, show in other
In example, if being formed with buffer layer between first conductive type epitaxial layer 12 and first conductivity type substrate 11,
The depth of groove described in the step can be identical with the thickness of first conductive type epitaxial layer 12.Buffer layer is arranged can be with
Prevent the impurity diffusion of the first conductivity type substrate 11 described in subsequent elevated temperature processes to first conductivity type columns
In 14.
As an example, in the step S3 equally second conductivity type columns 13 can be formed using epitaxy technique, pass through
The obtained structure of the step is as shown in Figure 4.
As an example, the method for forming the gate oxide 191 in the step S4 can be heavy for thermal oxidation method and gas phase
Product method, the preferred silica of the gate oxide 191, and preferably formed by thermal oxidation method, be conducive to needed for quickly being formed
The gate oxide 191 of thickness.For the pressure resistance for improving device, the thickness of the gate oxide 191 is preferably greater than 500 angstroms；The grid
The preferred polysilicon of pole conductive layer 192, and also preferably through being epitaxially formed because polysilicon is more resistant to high temperature, and with the grid oxygen
The boundary defect for changing layer 191 is small, furthermore can change its work function by the impurity of doping opposed polarity to reduce device
Critical voltage.When selecting polysilicon layer to do the grid conducting layer 192, the thickness of the grid conducting layer 192 is preferably
3000~5000 angstroms.
Step S5 is carried out later, is injected the second conductive type impurity atom in the second conductivity type columns of Xiang Suoshu 13, is gone forward side by side
Row high temperature pushes away trap, for example anneals 1~10 hour (with specific reference to doping concentration and depth and device under 1000~1200 DEG C of high temperature
Depending on the parameters such as part size), ion implanted and high temperature, which pushes away the second conduction type well region 15 formed after trap, will extend into
The lower surface of the gate oxide 191, i.e., the described second conduction type well region 15 are connected with the gate oxide 191, obtain
Structure it is as shown in Figure 5.In this process, the grid conducting layer 192 plays the role of exposure mask without in addition by light
Exposure mask (Mask), advantageously reduces production cost.Then the ditch for running through the grid conducting layer 192 can be formed by etching
Slot 31 can form the interlayer dielectric layer 193 by vapor deposition later, and the interlayer dielectric layer 193, which is located at the grid, leads
The side wall of electric layer 192 and surface, obtained structure are as shown in Figure 6.The interlayer dielectric layer 193 can be silicon nitride.Certainly, another
In one example, the groove 31 may also extend through the surface of the gate oxide 191 and first conductivity type columns 14 of going directly,
In this case, high K dielectric material can be used in the interlayer dielectric layer 193, thus in the mistake for forming the interlayer dielectric layer 193
Cheng Zhong, the interlayer dielectric layer 193 can synchronize the table for being formed in 31 bottom of groove namely first conductivity type columns 14
Face and as required spacer insulator layer 221.Depth based on the groove 31 is different, and subsequent technique is slightly different, to this
It will be continued to explain in subsequent content.And can be formed in the interlayer dielectric layer 193 in the step contact hole (not shown) so as to
The grid conducting layer 192 is electrically drawn in subsequent.Certainly, the step of forming the contact hole can also shape in the subsequent process
At as long as before forming the source metal 20.Certainly, in other examples, described second can also be initially formed to lead
Electric type well region 15 re-forms 191 layers of the gate oxide and the interlayer dielectric layer 193, does not do stringent limit in the present embodiment
System.
As an example, equally forming the first conduction type source region 16 and described by ion implanting in the step S6
Second conductive type of trap draw-out area 17, the first conduction type source region 16 and the gate oxide 191 are in contact and described
The side wall of the side wall of one conduction type source region 16 and the second conduction type well region 15 has spacing, which constitutes described the
The channel of two conduction type well regions 15.The structure chart obtained through the step is as shown in Figure 7.
As an example, in the step S7 source metal can be formed by physical vapour deposition (PVD) or electroplating technology
20, spaced metallization 222 and drain metal layer 21, and the source metal 20 is usually also located at the interlayer dielectric layer 193
Surface to ensure the electric connection of device.And it should be noted that if the Gate Electrode Conductive is formed in the step S4
It then further include in the groove 31 before the step S7 if groove 31 between layer 192 also extends through the gate oxide 191
The step of being inside initially formed spacer insulator layer 221, the spacer insulator layer 221 are located at the surface of first conductivity type columns 14,
And the spacer insulator layer 221 is connected with the gate oxide 191, to protect the device surface not to be contaminated.Described
The thickness of used outside insulated layer 221 is usually more than the thickness of the gate oxide 191, the thickness of the preferably smaller than described gate oxide 191
Degree is conducive to the reverse recovery characteristic for improving device in this way, and material can be silica, but preferably high K dielectric material, than
Such as Al2O3, be conducive to the Leakage Current for reducing device, improve the breakdown voltage of device.If formed in 31 bottom of groove
If the interlayer dielectric layer 193 is different from the required material of spacer insulator layer 221, then the spacer insulator layer is being formed
Further include the steps that the interlayer dielectric layer 193 for first removing 31 bottom of groove before 221.Certainly, in other examples,
The spacer insulator layer 221 can also directly utilize the gate oxide 191, i.e., the described groove 31 does not extend to the gate oxidation
In layer 191, the gate oxide 191 of 31 bottom of groove is used as the spacer insulator layer 221, is conducive to technique in this way and simplifies,
Or can be with the gate oxide 191 of etch away sections thickness, remaining part is as the spacer insulator layer 221.This reality
It applies and does not do stringent limitation in example.It collectively forms gate spacer layer 22 by the grid 19, especially with the spaced metallization 222
It is that the grid conducting layer 192 of the grid 19 separates.It in another example, can also be right before forming the drain metal layer 21
First conductivity type substrate 11 carries out the back side (forming the surface of the drain metal layer 21) grinding further to subtract
Small device size.
As an example, the spaced metallization 222 and the source metal 20 can be formed in same technique, thus
The spaced metallization 222 and the material of the source metal 20 can be identical, for example can be but be not limited to aluminium, described
Drain metal layer is preferably but not limited to one of nickel, titanium or silver or a variety of.The spaced metallization 222 and the source metal
Layer 20 is preferably interconnecting.Superjunction MOS device structure as described in Figure 2 can be obtained upon completion of this step.The interval gold
The first conductivity type columns 14 for belonging to layer 222, spacer insulator layer 221 and super-junction structure form MIS diode in the longitudinal direction, help
In the performance for improving the superjunction MOS device structure.
As described above, superjunction MOS device structure and preparation method thereof of the invention, has the following beneficial effects: the present invention
Spacer insulator layer and spaced metallization are introduced in the gate structure of conventional superjunction MOS device to separate gate structure,
The spaced metallization and spacer insulator layer and the first conductivity type columns of super-junction structure form MIS diode (gold in the longitudinal direction
Belong to Metal- insulator Insulator- semiconductor Semiconductor), since the switching speed of MIS diode is in a picosecond amount
Grade (and the switching speed of general-purpose diode is nanosecond order), therefore the intracorporal Reverse recovery of superjunction MOS device can be effectively reduced
Charge (Qrr), the reverse recovery time (Trr) for shortening superjunction devices, thus, it is possible to reduce the damage in device reversely restoring process
Consumption reduces the noise jamming in switching process, further promotes superjunction devices performance, improves device and using the device
The stability of system.In addition, comparing Schottky diode, the reverse leakage of MIS diode is smaller, is conducive to further increase device
The breakdown reverse voltage of part.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial exploitation value
Value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (10)
1. a kind of superjunction MOS device structure characterized by comprising
First conductivity type substrate；
First conductive type epitaxial layer, positioned at the surface of first conductivity type substrate；
Multiple second conductivity type columns are spaced apart in first conductive type epitaxial layer, with conductive each described second
It is separated out the first conductivity type columns between type column and forms super-junction structure, the second conduction type is different from the first conduction type；
Multiple second conduction type well regions are located in first conductive type epitaxial layer, and are located at second conduction type
The upper surface of column；
First conduction type source region is located in the second conduction type well region；
Second conductive type of trap draw-out area, be located at the second conduction type well region in, and with the first conduction type source region
It is disposed adjacent；
Grid, including gate oxide, grid conducting layer and interlayer dielectric layer；Wherein, the gate oxide is located at described first and leads
The portion of upper surface of the upper surface of electric type column and the second conduction type well region；The grid conducting layer is located at the grid oxygen
Change the upper surface of layer；The interlayer dielectric layer is located at upper surface and the side wall of the grid conducting layer；
Gate spacer layer is located in the grid, and the gate spacer layer includes spacer insulator layer and spaced metallization, between described
Used outside insulated layer is located at the upper surface of first conductivity type columns, and the spaced metallization is located at the upper table of the spacer insulator layer
The grid conducting layer is partitioned at least two parts by face, the gate spacer layer；
Source metal, positioned at the surface of second conductive type of trap draw-out area and the table of the first conduction type source region
Face；
Drain metal layer, the surface positioned at first conductivity type substrate far from first conductive type epitaxial layer.
2. superjunction MOS device structure according to claim 1, it is characterised in that: the following table of second conductivity type columns
There is spacing, the lower surface of the first conduction type source region and described second is led between face and first conductivity type substrate
There is spacing between the lower surface of electric type well region.
3. superjunction MOS device structure according to claim 1, it is characterised in that: the gate oxide and it is described between completely cut off
Edge layer is connected.
4. superjunction MOS device structure according to claim 1, it is characterised in that: first conduction type is N-type and institute
State that the second conduction type is p-type or first conduction type is p-type and second conduction type is N-type.
5. superjunction MOS device structure according to claim 1, it is characterised in that: the width of the spaced metallization is little
In the upper surface width of first conductivity type columns.
6. superjunction MOS device structure according to claim 1, it is characterised in that: the width of the spaced metallization be 2~
3μm。
7. superjunction MOS device structure according to claim 1, it is characterised in that: the material of the spacer insulator layer includes
High K dielectric material.
8. superjunction MOS device structure according to any one of claims 1 to 7, it is characterised in that: first conduction type
The doping concentration of substrate is identical with the doping concentration of the first conduction type source region and is greater than the first conduction type extension
The doping concentration of layer, the doping that the doping concentration of second conductive type of trap draw-out area is greater than second conductivity type columns are dense
Degree.
9. a kind of preparation method of superjunction MOS device structure, which is characterized in that comprising steps of
The first conductivity type substrate is provided, the first conductivity type substrate surface Yu Suoshu forms the first conductive type epitaxial layer；
In forming multiple grooves being spaced apart in first conductive type epitaxial layer, multiple grooves are led described first
Multiple first conductivity type columns are separated out between in electric type epitaxial layer；
The groove is filled to form multiple second conductivity type columns, second conductivity type columns and described first are led
Electric type column forms super-junction structure, and the second conduction type is different from the first conduction type；
Gate oxide and grid conducting layer are sequentially formed, the gate oxide is located at the upper surface of first conductivity type columns,
The grid conducting layer is located at the upper surface of the gate oxide；
Second conductivity type columns are carried out ion implanting and carry out high temperature to push away trap in the upper of second conductivity type columns
Portion forms the second conduction type well region, and the second conduction type well region extends to the lower surface of the gate oxide；Formation is passed through
The groove of the grid conducting layer is worn, the upper surface of Yu Suoshu grid conducting layer and side wall form interlayer dielectric layer；
In forming the first conduction type source region and the second conductive type of trap draw-out area in the second conduction type well region, described
Two conductive type of trap draw-out areas and the first conduction type source region are disposed adjacent；
Source metal, spaced metallization and drain metal layer are formed, the source metal covers second conduction type
The surface of trap draw-out area and the surface of the first conduction type source region, the spaced metallization fill up in the grid conducting layer
Groove, the drain metal layer is located at table of first conductivity type substrate far from first conductive type epitaxial layer
Face.
10. preparation method according to claim 9, it is characterised in that: the groove through the grid conducting layer also extends
To the surface of first conductivity type columns；Forming the spaced metallization in the groove further includes before in the groove
The step of interior formation spacer insulator layer, the spacer insulator layer are located at the surface of first conductivity type columns.
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Inventor after: Luo Jiexin Inventor after: Chai Zhan Inventor after: Xu Dapeng Inventor after: Huang Xiaoyan Inventor before: Luo Jiexin Inventor before: Xue Zhongying Inventor before: Chai Zhan Inventor before: Xu Dapeng Inventor before: Huang Xiaoyan |