CN110212026B - Super junction MOS device structure and preparation method thereof - Google Patents
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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Abstract
The invention provides a super junction MOS device structure and a preparation method thereof. The super junction MOS device structure comprises a first conduction type substrate; a first conductivity type epitaxial layer; a plurality of second conductive type pillars; a plurality of second conductivity type well regions; a first conductive type source region; a second conductivity type well lead-out region; a gate electrode; the grid spacing layer is positioned in the grid and comprises a spacing insulating layer and a spacing metal layer, the spacing insulating layer is positioned on the upper surface of the first conductive type column, and the spacing metal layer is positioned on the upper surface of the spacing insulating layer; the source metal layer is positioned on the surface of the second conduction type well lead-out region and the surface of the first conduction type source region; and the drain metal layer is positioned on the surface of the first conduction type substrate far away from the first conduction type epitaxial layer. The invention can effectively reduce the reverse recovery charge in the super junction MOS device body and shorten the reverse recovery time of the super junction device, thereby reducing the device loss, reducing the noise interference in the switching process and further improving the performance of the super junction device.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to a super junction MOS device structure and a preparation method thereof.
Background
Since the last Super-Junction MOS (SJ-MOS) structure was proposed for the first time in the 80 s, the Super-Junction MOS device attracts wide attention in the industry due to its advantages of small on-resistance, fast on-speed, and low switching loss, and its structure is also continuously optimized. In the existing super junction transistor, a doped region composed of a series of P-type and N-type semiconductor thin layers which are alternately arranged is adopted to replace a single lightly doped drift region in a conventional VDMOS (Vertical double-diffused metal oxide semiconductor) device. When the device is in a cut-off state, because depletion region electric fields in the P type and N type layers generate a mutual compensation effect, the doping concentration of the P type and N type layers can be very high, and the breakdown voltage of the device cannot be reduced; this high concentration doping can significantly reduce the on-resistance of the device when it is turned on. Due to the special structure, the performance of the super junction MOS device is superior to that of the traditional LDMOS device.
As mentioned above, the super junction MOS device utilizes the depletion region electric fields in the P-type and N-type layers to generate the mutual compensation effect to achieve the charge balance, so in order to increase the breakdown voltage of the super junction device, it is usually desirable that the super junction device has a larger thickness and a lower doping concentration, but this may result in that the area of the P-N junction of the super junction device is much larger than that of the conventional power device, such as planar double-diffused mosfet (planar dmos), so that during the operation of the super junction device, after the parasitic diode in the device body is turned on, the larger carrier injection may increase the reverse recovery charge Qrr and the reverse recovery peak current Irrm. For example, as shown in fig. 1, a graph of reverse recovery characteristics of a conventional super junction MOSFET device and a planar MOSFET device, it can be seen that under the same operating conditions (e.g., the same operating temperature and the same current change rate), the super junction MOSFET device has a larger reverse recovery current than the planar MOSFET device (the reverse recovery peak current of the super junction MOSFET is 14.1A and the reverse recovery peak current of the planar MOSFET device is 12.6A). This results in increased power loss during reverse recovery of the superjunction MOS device, which in turn leads to degraded device performance and reduced lifetime.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a super junction MOS device structure and a method for manufacturing the same, which are used to solve the problems of increased power loss and the resulting degradation of device performance and reduced service life of the super junction MOS device structure due to the large reverse recovery current.
To achieve the above and other related objects, the present invention provides a super junction MOS device structure, including:
a first conductive type substrate;
the first conductive type epitaxial layer is positioned on the surface of the first conductive type substrate;
a plurality of second conductive type columns distributed in the first conductive type epitaxial layer at intervals so as to form a super junction structure by separating the first conductive type columns among the second conductive type columns, wherein the second conductive type is different from the first conductive type;
a plurality of second conductivity type well regions located within the first conductivity type epitaxial layer and located on upper surfaces of the second conductivity type pillars;
a first conductivity type source region located in the second conductivity type well region;
a second conductivity type well lead-out region located in the second conductivity type well region and adjacent to the first conductivity type source region;
the grid comprises a grid oxide layer, a grid conducting layer and an interlayer dielectric layer; wherein the gate oxide layer is located on the upper surface of the first conductive type column and part of the upper surface of the second conductive type well region; the grid conducting layer is positioned on the upper surface of the grid oxide layer; the interlayer dielectric layer is positioned on the upper surface and the side wall of the grid conducting layer;
a gate spacer layer located within the gate, the gate spacer layer including a spacer insulating layer and a spacer metal layer, the spacer insulating layer being located on an upper surface of the first conductivity type pillar, the spacer metal layer being located on a surface of the spacer insulating layer, the gate spacer layer spacing the gate conductive layer into at least two portions;
the source metal layer is positioned on the surface of the second conduction type well lead-out region and the surface of the first conduction type source region;
and the drain metal layer is positioned on the surface of the first conduction type substrate far away from the first conduction type epitaxial layer.
Optionally, a space is provided between a lower surface of the second conductive type pillar and the first conductive type substrate, and a space is provided between a lower surface of the first conductive type source region and a lower surface of the second conductive type well region.
Optionally, the gate oxide layer and the spacer insulating layer are connected.
Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
Optionally, a width of the spacer metal layer is not greater than an upper surface width of the first conductive type pillar.
Optionally, the width of the spacing metal layer is 2-3 μm.
Optionally, the material of the spacer insulating layer comprises a high-K dielectric material.
Optionally, the spacer metal layer and the source metal layer are connected.
Optionally, the doping concentration of the first conductivity-type substrate is the same as the doping concentration of the first conductivity-type source region and is greater than the doping concentration of the first conductivity-type epitaxial layer, and the doping concentration of the second conductivity-type well lead-out region is greater than the doping concentration of the second conductivity-type column.
The invention also provides a preparation method of the super junction MOS device structure, which can be used for preparing the super junction MOS device structure in any scheme, and the preparation method comprises the following steps:
providing a first conductive type substrate, and forming a first conductive type epitaxial layer on the surface of the first conductive type substrate;
forming a plurality of grooves distributed at intervals in the first conductive type epitaxial layer, wherein the grooves form a plurality of first conductive type columns at intervals in the first conductive type epitaxial layer;
filling the trenches to form a plurality of second conductivity type pillars, the second conductivity type pillars and the first conductivity type pillars forming a super junction structure, the second conductivity type being different from the first conductivity type;
sequentially forming a gate oxide layer and a gate conducting layer, wherein the gate oxide layer is positioned on the upper surface of the first conductive type column, and the gate conducting layer is positioned on the upper surface of the gate oxide layer;
performing ion implantation on the second conductive type column and performing high-temperature drive-in to form a second conductive type well region on the upper part of the second conductive type column, wherein the second conductive type well region extends to the lower surface of the gate oxide layer to form a groove penetrating through the gate conductive layer, and an interlayer dielectric layer is formed on the upper surface and the side wall of the gate conductive layer;
forming a first conduction type source region and a second conduction type well leading-out region in the second conduction type well region, wherein the second conduction type well leading-out region and the first conduction type source region are arranged adjacently;
and forming a source metal layer, an interval metal layer and a drain metal layer, wherein the source metal layer covers the surface of the second conductive type well lead-out region and the surface of the first conductive type source region, the interval metal layer fills the groove in the grid conductive layer, and the drain metal layer is positioned on the surface of the first conductive type substrate far away from the first conductive type epitaxial layer.
Optionally, the trench penetrating through the gate conductive layer further extends to the surface of the first conductive type pillar, and thus before forming the spacer metal layer in the trench, a step of forming a spacer insulating layer in the trench is further included, the spacer insulating layer being located on the surface of the first conductive type pillar.
As described above, the super junction MOS device structure and the manufacturing method thereof of the present invention have the following beneficial effects: according to the invention, the spacing insulating layer and the spacing metal layer are introduced into the conventional gate structure to separate the gate structure, the MIS diode is formed on the spacing metal layer, the spacing insulating layer and the first conduction type column of the super junction structure in the longitudinal direction, and as the switching speed of the MIS diode is in picosecond magnitude (and the switching speed of the common diode is in nanosecond magnitude), the reverse recovery charge (Qrr) in the super junction MOS device body can be effectively reduced, and the reverse recovery time (Trr) of the super junction device is shortened, so that the loss in the reverse recovery process of the device can be reduced, the noise interference in the switching process is reduced, the performance of the super junction device is further improved, the stability of the device and a system adopting the device is improved, and the service life of the device is prolonged. In addition, compared with a Schottky diode, the reverse leakage of the MIS diode is smaller, and the reverse breakdown voltage of the device is further improved.
Drawings
Fig. 1 is a graph showing reverse recovery characteristics of a super junction MOSFET device and a planar MOSFET device in the prior art.
Fig. 2 is a schematic structural diagram of a super junction MOS device structure according to a first embodiment of the present invention, and fig. 2 is a schematic structural diagram finally prepared according to a second embodiment of the present invention.
Fig. 3 is a flowchart illustrating a method for manufacturing a super junction MOS device structure according to a second embodiment of the present invention.
Fig. 4 to 7 show schematic structural diagrams of steps of a method for manufacturing a super junction MOS device structure according to a second embodiment of the present invention.
Description of the element reference numerals
11 first conductivity type substrate
12 epitaxial layer of the first conductivity type
13 second conductivity type pillar
14 pillars of the first conductivity type
15 second conductivity type well region
16 source region of the first conductivity type
17 well lead-out region of second conductivity type
19 grid electrode
191 gate oxide layer
192 Gate conductive layer
193 interlayer dielectric layer
20 source metal layer
21 drain metal layer
22 gate spacer layer
221 space insulating layer
222 spacer metal layer
31 groove
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to 7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
As shown in fig. 2, the present embodiment provides a super junction MOS device structure, which includes: a first conductivity type substrate 11; a first conductivity type epitaxial layer 12 on a surface of the first conductivity type substrate 11; a plurality of second conductive type pillars 13 spaced apart from each other in the first conductive type epitaxial layer 12, so as to form first conductive type pillars 14 between the second conductive type pillars 13, and the first conductive type pillars 14 and the second conductive type pillars 13 are alternately arranged to form a super junction structure, wherein the second conductive type is different from the first conductive type; a plurality of second conductivity-type well regions 15 located within the first conductivity-type epitaxial layer 12 and on the upper surfaces of the second conductivity-type pillars 13, and the second conductivity-type well regions 15 preferably extend to the upper surfaces of the portions of the first conductivity-type pillars 14, so that the widths of the upper surfaces of the first conductivity-type pillars 14 are smaller than the widths of the lower surfaces thereof; a first conductivity type source region 16 located in the second conductivity type well region 15; a second conductivity type well lead-out region 17 located in the second conductivity type well region 15 and disposed adjacent to the first conductivity type source region 16; a gate 19 including a gate oxide layer 191, a gate conductive layer 192 and an interlayer dielectric layer 193; wherein the gate oxide layer 191 is located on the upper surface of the first conductive type pillar 14 and part of the upper surface of the second conductive type well region 15, and the gate oxide layer 191 is preferably partially in contact with the first conductive type source region 16; the gate conducting layer 192 is positioned on the upper surface of the gate oxide layer 191; the interlayer dielectric layer 193 is positioned on the upper surface and the side wall of the gate conductive layer 192; a gate spacer layer 22 located within the gate 19, the gate spacer layer 22 comprising a spacer insulating layer 221 and a spacer metal layer 222, the spacer insulating layer 221 being located on the upper surface of the first conductive type pillar 14, the spacer metal layer 222 being located on the surface of the spacer insulating layer 221, the gate spacer layer 22 spacing the gate conductive layer 193 into at least two parts; a source metal layer 20 located on the surface of the second conductive type well lead-out region 17 and the surface of the first conductive type source region 16; and a drain metal layer 21 located on a surface of the first conductive type substrate 11 away from the first conductive type epitaxial layer 12.
The present invention introduces a spacer insulating layer 221 and a spacer metal layer 222 in the gate 19 structure of the conventional superjunction MOS device to space the gate 19 structure, particularly the gate conductive layer 193, the spacer Metal layer 222 and the spacer insulating layer 221 and the first conductive type pillar 14 of the super junction structure form an MIS diode (Metal-Insulator-Semiconductor) in the longitudinal direction, because the switching speed of the MIS diode is in picosecond magnitude (and the switching speed of the common diode is in nanosecond magnitude), the reverse recovery charge (Qrr) in the super junction MOS device body can be effectively reduced, the reverse recovery time (Trr) of the super junction device is shortened, therefore, the loss of the device in the reverse recovery process can be reduced, the noise interference in the switching process is reduced, the performance of the super junction device is further improved, and the stability of the device and a system adopting the device is improved. In addition, compared with a Schottky diode, the reverse leakage of the MIS diode is smaller, and the reverse breakdown voltage of the device is further improved.
It should be noted that, in the present invention, the first conductivity type epitaxial layer 12 is partitioned into the plurality of first conductivity type pillars 14 by the plurality of second conductivity type pillars 13, and the first conductivity type pillars 14 and the second conductivity type pillars 13 are alternately arranged to form a super junction structure, so that the first conductivity type pillars 14 are substantially a part of the first conductivity type epitaxial layer 12, but for understanding of the super junction structure, separate reference numerals are used in this embodiment for description.
The conductivity type is determined by doping different types of impurity atoms in a neutral base, for example, a semiconductor substrate of the germanium-silicon type is doped with a group-five element (which can provide electrons) such as nitrogen, phosphorus, arsenic, and the like to form an N-type conductivity; p-type conductivity may be formed by doping group iii elements such as boron, aluminum, etc., to provide holes. As an example, in the present embodiment, an N-type semiconductor substrate, such as a silicon substrate or a germanium substrate doped with a group five element such as nitrogen, phosphorus, arsenic, etc., may be used as the first conductive type substrate 11, and in this case, the second conductive type column 13 is a P-type conductive column, such as polysilicon doped with a group three element such as boron, aluminum, etc.; of course, in another example, a P-type semiconductor substrate may also be used as the first conductive type substrate 11, and the second conductive type column 13 is an N-type column, which can be flexibly selected according to different requirements, and is not limited in this embodiment. Of course, in practical applications, an N-type semiconductor substrate, such as a silicon substrate or a germanium substrate of N-type, is preferable to form the NMOS transistor because its on-resistance is smaller and the manufacturing process is simpler. The substrate 11 of the first conductivity type is a highly doped substrate with a doping concentration of typically 10 19 cm -3 The above. The doping concentration of the first conductivity type epitaxial layer 12 is generally lower than the doping concentration of the first conductivity type substrate 11, for example 10 15 ～5*10 16 cm -3 . The thickness of the first conductivity type epitaxial layer 12 determines the breakdown voltage of the device, so that theoretically, the thicker the device is better, but if the thickness is too thick, the device is too large, and in sum, the thickness of the first conductivity type epitaxial layer 12 is preferably 20-60 μm. As an example, the second conductive type pillar 13 has a width of 2 to 6um and a doping concentration of 3 x 10 15 cm -3 . Of course, the above parameters may be set in other ways according to different structural designs, and this embodiment is not limited strictly.
In an example, the super junction device structure further includes a first conductivity type buffer layer (not shown) located between the first conductivity type substrate 11 and the first conductivity type epitaxial layer 12, and a doping concentration of the first conductivity type buffer layer may be between doping concentrations of the first conductivity type substrate 11 and the first conductivity type epitaxial layer 12, so that impurity atoms of the first conductivity type substrate 11 may be prevented from diffusing into the first conductivity type epitaxial layer 12 during a high temperature process, and a breakdown voltage of the device may be prevented from being reduced due to an increase in the doping concentration of the first conductivity type epitaxial layer 12 (especially, a region corresponding to the first conductivity type pillar 14).
In another example, there is a space between the lower surface of the second conductive type pillar 13 and the first conductive type substrate 11, and the first conductive type epitaxial layer 12 between the lower surface of the second conductive type pillar 13 and the first conductive type substrate 11 functions as a buffer layer, so that it may be unnecessary to additionally fabricate a buffer layer.
As an example, a lower surface of the first conductivity type source region 16 and a lower surface of the second conductivity type well region 15 have a space therebetween, the space forming a channel of the second conductivity type well region 15.
As an example, the gate spacer layer 22 separates the gate conductive layer 193 into at least two parts; when the gate spacer layer 22 separates the gate conductive layer 193 into two parts, the gate spacer layer 22 is preferably located at the middle of the two parts of the gate conductive layer 193, that is, the two parts of the gate conductive layer 193 are preferably uniform in size, so as to ensure charge equalization during reverse recovery and improve device performance. Of course, in other examples, the gate spacers 22 may also evenly space the gate conductive layer 193 into three or more portions, but the gate spacers 22 are preferably all located on the upper surface of the first conductivity type pillar 14.
As an example, the width of the spacer metal layer 222 is not greater than the width of the upper surface of the first conductive type pillar 14 (i.e., the surface where the two are in contact) and preferably not greater than half the width of the gate conductive layer 192 so as not to affect the performance of the gate electrode 19. In a preferred example, the width of the spacer metal layer 222 is 2 to 3 μm, and more preferably 2.5 μm, because the inventors repeatedly verified that, when the width of the spacer metal layer 222 is in this range, the MIS diode formed by the spacer metal layer 222, the spacer insulating layer 221, and the first conductivity type pillar 14 in the longitudinal direction is particularly significant in improving the reverse recovery characteristic of the superjunction MOS device, and the maximum reverse recovery current and the reverse recovery time of the superjunction MOS device can be significantly reduced (by 20% or more).
As an example, the spacer metal layer 222 and the source metal layer 20 are connected to ensure good connection of device performance, and meanwhile, the spacer metal layer 222 and the source metal layer 20 may be made of the same material and may be formed in the same process, which is beneficial to simplifying the manufacturing process.
As an example, the doping concentration of the first conductive type substrate 11 and the doping concentration of the first conductive type source region 16 are the same and greater than the doping concentration of the first conductive type epitaxial layer 12, and the doping concentration of the second conductive type well lead-out region 17 is greater than the doping concentration of the second conductive type column 13.
By way of example, the source metal layer 20 is preferably, but not limited to, an aluminum layer, and the source metal layer 20 is usually also located on the surface of the interlayer dielectric layer 193 to ensure electrical connection of the device; the spacer metal layer 222 may also be an aluminum layer; the drain metal layer 21 may be one or more of a titanium layer, a nickel layer, and a silver layer.
As an example, the gate conductive layer 192 is preferably a polysilicon layer because polysilicon is more resistant to high temperature and has small interface defects with the gate oxide layer 191, and furthermore, the work function thereof can be changed by doping impurities of different polarities to lower the threshold voltage of the device. When a polysilicon layer is selected as the gate conductive layer 192, the thickness of the gate conductive layer 192 is preferably 3000 to 5000 angstroms; the gate oxide layer 191 is used to realize the isolation between the gate conductive layer 192 and the second conductive type well region 15, in order to ensure the gate conductive layer 192The gate oxide layer 191 is preferably thicker than 500 angstroms and is preferably made of silicon dioxide, and the gate oxide layer can be realized by a thermal oxidation process; the interlayer dielectric layer 193 may be silicon nitride; the spacer insulating layer 221 may also be silicon dioxide, but is more preferably a high-K dielectric material, such as Al 2 O 3 The method is favorable for further reducing the leakage current of the device and improving the breakdown voltage of the device. In other examples, the material of each structural layer may be selected, for example, the gate conductive layer 192 may be a metal layer or a metal silicide, but is not limited thereto.
Example two
As shown in fig. 3, the present invention further provides a method for manufacturing a super junction MOS device structure, which can be used to manufacture the super junction MOS device structure in the first embodiment, and therefore, the description of the same structure in the first embodiment is also applicable to this embodiment, and for the sake of brevity, no detailed description is given in this embodiment. The preparation method of the super junction MOS device structure at least comprises the following steps:
step S1: providing a first conductive type substrate 11, and forming a first conductive type epitaxial layer 12 on the surface of the first conductive type substrate 11;
step S2: forming a plurality of trenches distributed at intervals in the first conductive type epitaxial layer 12, wherein the plurality of trenches form a plurality of first conductive type pillars 14 at intervals in the first conductive type epitaxial layer 12;
step S3: filling the trenches to form a plurality of second conductive type pillars 13, the second conductive type pillars 13 and the first conductive type pillars 14 forming a super junction structure, the second conductive type being different from the first conductive type;
step S4: sequentially forming a gate oxide layer 191 and a gate conductive layer 192, wherein the gate oxide layer 191 is positioned on the upper surface of the first conductive type column 14, and the gate conductive layer 192 is positioned on the upper surface of the gate oxide layer 191;
step S5: performing ion implantation on the second conductive type column 13 and performing high-temperature drive-in so as to form a second conductive type well region 15 on the upper portion of the second conductive type column 13, where the second conductive type well region 15 extends to the lower surface of the gate oxide 191 to form a trench 31 penetrating through the gate conductive layer 192, and an interlayer dielectric layer 193 is formed on the upper surface and the side wall of the gate conductive layer 192;
step S6: forming a first conductive type source region 16 and a second conductive type well lead-out region 17 in the second conductive type well region 15, wherein the second conductive type well lead-out region 17 and the first conductive type source region 16 are adjacently arranged;
step S7: forming a source metal layer 20, a spacer metal layer 222 and a drain metal layer 21, wherein the source metal layer 20 covers the surface of the second conductive type well lead-out region 17 and the surface of the first conductive type source region 16, the spacer metal layer 222 fills the trench 31 in the gate conductive layer 192, and the drain metal layer 21 is located on the surface of the first conductive type substrate 11 away from the first conductive type epitaxial layer 12.
The conductivity type is determined by doping different types of impurity atoms in a neutral base, for example, a semiconductor substrate of the germanium-silicon type is doped with a group-five element (which can provide electrons) such as nitrogen, phosphorus, arsenic, and the like to form an N-type conductivity; p-type conductivity may be formed by doping group iii elements such as boron, aluminum, etc., to provide holes. As an example, in the present embodiment, an N-type semiconductor substrate, such as a silicon substrate or a germanium substrate doped with a group five element such as nitrogen, phosphorus, arsenic, etc., may be used as the first conductive type substrate 11, and in this case, the second conductive type column 13 is a P-type conductive column, such as polysilicon doped with a group three element such as boron, aluminum, etc.; of course, in another example, a P-type substrate may also be used as the first conductive type substrate 11, and the second conductive type pillar 13 is an N-type pillar, which may be flexibly selected according to different requirements, and is not limited in this embodiment. Of course, in practical applications, an N-type semiconductor substrate, such as an N-type silicon substrate or a germanium substrate, is preferred to form the NMOS transistor because its on-resistance is smaller and the manufacturing process is simpler. The substrate 11 of the first conductivity type is a highly doped substrate, typically with a doping concentration of 10 19 cm -3 The above. The doping concentration of the first conductivity type epitaxial layer 12 is generally lowThe doping concentration in the first conductivity type substrate 11 is, for example, 10 15 ～5*10 16 cm -3 . The thickness of the first conductivity type epitaxial layer 12 determines the breakdown voltage of the device, so that theoretically, the thicker the device is better, but if the thickness is too thick, the device is too large, and in sum, the thickness of the first conductivity type epitaxial layer 12 is preferably 20-60 μm. As an example, the second conductive type pillar 13 has a width of 2 to 6um and a doping concentration of 3 x 10 15 cm -3 . Of course, the above parameters may be set in other ways according to different structural designs, and this embodiment is not limited strictly.
As an example, the method of forming the first conductive type epitaxial layer 12 is preferably vapor deposition, and the doping concentration of the first conductive type epitaxial layer 12 is preferably less than the doping concentration of the first conductive type substrate 11 by adjusting the concentration of impurity atoms doped during the deposition to achieve a desired doping concentration.
As an example, in step S2, the trench may be formed by wet etching or dry etching according to a specific material of the first conductivity type epitaxial layer 12. Of course, as will be appreciated by those skilled in the art, this step typically requires photolithography with a photomask to define the location and shape of the trenches, which are then formed by etching. In this embodiment, the depth of the trench is smaller than the thickness of the first conductivity type epitaxial layer 12, so that there is a space between the trench and the first conductivity type substrate 11, and the first conductivity type epitaxial layer 12 located between the space will be used as a buffer layer between the first conductivity type pillar 14 and the first conductivity type substrate 11 which are formed later. Of course, in another example, if a buffer layer is formed between the first conductive type epitaxial layer 12 and the first conductive type substrate 11, the depth of the trench in this step may be the same as the thickness of the first conductive type epitaxial layer 12. Providing the buffer layer may prevent impurities of the first conductive type substrate 11 from diffusing into the first conductive type column 14 during a subsequent high temperature process.
As an example, the second conductive type pillar 13 may be formed in step S3 by using an epitaxial process, and the resulting structure is shown in fig. 4.
As an example, the method for forming the gate oxide layer 191 in step S4 may be a thermal oxidation method and a vapor deposition method, and the gate oxide layer 191 is preferably silicon dioxide, and is preferably formed by a thermal oxidation method, which facilitates rapid formation of the gate oxide layer 191 with a desired thickness. In order to improve the withstand voltage of the device, the thickness of the gate oxide layer 191 is preferably more than 500 angstroms; the gate conductive layer 192 is preferably polysilicon, and is also preferably formed by epitaxy because polysilicon is more resistant to high temperature and has small interface defects with the gate oxide 191, and furthermore, the work function thereof can be changed by doping impurities of different polarities to lower the threshold voltage of the device. When the gate conductive layer 192 is made of a polysilicon layer, the thickness of the gate conductive layer 192 is preferably 3000 to 5000 angstroms.
Then, step S5 is performed, a second conductive type impurity atom is injected into the second conductive type pillar 13, and high temperature drive-in is performed, for example, annealing is performed at a high temperature of 1000 to 1200 ℃ for 1 to 10 hours (specifically, according to parameters such as doping concentration and depth, and device size), the second conductive type well region 15 formed after ion injection and high temperature drive-in extends to the lower surface of the gate oxide 191, that is, the second conductive type well region 15 is connected to the gate oxide 191, and the obtained structure is as shown in fig. 5. In this process, the gate conductive layer 192 serves as a Mask without using a photomask (Mask), which is advantageous in reducing the manufacturing cost. The trench 31 penetrating through the gate conductive layer 192 may be formed by etching, and then the interlayer dielectric layer 193 may be formed by vapor deposition, where the interlayer dielectric layer 193 is located on the sidewall and the surface of the gate conductive layer 192, and the resulting structure is as shown in fig. 6. The interlayer dielectric layer 193 may be silicon nitride. Of course, in another example, the trench 31 may also penetrate through the gate oxide layer 191 to reach the surface of the first conductive type pillar 14, in which case, the interlayer dielectric layer 193 may be made of a high-K dielectric material, so that the interlayer dielectric layer 193 may be simultaneously formed at the bottom of the trench 31, i.e., the surface of the first conductive type pillar 14, as the required spacer insulating layer 221 during the process of forming the interlayer dielectric layer 193. The subsequent processes are slightly different based on the depth of the trench 31, which will be described later. In this step, a contact hole (not shown) may be formed in the interlayer dielectric layer 193 to electrically lead out the gate conductive layer 192. Of course, the step of forming the contact hole may be formed in a subsequent process as long as it is before the source metal layer 20 is formed. Of course, in other examples, the second conductive type well region 15 may be formed first, and then the gate oxide layer 191 and the interlayer dielectric layer 193 may be formed, which is not limited in this embodiment.
As an example, the first conductivity type source region 16 and the second conductivity type well lead-out region 17 are also formed by ion implantation in step S6, the first conductivity type source region 16 is in contact with the gate oxide layer 191, and a side wall of the first conductivity type source region 16 and a side wall of the second conductivity type well region 15 have a space, which constitutes a channel of the second conductivity type well region 15. The structure obtained by this step is shown in FIG. 7.
As an example, in the step S7, the source metal layer 20, the spacer metal layer 222, and the drain metal layer 21 may be formed by a physical vapor deposition or electroplating process, and the source metal layer 20 is usually also located on the surface of the interlayer dielectric layer 193 to ensure electrical connection of the device. It should be noted that, if the trench 31 formed between the gate conductive layers 192 in the step S4 further penetrates through the gate oxide layer 191, the method further includes, before the step S7, a step of forming a spacer insulating layer 221 in the trench 31, where the spacer insulating layer 221 is located on the surface of the first conductive type pillar 14, and the spacer insulating layer 221 is connected to the gate oxide layer 191, so as to protect the device surface from being contaminated. The thickness of the spacer insulating layer 221 is generally not greater than the thickness of the gate oxide 191, preferably less than the thickness of the gate oxide 191, which is beneficial for improving the reverse recovery characteristics of the device, and the material may be silicon dioxide, but is preferably a high-K dielectric material, and the ratioSuch as Al 2 O 3 The leakage current of the device is reduced, and the breakdown voltage of the device is improved. If the material of the interlayer dielectric layer 193 formed at the bottom of the trench 31 is different from that of the required spacer insulating layer 221, a step of removing the interlayer dielectric layer 193 at the bottom of the trench 31 is further included before forming the spacer insulating layer 221. Of course, in other examples, the spacer insulating layer 221 may also directly utilize the gate oxide layer 191, that is, the trench 31 does not extend into the gate oxide layer 191, and the gate oxide layer 191 at the bottom of the trench 31 serves as the spacer insulating layer 221, which is beneficial to process simplification, or a part of the thickness of the gate oxide layer 191 may be etched away, and the rest part serves as the spacer insulating layer 221. The present embodiment is not strictly limited. Which together with the spacer metal layer 222 constitute a gate spacer 22 separating the gate 19, in particular the gate conductive layer 192 of the gate 19. In another example, the first conductive type substrate 11 may be subjected to back grinding (i.e., the surface on which the drain metal layer 21 is to be formed) before the drain metal layer 21 is formed, so as to further reduce the device size.
As an example, the spacer metal layer 222 and the source metal layer 20 may be formed in the same process, and thus the material of the spacer metal layer 222 and the source metal layer 20 may be the same, such as but not limited to aluminum, and the drain metal layer is preferably but not limited to one or more of nickel, titanium or silver. The spacer metal layer 222 and the source metal layer 20 are preferably connected to each other. After this step is completed, the super junction MOS device structure as shown in fig. 2 can be obtained. The spacer metal layer 222, the spacer insulating layer 221 and the first conductivity type column 14 of the super junction structure form a MIS diode in the longitudinal direction, which helps to improve the performance of the super junction MOS device structure.
As described above, the super junction MOS device structure and the manufacturing method thereof of the present invention have the following beneficial effects: according to the super-junction MOS device, the spacing insulating layer and the spacing Metal layer are introduced into the gate structure of the conventional super-junction MOS device to separate the gate structure, the spacing Metal layer, the spacing insulating layer and the first conductive type column of the super-junction structure form an MIS diode (Metal-Insulator-Semiconductor diode) in the longitudinal direction, and as the switching speed of the MIS diode is in the picosecond magnitude (and the switching speed of the common diode is in the nanosecond magnitude), the reverse recovery charge (Qrr) in the super-junction MOS device can be effectively reduced, the reverse recovery time (Trr) of the super-junction device is shortened, so that the loss in the reverse recovery process of the device can be reduced, the noise interference in the switching process is reduced, the performance of the super-junction device is further improved, and the stability of the device and the system adopting the device is improved. In addition, compared with a Schottky diode, the reverse leakage of the MIS diode is smaller, and the reverse breakdown voltage of the device is further improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A super junction MOS device structure, comprising:
a first conductive type substrate;
the first conductive type epitaxial layer is positioned on the surface of the first conductive type substrate;
the second conductive type columns are distributed in the first conductive type epitaxial layer at intervals so as to form a super junction structure by separating the first conductive type columns among the second conductive type columns, and the second conductive type is different from the first conductive type;
a plurality of second conductivity type well regions located within the first conductivity type epitaxial layer and located on upper surfaces of the second conductivity type pillars;
a first conductivity type source region located in the second conductivity type well region;
a second conductivity type well lead-out region located in the second conductivity type well region and adjacent to the first conductivity type source region;
the grid comprises a grid oxide layer, a grid conducting layer and an interlayer dielectric layer; wherein the gate oxide layer is located on the upper surface of the first conductive type column and part of the upper surface of the second conductive type well region; the grid conducting layer is positioned on the upper surface of the grid oxide layer; the interlayer dielectric layer is positioned on the upper surface and the side wall of the grid conducting layer;
the grid spacing layer is positioned in the grid and comprises a spacing insulating layer and a spacing metal layer, the spacing insulating layer is positioned on the upper surface of the first conductive type column, the spacing metal layer is positioned on the upper surface of the spacing insulating layer, the grid spacing layer spaces the grid conductive layer into at least two parts, and the spacing metal layer, the spacing insulating layer and the first conductive type column of the super junction structure form an MIS diode in the longitudinal direction;
the source metal layer is positioned on the surface of the second conduction type well lead-out region and the surface of the first conduction type source region;
and the drain metal layer is positioned on the surface of the first conduction type substrate far away from the first conduction type epitaxial layer.
2. The superjunction MOS device structure of claim 1, wherein: a space is formed between the lower surface of the second conductive type column and the first conductive type substrate, and a space is formed between the lower surface of the first conductive type source region and the lower surface of the second conductive type well region.
3. The superjunction MOS device structure of claim 1, wherein: the gate oxide layer is connected with the interval insulating layer.
4. The superjunction MOS device structure of claim 1, wherein: the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
5. The superjunction MOS device structure of claim 1, wherein: the width of the spacer metal layer is not greater than the width of the upper surface of the first conductive type pillar.
6. The superjunction MOS device structure of claim 1, wherein: the width of the interval metal layer is 2-3 mu m.
7. The superjunction MOS device structure of claim 1, wherein: the material of the spacer insulating layer comprises a high-K dielectric material.
8. The super-junction MOS device structure of any of claims 1-7, wherein: the doping concentration of the first conduction type substrate is the same as that of the first conduction type source region and is greater than that of the first conduction type epitaxial layer, and the doping concentration of the second conduction type well leading-out region is greater than that of the second conduction type column.
9. A method of manufacturing a super junction MOS device structure according to any of claims 1 to 8, comprising the steps of:
providing a first conductive type substrate, and forming a first conductive type epitaxial layer on the surface of the first conductive type substrate;
forming a plurality of grooves distributed at intervals in the first conductive type epitaxial layer, wherein the grooves form a plurality of first conductive type columns at intervals in the first conductive type epitaxial layer;
filling the trenches to form a plurality of second conductivity type pillars, the second conductivity type pillars and the first conductivity type pillars forming a super junction structure, the second conductivity type being different from the first conductivity type;
sequentially forming a gate oxide layer and a gate conducting layer, wherein the gate oxide layer is positioned on the upper surface of the first conductive type column, and the gate conducting layer is positioned on the upper surface of the gate oxide layer;
performing ion implantation on the second conductive type column and performing high-temperature drive-in to form a second conductive type well region on the upper part of the second conductive type column, wherein the second conductive type well region extends to the lower surface of the gate oxide layer; forming a groove penetrating through the grid conducting layer, and forming an interlayer dielectric layer on the upper surface and the side wall of the grid conducting layer;
forming a first conductive type source region and a second conductive type well lead-out region in the second conductive type well region, wherein the second conductive type well lead-out region and the first conductive type source region are arranged adjacently;
and forming a source metal layer, an interval metal layer and a drain metal layer, wherein the source metal layer covers the surface of the second conductive type well lead-out region and the surface of the first conductive type source region, the interval metal layer fills the groove in the grid conductive layer, and the drain metal layer is positioned on the surface of the first conductive type substrate far away from the first conductive type epitaxial layer.
10. The method of claim 9, wherein: the groove penetrating through the grid conducting layer also extends to the surface of the first conducting type column; the method further includes a step of forming a spacer insulating layer in the trench before forming the spacer metal layer in the trench, the spacer insulating layer being located on a surface of the first conductive type pillar.
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Inventor after: Luo Jiexin Inventor after: Chai Zhan Inventor after: Xu Dapeng Inventor after: Huang Xiaoyan Inventor before: Luo Jiexin Inventor before: Xue Zhongying Inventor before: Chai Zhan Inventor before: Xu Dapeng Inventor before: Huang Xiaoyan |
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| CB03 | Change of inventor or designer information |