CN110176499B - Super junction MOS device structure and preparation method thereof - Google Patents
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention provides a super junction MOS device structure and a preparation method thereof. The device structure includes: a first conductive type substrate; a first conductivity type epitaxial layer; the second conductive type columns are distributed in the first conductive type epitaxial layer at intervals so as to form a super junction structure by separating the first conductive type columns among the second conductive type columns; a plurality of second conductivity type well regions; a first conductive type source region; a second conductivity type well lead-out region; a gate oxide layer; a negative capacitance material layer; a gate conductive layer; an interlayer dielectric layer; the source electrode metal layer is positioned on the surface of the second conduction type well lead-out region and the surface of the first conduction type source region; and the drain metal layer is positioned on the surface of the first conduction type substrate far away from the first conduction type epitaxial layer. The invention can effectively avoid sudden change of the reverse output capacitor (Coss) and the reverse transmission capacitor (Crss) of the super junction MOS device structure in the switching process, avoid the device from generating oscillation, improve the EMI characteristic and improve the stability of the device.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to a super junction MOS device structure and a preparation method thereof.
Background
Since the Super-Junction MOS (SJ-MOS) structure was proposed for the first time in the last 80 years, the Super-Junction MOS device attracts extensive attention in the industry due to its advantages of small on-resistance, fast on-speed, and low switching loss, and its structure is also continuously optimized. In the existing super junction transistor, a doped region composed of a series of P-type and N-type semiconductor thin layers which are alternately arranged is adopted to replace a single lightly doped drift region in a conventional VDMOS (Vertical double-diffused metal oxide semiconductor) device. When the device is in a cut-off state, because depletion region electric fields in the P type and N type layers generate a mutual compensation effect, the doping concentration of the P type and N type layers can be very high, and the breakdown voltage of the device cannot be reduced; this high concentration doping can significantly reduce the on-resistance of the device when it is turned on. Due to the special structure, the performance of the super junction MOS device is superior to that of the traditional LDMOS device.
The super-junction MOS device structure uses a transverse electric field, the middle N + region is completely exhausted at high voltage, the stored charge is very small, Coss (reverse output capacitance) and Crss (reverse transmission capacitance) are very small, and V isDSThe (drain-source voltage) starts to drop very fast. When V isDSWhen the voltage drops to 50V or lower, the widths of the depletion layers of the N + and P regions are reduced until the depletion layers disappear and gradually return to the original high doping state, which means that the stored charges are suddenly increased, and therefore, the capacitance is also suddenly increased. Especially, in the switching process, when the drain voltage is relatively small, the capacitance of the super junction MOS structure changes sharply (corresponding to the dV/dt abrupt change region indicated by the dashed line frame in fig. 1), which easily causes problems such as oscillation and EMI (electromagnetic Interference) of the device, and may also cause device failure in a serious case.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a super junction MOS device structure and a method for manufacturing the same, which are used to solve the problems that the existing super junction MOS device structure is easy to cause device oscillation and electromagnetic interference due to a rapid change in capacitance during a switching process, and even may cause device failure.
To achieve the above and other related objects, the present invention provides a super junction MOS device structure, including:
a first conductive type substrate;
the first conductive type epitaxial layer is positioned on the surface of the first conductive type substrate;
a plurality of second conductive type columns distributed in the first conductive type epitaxial layer at intervals so as to form a super junction structure by separating the first conductive type columns among the second conductive type columns, wherein the second conductive type is different from the first conductive type;
a plurality of second conductivity type well regions located within the first conductivity type epitaxial layer and located on upper surfaces of the second conductivity type pillars;
a first conductivity type source region located in the second conductivity type well region;
a second conductive type well lead-out region which is positioned in the second conductive type well region and is adjacent to the first conductive type source region;
a gate oxide layer on an upper surface of the first conductive type pillar;
the negative capacitance material layer is positioned on the upper surface of the gate oxide layer;
the grid conducting layer is positioned on the surfaces of the grid oxide layer and the negative capacitance material layer;
the interlayer dielectric layer is positioned on the upper surface and the side wall of the grid conducting layer;
the source metal layer is positioned on the surface of the second conduction type well lead-out region and the surface of the first conduction type source region;
and the drain metal layer is positioned on the surface of the first conduction type substrate far away from the first conduction type epitaxial layer.
Optionally, the material of the negative capacitance material layer includes one or more of a layered ferroelectric ceramic material and a relaxor type ferroelectric ceramic material.
Optionally, a space is provided between a lower surface of the second conductive type pillar and the first conductive type substrate, and a space is provided between a lower surface of the first conductive type source region and a lower surface of the second conductive type well region.
Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
Optionally, the super junction MOS device structure further includes a first conductivity type buffer layer located between the first conductivity type substrate and the first conductivity type epitaxial layer, and a doping concentration of the first conductivity type buffer layer is between that of the first conductivity type substrate and that of the first conductivity type epitaxial layer.
Optionally, a width of the layer of negative capacitance material is the same as a width of the first-conductivity-type pillar upper surface.
Optionally, the thickness of the negative capacitance material layer is 30-50 nm.
Optionally, the material of the source metal layer includes aluminum, and the material of the drain metal layer includes one or more of titanium, nickel, and silver.
The invention also provides a preparation method of the super junction MOS device structure, which comprises the following steps:
providing a first conductive type substrate, and forming a first conductive type epitaxial layer on the surface of the first conductive type substrate;
forming a plurality of grooves distributed at intervals in the first conductive type epitaxial layer, wherein the grooves form a plurality of first conductive type columns at intervals in the first conductive type epitaxial layer;
filling the trenches to form a plurality of second conductivity type pillars, the second conductivity type pillars and the first conductivity type pillars forming a super junction structure, the second conductivity type being different from the first conductivity type;
forming a gate oxide layer, a negative capacitance material layer, a gate conducting layer and an interlayer dielectric layer; the gate oxide layer is positioned on the upper surface of the first conductive type column, the negative capacitance material layer is positioned on the upper surface of the gate oxide layer, the gate conducting layer is positioned on the surfaces of the gate oxide layer and the negative capacitance material layer, and the interlayer dielectric layer is positioned on the surface and the side wall of the gate conducting layer;
performing ion implantation on the second conductive type column and performing high-temperature drive-in to form a second conductive type well region on the upper part of the second conductive type column, wherein the second conductive type well region extends to the lower surface of the gate oxide layer;
forming a first conductive type source region and a second conductive type well lead-out region in the second conductive type well region, wherein the second conductive type well lead-out region and the first conductive type source region are arranged adjacently;
and forming a source metal layer and a drain metal layer, wherein the source metal layer covers the surface of the second conductive type well lead-out region and the surface of the first conductive type source region, and the drain metal layer is positioned on the surface of the first conductive type substrate far away from the first conductive type epitaxial layer.
As described above, the super junction MOS device structure and the manufacturing method thereof of the present invention have the following beneficial effects: according to the invention, the negative capacitance material layer is added in the traditional super-junction MOS device structure to adjust the junction capacitance (Cgd) of the super-junction MOS device, so that the sudden change of the reverse output capacitance (Coss) and the reverse transmission capacitance (Crss) of the super-junction MOS device in the switching process can be effectively avoided, the device is prevented from generating vibration, the EMI characteristic of the device is improved, the stability of the device is improved, and the power consumption of the device is reduced.
Drawings
Fig. 1 shows a capacitance characteristic curve of a super junction MOS device structure in the prior art.
Fig. 2 is a schematic structural diagram of a super junction MOS device structure according to a first embodiment of the present invention, and fig. 2 is a schematic structural diagram finally prepared according to a second embodiment of the present invention.
Fig. 3 is a flowchart illustrating a method for manufacturing a super junction MOS device structure according to a second embodiment of the present invention.
Fig. 4 to 7 are schematic structural diagrams showing steps of a second preparation method according to the present invention.
Description of the element reference numerals
11 first conductivity type substrate
12 epitaxial layer of the first conductivity type
13 second conductivity type pillar
14 pillars of the first conductivity type
15 second conductivity type well region
16 source region of the first conductivity type
17 well lead-out region of second conductivity type
18 layer of negative capacitance material
191 gate oxide layer
192 Gate conductive layer
193 interlayer dielectric layer
20 source metal layer
21 drain metal layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2-7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
As shown in fig. 2, the present embodiment provides a super junction MOS device structure, which includes: a first conductivity type substrate 11; a first conductivity type epitaxial layer 12 on a surface of the first conductivity type substrate 11; a plurality of second conductive type pillars 13 spaced apart from each other in the first conductive type epitaxial layer 12, so as to form first conductive type pillars 14 between the second conductive type pillars 13, and the first conductive type pillars 14 and the second conductive type pillars 13 are alternately arranged to form a super junction structure, wherein the second conductive type is different from the first conductive type; a plurality of second conductivity-type well regions 15 located within the first conductivity-type epitaxial layer 12 and on the upper surfaces of the second conductivity-type pillars 13, and the second conductivity-type well regions 15 preferably extend to the upper surfaces of the portions of the first conductivity-type pillars 14, so that the widths of the upper surfaces of the first conductivity-type pillars 14 are smaller than the widths of the lower surfaces thereof; a first conductivity type source region 16 located in the second conductivity type well region 15; a second conductivity type well lead-out region 17 located in the second conductivity type well region 15 and disposed adjacent to the first conductivity type source region 16; a gate oxide layer 191 on the upper surface of said first conductivity type pillars 14 and part of the upper surface of said second conductivity type well region 15, and said gate oxide layer 191 preferably partially contacts said first conductivity type source region 16; a negative capacitance material layer 18 located on the upper surface of the gate oxide 191; a gate conductive layer 192 on the surfaces of the gate oxide layer 191 and the negative capacitance material layer 18; an interlayer dielectric layer 193 on the upper surface and the sidewall of the gate conductive layer 192; a source metal layer 20 located on the surface of the second conductive type well lead-out region 17 and the surface of the first conductive type source region 16, and the source metal layer 20 is usually also located on the surface of the interlayer dielectric layer 193 to ensure electrical connection of the device; and a drain metal layer 21 located on a surface of the first conductive type substrate 11 away from the first conductive type epitaxial layer 12.
According to the invention, the negative capacitance material layer 18 is added in the traditional super-junction MOS device structure to adjust the junction capacitance (Cgd) of the super-junction MOS device, so that the sudden change of the reverse output capacitance (Coss) and the reverse transmission capacitance (Crss) of the super-junction MOS device in the switching process can be effectively avoided, the device is prevented from generating oscillation and the EMI characteristic is improved, the stability of the device is improved, and the power consumption of the device is reduced.
It should be noted that, in the present invention, the first conductivity type epitaxial layer 12 is partitioned into the plurality of first conductivity type pillars 14 by the plurality of second conductivity type pillars 13, and the first conductivity type pillars 14 and the second conductivity type pillars 13 are alternately arranged to form a super junction structure, so that the first conductivity type pillars 14 are substantially a part of the first conductivity type epitaxial layer 12, but for understanding of the super junction structure, separate reference numerals are used in this embodiment for description.
The conductivity type is determined by doping the neutral base with impurity atoms of different types, for example, doping a semiconductor substrate of the germanium-silicon type with a group-five element (which can provide electrons) such as nitrogen, phosphorus, arsenic, etc., can form an N-type conductivityMolding; p-type conductivity may be formed by doping group iii elements such as boron, aluminum, etc., to provide holes. As an example, in the present embodiment, an N-type semiconductor substrate, such as a silicon substrate or a germanium substrate doped with a group five element such as nitrogen, phosphorus, arsenic, etc., may be used as the first conductive type substrate 11, and in this case, the second conductive type column 13 is a P-type conductive column, such as polysilicon doped with a group three element such as boron, aluminum, etc.; of course, in another example, a P-type substrate may also be used as the first conductive type substrate 11, and the second conductive type pillar 13 is an N-type pillar, which may be flexibly selected according to different requirements, and is not limited in this embodiment. Of course, in practical applications, an N-type semiconductor substrate, such as an N-type silicon substrate or a germanium substrate, is preferred to form the NMOS transistor because its on-resistance is smaller and the manufacturing process is simpler. The substrate 11 of the first conductivity type is a highly doped substrate with a doping concentration of typically 1019cm-3The above. The doping concentration of the first conductivity type epitaxial layer 12 is generally lower than the doping concentration of the first conductivity type substrate 11, for example 1015～5*1016cm-3. The thickness of the first conductivity type epitaxial layer 12 determines the breakdown voltage of the device, so that theoretically, the thicker the device is better, but if the thickness is too thick, the device is too bulky, and in sum, the thickness of the first conductivity type epitaxial layer 12 is preferably 20-60 μm. As an example, the second conductive type pillar 13 has a width of 2 to 6um and a doping concentration of 3 x 1015cm-3. Of course, the above parameters may be set in other ways according to different structural designs, and this embodiment is not limited strictly.
In an example, the super junction device structure further includes a first conductivity type buffer layer (not shown) located between the first conductivity type substrate 11 and the first conductivity type epitaxial layer 12, and a doping concentration of the first conductivity type buffer layer may be between doping concentrations of the first conductivity type substrate 11 and the first conductivity type epitaxial layer 12, so that impurity atoms of the first conductivity type substrate 11 may be prevented from diffusing into the first conductivity type epitaxial layer 12 during a high temperature process, and a breakdown voltage of the device may be prevented from being reduced due to an increase in the doping concentration of the first conductivity type epitaxial layer 12 (especially, a region corresponding to the first conductivity type pillar 14).
In another example, there is a space between the lower surface of the second conductive type pillar 13 and the first conductive type substrate 11, and the first conductive type epitaxial layer 12 between the lower surface of the second conductive type pillar 13 and the first conductive type substrate 11 functions as a buffer layer, so that a buffer layer may not be required to be additionally fabricated.
As an example, a lower surface of the first conductivity type source region 16 and a lower surface of the second conductivity type well region 15 have a space therebetween, the space forming a channel of the second conductivity type well region 15.
As an example, the doping concentration of the first conductive-type substrate 11 and the doping concentration of the first conductive-type source region 16 are the same and greater than the doping concentration of the first conductive-type epitaxial layer 12, and the doping concentration of the second conductive-type well lead-out region 17 is greater than the doping concentration of the second conductive-type column 13.
As an example, the source metal layer 20 includes an aluminum layer; the drain metal layer 21 includes one or more of a titanium layer, a nickel layer, and a silver layer.
As an example, the gate conductive layer 192 is preferably a polysilicon layer because polysilicon is more resistant to high temperature and has small interface defects with the gate oxide layer 191, and furthermore, the work function thereof can be changed by doping impurities of different polarities to lower the threshold voltage of the device. When a polysilicon layer is selected as the gate conductive layer 192, the thickness of the gate conductive layer 192 is preferably 3000 to 5000 angstroms; the gate oxide 191 is used for realizing the isolation between the gate conductive layer 192 and the second conductive type well region 15, and in order to ensure the withstand voltage of the gate conductive layer 192, the thickness of the gate oxide 191 is preferably greater than 500 angstroms, and the material thereof is preferably silicon dioxide, and particularly can be realized by a thermal oxidation process; the interlayer dielectric layer 193 may be, but is not limited to, silicon nitride.
The material of the negative capacitance material layer 18 includes, but is not limited to, a layered ferroelectric ceramic material and a relaxationOne or more of the relaxation-type ferroelectric ceramic materials realize the negative capacitance regulation effect by utilizing the hysteresis characteristics of the ferroelectric materials under positive and negative electric fields. Such as lead zirconate titanate (Pb (Zr, Ti) O) piezoelectric ceramics3PZT for short), or a piezoelectric ceramic of the metaniobate series, such as potassium sodium metaniobate (Na)0.5·K0.5·NbO3) And barium strontium metaniobate (Ba)x·Sr1-x·Nb2O5) Etc., or may be (Bi, R) obtained by doping with a rare earth element R (La, Nd, etc.)4TiO12[ BRT for short ] ferroelectric thin films. In this embodiment, as an example, the negative capacitance material layer 18 is made of an HfTaO material, because the inventor finds that, through multiple experiments, the HfTaO material has good charge trapping capability, and the interface bonding property with the gate oxide layer 191 is better, so that the device performance can be significantly improved. The capacitance-saving capacity of the super-junction MOS device is adjusted by utilizing the negative capacitance characteristic of the negative capacitance material layer 18, so that the change of the reverse transmission capacity and the reverse output capacity of the super-junction MOS device is more gradual, the sudden change phenomenon cannot occur, the device shock and the electromagnetic interference caused by the sudden change of the reverse transmission capacity and the reverse output capacity are avoided, the stability of the device is improved, and meanwhile, the power consumption of the device can be effectively reduced.
As an example, the width of the negative capacitance material layer 18 is the same as the width of the upper surface of the first conductive type pillar 14 (i.e., the surface in contact with the first conductive type pillar), which can improve the uniformity of charge distribution and avoid local charge accumulation.
By way of example, the thickness of the negative capacitance material layer 18 is 30-50 nm, and more preferably 45nm, and the negative capacitance material layer 18 at this thickness can play a good role in mitigating capacitance jump without affecting the switching speed of the device. Because if the negative capacitance material layer 18 is too thin, it tends to cause poor thermal stability of itself, deformation during a high temperature process, leakage of electricity, etc., and if it is too thick, it tends to cause hysteresis loss, lowering the switching speed of the device.
In other examples, the material of each structural layer may be selected, for example, the gate conductive layer 192 may be a metal layer or a metal silicide, but is not limited thereto.
Example two
As shown in fig. 3, the present invention further provides a method for manufacturing a super junction MOS device structure, which can be used to manufacture the super junction MOS device structure in the first embodiment, and thus the description of the same structure in the first embodiment is also applicable to this embodiment. The preparation method at least comprises the following steps:
step S1: providing a first conductive type substrate 11, and forming a first conductive type epitaxial layer 12 on the surface of the first conductive type substrate 11;
step S2: forming a plurality of trenches distributed at intervals in the first conductive type epitaxial layer 12, wherein the plurality of trenches form a plurality of first conductive type pillars 14 at intervals in the first conductive type epitaxial layer 12;
step S3: filling the trenches to form a plurality of second conductive type pillars 13, the second conductive type pillars 13 and the first conductive type pillars 14 forming a super junction structure, the second conductive type being different from the first conductive type;
step S4: forming a gate oxide layer 191, a negative capacitance material layer 18, a gate conductive layer 192 and an interlayer dielectric layer 193; the gate oxide layer 191 is positioned on the upper surface of the first conductive type column 14, the negative capacitance material layer 18 is positioned on the upper surface of the gate oxide layer 191, the gate conducting layer 192 is positioned on the surfaces of the gate oxide layer 191 and the negative capacitance material layer 18, and the interlayer dielectric layer 193 is positioned on the surface and the side wall of the gate conducting layer 192;
step S5: performing ion implantation on the second conductive type pillars 13 and performing high-temperature drive-in so as to form second conductive type well regions 15 on the upper portions of the second conductive type pillars 13, where the second conductive type well regions 15 extend to the lower surfaces of the gate oxide layers 191;
step S6: forming a first conductive type source region 16 and a second conductive type well lead-out region 17 in the second conductive type well region 15, wherein the second conductive type well lead-out region 17 and the first conductive type source region 16 are adjacently arranged;
step S7: forming a source metal layer 20 and a drain metal layer 21, wherein the source metal layer 20 covers the surface of the second conductive type well lead-out region 17 and the surface of the first conductive type source region 16, and the drain metal layer 21 is located on the surface of the first conductive type substrate 11 away from the first conductive type epitaxial layer 12.
The conductivity type is determined by doping different types of impurity atoms in a neutral base, for example, a semiconductor substrate of the germanium-silicon type is doped with a group-five element (which can provide electrons) such as nitrogen, phosphorus, arsenic, and the like to form an N-type conductivity; p-type conductivity may be formed by doping group iii elements such as boron, aluminum, etc., to provide holes. As an example, in the present embodiment, an N-type semiconductor substrate, such as a silicon substrate or a germanium substrate doped with a group five element such as nitrogen, phosphorus, arsenic, etc., may be used as the first conductive type substrate 11, and in this case, the second conductive type column 13 is a P-type conductive column, such as polysilicon doped with a group three element such as boron, aluminum, etc.; of course, in another example, a P-type substrate may also be used as the first conductive type substrate 11, and the second conductive type pillar 13 is an N-type pillar, which may be flexibly selected according to different requirements, and is not limited in this embodiment. Of course, in practical applications, an N-type semiconductor substrate, such as an N-type silicon substrate or an NMOS transistor, is preferred because its on-resistance is smaller and the manufacturing process is simpler. The substrate 11 of the first conductivity type is a highly doped substrate with a doping concentration of typically 1019cm-3The above. The doping concentration of the first conductivity type epitaxial layer 12 is generally lower than the doping concentration of the first conductivity type substrate 11, for example 1015～5*1016cm-3. The thickness of the first conductivity type epitaxial layer 12 determines the breakdown voltage of the device, so that theoretically, the thicker the device is better, but if the thickness is too thick, the device is too large, and in sum, the thickness of the first conductivity type epitaxial layer 12 is preferably 20-60 μm. As an example, the second conductive type pillar 13 has a width of 2 to 6um and a doping concentration of 3 x 1015cm-3. Of course, the above parameters may be set in other ways according to different structural designs, and this embodiment is not limited strictly.
As an example, the method of forming the first conductive type epitaxial layer 12 is preferably vapor deposition, and the doping concentration of the first conductive type epitaxial layer 12 is preferably less than the doping concentration of the first conductive type substrate 11 by adjusting the concentration of impurity atoms doped during the deposition to achieve a desired doping concentration.
As an example, in step S2, the trench may be formed by wet etching or dry etching according to a specific material of the first conductivity type epitaxial layer 12. Of course, as will be appreciated by those skilled in the art, this step typically requires photolithography with a photomask to define the location and shape of the trenches, which are then formed by etching. In this embodiment, the depth of the trench is smaller than the thickness of the first conductivity type epitaxial layer 12, so that there is a space between the trench and the first conductivity type substrate 11, and the first conductivity type epitaxial layer 12 located between the space will be used as a buffer layer between the first conductivity type pillar 14 and the first conductivity type substrate 11 which are formed later. Of course, in another example, if a buffer layer is formed between the first conductive type epitaxial layer 12 and the first conductive type substrate 11, the depth of the trench in this step may be the same as the thickness of the first conductive type epitaxial layer 12. Providing the buffer layer may prevent impurities of the first conductive type substrate 11 from diffusing into the first conductive type column 14 during a subsequent high temperature process.
As an example, in the step S3, the second conductive type pillar 13 may also be formed by an epitaxial process, and the resulting structure is shown in fig. 4.
As an example, the method for forming the gate oxide layer 191 in step S4 may be a thermal oxidation method and a vapor deposition method, and the gate oxide layer 191 is preferably silicon dioxide, and is preferably, but not limited to, formed by a thermal oxidation method, which facilitates rapid formation of the gate oxide layer 191 with a desired thickness. In order to improve the withstand voltage of the device, the thickness of the gate oxide layer 191 is preferably more than 500 angstroms; the material of the negative capacitance material layer 18 includes, but is not limited to, one or more of a layered ferroelectric ceramic material and a relaxor type ferroelectric ceramic material, such as lead zirconate titanate (Pb (Z) piezoelectric ceramicr,Ti)O3PZT) or meta-niobate-based piezoelectric ceramics, e.g. potassium sodium meta-niobate (Na)0.5·K0.5·NbO3) And barium strontium metaniobate (Ba)x·Sr1-x·Nb2O5) Or (Bi, R) obtained by doping with a rare earth element R (La, Nd, etc.)4TiO12[ BRT for short ] ferroelectric thin films. In the present embodiment, as an example, the negative capacitance material layer 18 employs an HfTaO material; the method for forming the negative capacitance material layer 18 is preferably, but not limited to, a chemical vapor deposition method, because the material formed by vapor deposition is more dense, thereby the thermal stability of the negative capacitance material layer 18 can be improved, and simultaneously the combination of the negative capacitance material layer 18 and the gate oxide layer 191 is more compact, the interface defects are reduced, and the migration rate of carriers is improved; the gate conductive layer 192 is preferably, but not limited to, polysilicon, and is also preferably formed by epitaxy because polysilicon is more resistant to high temperature and has small interface defects with the gate oxide layer 191, and furthermore, the work function thereof can be changed by doping impurities of different polarities to lower the threshold voltage of the device. When a polysilicon layer is selected as the gate conductive layer 192, the thickness of the gate conductive layer 192 is preferably 3000 to 5000 angstroms; the material of the interlayer dielectric layer 193 is preferably silicon nitride, and the method for forming the interlayer dielectric layer 193 is preferably but not limited to chemical vapor deposition. The resulting structure after this step is shown in fig. 5. After the interlayer dielectric layer 193 is formed, a contact hole (not shown) may be formed in the interlayer dielectric layer 193 to facilitate subsequent electrical leading-out of the gate conductive layer 192. Of course, the step of forming the contact hole may be formed in a subsequent process as long as it is before the source metal layer 20 is formed. Of course, in other examples, the second conductive type well region 15 may be formed first, and then the gate oxide layer 191 and the interlayer dielectric layer 193 may be formed, which is not limited in this embodiment.
Then, step S5 is performed to implant ions into the second conductive type pillar 13 and perform high temperature drive-in so as to form a second conductive type well region 15 on the upper portion of the second conductive type pillar 13; the high-temperature drive-in process can be annealing at 1000-1200 ℃ for 1-10 hours (specifically determined according to parameters such as doping concentration, depth and device size). The second conductive type well region 15 formed after ion implantation and high temperature well driving extends to the lower surface of the gate oxide 191, that is, the second conductive type well region 15 is connected to the gate oxide 191, and the obtained structure is as shown in fig. 6. In this process, the gate oxide 191, the gate conductive layer 192 and the interlayer dielectric layer 193 together function as a Mask without using a photomask (Mask), which is beneficial to reducing the production cost.
As an example, the first conductivity type source region 16 and the second conductivity type well lead-out region 17 are also formed by ion implantation in step S6, the first conductivity type source region 16 is in contact with the gate oxide layer 191, and a side wall of the first conductivity type source region 16 and a side wall of the second conductivity type well region 15 have a space, which constitutes a channel of the second conductivity type well region 15. The structure obtained by this step is shown in FIG. 7.
As an example, the source metal layer 20 and the drain metal layer 21 may be formed in step S7 by, but not limited to, a physical vapor deposition or an electroplating process, and the source metal layer 20 is usually also located on the surface of the interlayer dielectric layer 193 to ensure the electrical connection of the device. The material of the source metal layer 20 includes, but is not limited to, aluminum, and the material of the drain metal layer 21 includes, but is not limited to, one or more of nickel, titanium, or silver. In another example, the first conductive type substrate 11 may be subjected to back grinding (i.e., the surface on which the drain metal layer 21 is to be formed) before the drain metal layer 21 is formed, so as to further reduce the device size. After this step is completed, the super junction MOS device structure as shown in fig. 2 can be obtained.
As described above, the present invention provides a super junction MOS device structure and a method for manufacturing the same, the super junction MOS device structure including: a first conductive type substrate; the first conductive type epitaxial layer is positioned on the surface of the first conductive type substrate; a plurality of second conductive type columns distributed in the first conductive type epitaxial layer at intervals so as to form first conductive type columns among the second conductive type columns and form a super junction structure by the alternating arrangement of the first conductive type columns and the second conductive type columns, wherein the second conductive type is different from the first conductive type; a plurality of second conductivity type well regions located within the first conductivity type epitaxial layer and located on upper surfaces of the second conductivity type pillars; a first conductivity type source region located in the second conductivity type well region; a second conductivity type well lead-out region located in the second conductivity type well region; a gate oxide layer located on the upper surface of the first conductive type pillar and a part of the upper surface of the second conductive type well region; the negative capacitance material layer is positioned on the upper surface of the gate oxide layer; the grid conducting layer is positioned on the surfaces of the grid oxide layer and the negative capacitance material layer; the interlayer dielectric layer is positioned on the upper surface and the side wall of the grid conducting layer; the source metal layer is positioned on the surface of the second conduction type well lead-out region and the surface of the first conduction type source region; and the drain metal layer is positioned on the surface of the first conduction type substrate far away from the first conduction type epitaxial layer. The invention can effectively avoid sudden change of the reverse output capacitance (Coss) and the reverse transmission capacitance (Crss) of the super junction MOS device in the switching process, avoid the device from generating oscillation, improve the EMI characteristic, improve the stability of the device and simultaneously contribute to reducing the power consumption of the device. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (10)
1. A super junction MOS device structure, comprising:
a first conductive type substrate;
the first conductive type epitaxial layer is positioned on the surface of the first conductive type substrate;
a plurality of second conductive type columns distributed in the first conductive type epitaxial layer at intervals so as to form a super junction structure by separating the first conductive type columns among the second conductive type columns, wherein the second conductive type is different from the first conductive type;
a plurality of second conductivity type well regions located within the first conductivity type epitaxial layer and located on upper surfaces of the second conductivity type pillars;
a first conductivity type source region located in the second conductivity type well region;
a second conductive type well lead-out region which is positioned in the second conductive type well region and is adjacent to the first conductive type source region;
a gate oxide layer on an upper surface of the first conductive type pillar;
the negative capacitance material layer is positioned on the upper surface of the gate oxide layer;
the grid conducting layer is positioned on the surfaces of the grid oxide layer and the negative capacitance material layer;
the interlayer dielectric layer is positioned on the upper surface and the side wall of the grid conducting layer;
the source metal layer is positioned on the surface of the second conduction type well lead-out region and the surface of the first conduction type source region;
and the drain metal layer is positioned on the surface of the first conduction type substrate far away from the first conduction type epitaxial layer.
2. The superjunction MOS device structure of claim 1, wherein: the material of the negative capacitance material layer comprises one or more of a layered ferroelectric ceramic material and a relaxation type ferroelectric ceramic material.
3. The superjunction MOS device structure of claim 1, wherein: a space is formed between the lower surface of the second conductive type column and the first conductive type substrate, and a space is formed between the lower surface of the first conductive type source region and the lower surface of the second conductive type well region.
4. The superjunction MOS device structure of claim 1, wherein: the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
5. The superjunction MOS device structure of claim 1, wherein: the super junction MOS device structure further comprises a first conduction type buffer layer located between the first conduction type substrate and the first conduction type epitaxial layer, and the doping concentration of the first conduction type buffer layer is between the doping concentrations of the first conduction type substrate and the first conduction type epitaxial layer.
6. The superjunction MOS device structure of claim 1, wherein: the negative capacitance material layer has a width identical to a width of the first conductive-type pillar upper surface.
7. The superjunction MOS device structure of claim 1, wherein: the thickness of the negative capacitance material layer is 30-50 nm.
8. The superjunction MOS device structure of claim 1, wherein: the material of the source metal layer comprises aluminum, and the material of the drain metal layer comprises one or more of titanium, nickel and silver.
9. The superjunction MOS device structure of any of claims 1-8, wherein: the doping concentration of the first conduction type substrate is the same as that of the first conduction type source region and is greater than that of the first conduction type epitaxial layer, and the doping concentration of the second conduction type well leading-out region is greater than that of the second conduction type column.
10. A method for preparing a super junction MOS device structure is characterized by comprising the following steps:
providing a first conductive type substrate, and forming a first conductive type epitaxial layer on the surface of the first conductive type substrate;
forming a plurality of grooves distributed at intervals in the first conductive type epitaxial layer, wherein the grooves form a plurality of first conductive type columns at intervals in the first conductive type epitaxial layer;
filling the trenches to form a plurality of second conductivity type pillars, the second conductivity type pillars and the first conductivity type pillars forming a super junction structure, the second conductivity type being different from the first conductivity type;
forming a gate oxide layer, a negative capacitance material layer, a gate conducting layer and an interlayer dielectric layer; the gate oxide layer is positioned on the upper surface of the first conductive type column, the negative capacitance material layer is positioned on the upper surface of the gate oxide layer, the gate conducting layer is positioned on the surfaces of the gate oxide layer and the negative capacitance material layer, and the interlayer dielectric layer is positioned on the surface and the side wall of the gate conducting layer;
performing ion implantation on the second conductive type column and performing high-temperature drive-in to form a second conductive type well region on the upper part of the second conductive type column, wherein the second conductive type well region extends to the lower surface of the gate oxide layer;
forming a first conductive type source region and a second conductive type well lead-out region in the second conductive type well region, wherein the second conductive type well lead-out region and the first conductive type source region are arranged adjacently;
and forming a source metal layer and a drain metal layer, wherein the source metal layer covers the surface of the second conductive type well lead-out region and the surface of the first conductive type source region, and the drain metal layer is positioned on the surface of the first conductive type substrate far away from the first conductive type epitaxial layer.
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Denomination of invention: Structure and fabrication methods of super junction MOS devices Effective date of registration: 20231228 Granted publication date: 20220624 Pledgee: Wuding Road Sub branch of Bank of Shanghai Co.,Ltd. Pledgor: Shanghai Gongcheng Semiconductor Technology Co.,Ltd. Registration number: Y2023980075345 |