CN114823872B - Full-isolation substrate voltage-resistant power semiconductor device and manufacturing method thereof - Google Patents
Full-isolation substrate voltage-resistant power semiconductor device and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims description 19
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
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- 238000001259 photo etching Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims 1
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- 238000010586 diagram Methods 0.000 description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66409—Unipolar field-effect transistors
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Abstract
The invention provides a full-isolation substrate withstand voltage power semiconductor device and a manufacturing method thereof, wherein the full-isolation substrate withstand voltage power semiconductor device comprises a first conductive type substrate, a first conductive type well region, a first conductive type heavily doped region, a second conductive type drift region, a second conductive type well region, a second conductive type source end heavily doped emission region, a second conductive type drain end heavily doped current collection region, a second conductive type doped island, a longitudinal dielectric oxide layer and a longitudinal polysilicon electrode which form a longitudinal floating field plate are distributed in the whole second conductive type drift region, the longitudinal polysilicon electrode penetrates through a buried oxide layer and penetrates into the second conductive type doped island, and the full-isolation substrate withstand voltage power semiconductor device further comprises a dielectric oxide layer to form a field oxide layer and a gate oxide layer, the dielectric oxide layer forms a buried oxide layer, a second conductive type polysilicon gate electrode, a longitudinal field plate metal, a source end metal and a drain end metal. In the off state, the vertical electrode penetrates into the second conductive type doped island, so that the transverse high voltage is introduced into the reverse PN junction of the substrate, the substrate participates in voltage resistance, and the voltage resistance of the device is improved.
Description
Technical Field
The invention belongs to the field of power semiconductors, and mainly provides a full-isolation substrate voltage-resistant power semiconductor device and a manufacturing method thereof.
Background
The power semiconductor device has the characteristics of high input impedance, high switching speed, low loss, wide safe working area and the like, and is widely applied to various aspects of computer and peripheral equipment, consumer electronics, network communication, electronic special equipment, automobile electronics, instruments and meters, LED display screens, electronic illumination and the like. The easy-to-integrate characteristic of the transverse power device enables the transverse power device to be widely applied to integrated circuits, and problems of leakage current, parasitic PN junction capacitance formed by an isolation well, latch-up effect and the like exist in the integrated circuits on a bulk silicon material, so that the reliability of the circuit is negatively affected; on the other hand, the integrated circuit on the SOI material can effectively avoid the problems, but the characteristic that the SOI isolates the pressure-resistant layer from the substrate in turn limits the pressure-resistant capability of the device.
Disclosure of Invention
In view of the above problems, the present invention provides a fully isolated substrate voltage-resistant power semiconductor device and a method for manufacturing the same, in which an HOF shim voltage-resistant layer is introduced into a drift region, and a vertical trench introduced into the HOF voltage-resistant layer can couple a drain-to-source voltage, and the substrate is made to participate in voltage resistance by penetrating a trench electrode in the HOF voltage-resistant layer into the substrate. Therefore, the invention can realize full isolation by using the thin buried oxide layer SOI and simultaneously enable the substrate to participate in pressure resistance to realize high pressure resistance.
The technical scheme of the invention is as follows:
a fully isolated substrate voltage tolerant power semiconductor device comprising:
the first conductivity type semiconductor substrate 11, the first conductivity type well region 12, the first conductivity type heavily doped emitter region 13, the second conductivity type drift region 21, the second conductivity type well region 22, the second conductivity type heavily doped emitter region 23, the second conductivity type heavily doped collector region 24, the second conductivity type doped island 25, the longitudinal dielectric oxide layer 31, the control gate dielectric oxide layer 32, the field dielectric oxide layer 33, the buried oxide layer 34, the longitudinal polysilicon electrode 41, the control gate polysilicon electrode 42, the longitudinal field plate contact metal electrode 51, the source metal 52, the drain metal 53;
wherein the in-body buried oxide layer 34 is located above the first conductivity type semiconductor substrate 11, the second conductivity type drift region 21 is located above the in-body buried oxide layer 34, the first conductivity type heavily doped emitter region 13 and the second conductivity type heavily doped emitter region 23 are located in the first conductivity type well region 12, the second conductivity type well region 22 is located on the right side of the second conductivity type drift region 21, the first conductivity type well region 12 is located on the left side of the second conductivity type drift region 21, and the second conductivity type heavily doped collector region 24 is located in the second conductivity type well region 22; the control gate dielectric oxide layer 32 is located above the first conductivity type well region 12, and has a left end in contact with the second conductivity type heavily doped emitter region 23 and a right end in contact with the second conductivity type drift region 21; the field dielectric oxide layer 33 is located on the upper surface of the second conductivity type drift region 21 between the control gate dielectric oxide layer 32 and the second conductivity type heavily doped collector region 24; the control gate polysilicon electrode 42 covers the upper surface of the control gate dielectric oxide layer 32 and extends partially to the upper surface of the field dielectric oxide layer 33;
the vertical dielectric oxide layer 31 and the vertical polysilicon electrode 41 form a vertical floating field plate, the vertical direction is perpendicular to the direction of the surface of the device, each second conductive type doped island 25 is respectively located in the substrate below each vertical field plate, the vertical floating field plates are staggered in the source-drain direction and periodically distributed in the whole second conductive type drift region 21 to form a voltage-resistant layer with a plurality of equipotential floating grooves, the equipotential floating grooves are connected with the in-vivo buried oxide layer 34, and the vertical polysilicon electrode 41 penetrates through the in-vivo buried oxide layer 34 and goes deep into the second conductive type doped island 25.
Preferably, the longitudinal and lateral pitches of adjacent longitudinal floating field plates distributed throughout the second conductivity type drift region 21 are equal or unequal or graded; and the cross-sectional shape of the longitudinal floating field plates is rectangular, or circular, or elliptical, or hexagonal.
Preferably, the number of the longitudinal floating field plates can be 1 to more.
Preferably, the device is an IGBT or PMOS device.
Preferably, the second conductivity type doped islands 25 or the entire continuous second conductivity type doped layer underlie the buried oxide layer 34; or second conductivity type doped strips from source to drain, respectively, under each row of vertical floating field plates.
The invention also provides a full-isolation substrate voltage-resistant power semiconductor device which does not comprise the second conductive type doped island 25.
The invention also provides a manufacturing method of the full-isolation substrate voltage-resistant power semiconductor device, which comprises the following steps:
step 1: selecting an SOI epitaxial wafer;
step 2: injecting a push junction into the SOI epitaxial wafer to obtain a second conductivity type drift region 21;
step 3: forming a deep groove by photoetching and etching through the buried oxide layer;
step 4: implanting the substrate at the bottom of the deep trench to obtain a doped island 25 of the second conductivity type;
step 5: forming a longitudinal dielectric oxide layer 31 on the groove wall;
step 6: digging through the bottom dielectric oxide layer by photolithography and etching, and penetrating into the second conductivity type doped islands 25;
step 7: depositing polycrystal into the deep groove and etching to the silicon plane
Step 8: forming a second conductive type well region 22 by implanting a second conductive type impurity with high energy ions and pushing a junction;
step 9: forming a control gate dielectric oxide layer 32 by thermal oxidation, and forming a field dielectric oxide layer 33 by deposition and etching;
step 10: forming a first conductivity type well region 12 by ion implanting a first conductivity type impurity and junction pushing;
step 11: depositing and etching polysilicon to form a control gate polysilicon electrode 42;
step 12: the implantation activation heavy doping forms a first conductive type heavy doping emitter region 13, a second conductive type source end heavy doping region 23 and a second conductive type heavy doping collector region 24;
preferably, the method is applied to SiC and GaN wide bandgap semiconductors.
Preferably, all dielectric oxide layers are formed by thermal growth, or by deposition and etching.
Preferably, the second conductivity type drift region 21 formed by implantation and junction pushing in step 2 is obtained by epitaxial method; and/or the first conductivity type well region 12 and the second conductivity type well region 22 obtained by implantation and junction pushing in step 8 and step 10 are formed by implantation and activation of a plurality of different energies.
The beneficial effects of the invention are as follows: the vertical floating field plate structure formed by the vertical dielectric oxide layer 31 and the vertical polysilicon electrode 41 added in the second conductivity type drift region 21 can realize the participation of the substrate of the SOI lateral device in the withstand voltage by the mode that the vertical polysilicon electrode penetrates into the substrate. The vertical floating field plate structure can automatically couple the electric potential from drain to source, and the electric potential is introduced into the substrate through the vertical polysilicon electrode, so that the substrate voltage resistance is realized, and meanwhile, the full isolation characteristic of the SOI is maintained; because the oxygen buried layer in the structure does not participate in pressure resistance, the in-vivo oxygen buried layer 34 can be as thin as 0.2 mu m, thereby improving the heat dissipation problem of the traditional fully-isolated SOI device; meanwhile, the self-adaptive MIS depletion mechanism is introduced into the vertical floating field plate, so that high-concentration doping in the depletion drift region can be assisted, the on-state current of the device is improved, and the specific on-resistance is reduced. The invention relates to a full-isolation substrate participation voltage-resistant device with mass production capacity.
Drawings
Fig. 1 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 1;
fig. 2 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 2;
fig. 3 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 3;
fig. 4 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 4;
fig. 5 is a schematic diagram of the structure of a fully isolated substrate voltage-resistant power semiconductor device according to embodiment 5;
fig. 6 is a schematic diagram of the structure of a fully isolated substrate voltage-resistant power semiconductor device according to embodiment 6;
fig. 7 is a schematic diagram of the structure of a fully isolated substrate voltage-resistant power semiconductor device according to embodiment 7;
fig. 8 is a schematic diagram of the structure of a fully isolated substrate voltage-resistant power semiconductor device according to embodiment 8;
fig. 9 is a schematic diagram of the structure of a fully isolated substrate voltage-resistant power semiconductor device according to embodiment 9;
fig. 10 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 10;
FIGS. 11 (a) -11 (l) are schematic process flow diagrams of the device of example 1.
11 is a first conductivity type semiconductor substrate, 12 is a first conductivity type well region, 13 is a first conductivity type heavily doped emitter region, 14 is a first conductivity type doped layer, 21 is a second conductivity type drift region, 22 is a second conductivity type well region, 23 is a second conductivity type heavily doped emitter region, 24 is a second conductivity type heavily doped collector region, 25 is a second conductivity type doped island, 31 is a longitudinal dielectric oxide layer, 32 is a control gate dielectric oxide layer, 33 is a field dielectric oxide layer, 34 is an in-body buried oxide layer, 41 is a longitudinal polysilicon electrode, 42 is a control gate polysilicon electrode, 51 is a longitudinal field plate contact metal electrode, 52 is a source metal, and 53 is a drain metal.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1
The embodiment 1 of a full-isolation substrate voltage-resistant power semiconductor device, as shown in fig. 1, specifically includes:
the first conductivity type semiconductor substrate 11, the first conductivity type well region 12, the first conductivity type heavily doped emitter region 13, the second conductivity type drift region 21, the second conductivity type well region 22, the second conductivity type heavily doped emitter region 23, the second conductivity type heavily doped collector region 24, the second conductivity type doped island 25, the longitudinal dielectric oxide layer 31, the control gate dielectric oxide layer 32, the field dielectric oxide layer 33, the buried oxide layer 34, the longitudinal polysilicon electrode 41, the control gate polysilicon electrode 42, the longitudinal field plate contact metal electrode 51, the source metal 52, the drain metal 53;
wherein the in-body buried oxide layer 34 is located above the first conductivity type semiconductor substrate 11, the second conductivity type drift region 21 is located above the in-body buried oxide layer 34, the first conductivity type heavily doped emitter region 13 and the second conductivity type heavily doped emitter region 23 are located in the first conductivity type well region 12, the second conductivity type well region 22 is located on the right side of the second conductivity type drift region 21, the first conductivity type well region 12 is located on the left side of the second conductivity type drift region 21, and the second conductivity type heavily doped collector region 24 is located in the second conductivity type well region 22; the control gate dielectric oxide layer 32 is located above the first conductivity type well region 12, and has a left end in contact with the second conductivity type heavily doped emitter region 23 and a right end in contact with the second conductivity type drift region 21; the field dielectric oxide layer 33 is located on the upper surface of the second conductivity type drift region 21 between the control gate dielectric oxide layer 32 and the second conductivity type heavily doped collector region 24; the control gate polysilicon electrode 42 covers the upper surface of the control gate dielectric oxide layer 32 and extends partially to the upper surface of the field dielectric oxide layer 33;
the vertical dielectric oxide layer 31 and the vertical polysilicon electrode 41 form a vertical floating field plate, the vertical direction is perpendicular to the direction of the surface of the device, each second conductive type doped island 25 is respectively located in the substrate below each vertical field plate, the vertical floating field plates are staggered in the source-drain direction and periodically distributed in the whole second conductive type drift region 21 to form a voltage-resistant layer with a plurality of equipotential floating grooves, the equipotential floating grooves are connected with the in-vivo buried oxide layer 34, and the vertical polysilicon electrode 41 penetrates through the in-vivo buried oxide layer 34 and goes deep into the second conductive type doped island 25.
The longitudinal spacing and the lateral spacing of adjacent longitudinal floating field plates distributed throughout the second conductivity type drift region 21 are equal or unequal or graded; and the cross-sectional shape of the longitudinal floating field plates is rectangular, or circular, or elliptical, or hexagonal.
The number of the longitudinal floating field plates can be 1 to more.
The device may also be an IGBT or PMOS device.
The basic working principle is as follows: the vertical floating field plate structure formed by the vertical dielectric oxide layer 31 and the vertical polysilicon electrode 41 added in the second conductivity type drift region 21 can realize the participation of the substrate of the SOI lateral device in the withstand voltage by the mode that the vertical polysilicon electrode penetrates into the substrate. The vertical floating field plate structure can automatically couple the electric potential from drain to source, and the electric potential is introduced into the substrate through the vertical polysilicon electrode, so that the substrate voltage resistance is realized, and meanwhile, the full isolation characteristic of the SOI is maintained; because the oxygen buried layer in the structure does not participate in pressure resistance, the in-vivo oxygen buried layer 34 can be as thin as 0.2 mu m, thereby improving the heat dissipation problem of the traditional fully-isolated SOI device; meanwhile, the self-adaptive MIS depletion mechanism is introduced into the vertical floating field plate, so that high-concentration doping in the depletion drift region can be assisted, the on-state current of the device is improved, and the specific on-resistance is reduced.
As shown in fig. 11 (a) to 11 (l), the present embodiment also provides a method for manufacturing a full-isolation substrate voltage-resistant power semiconductor device, including the steps of:
step 1: selecting an SOI epitaxial wafer;
step 2: injecting a push junction into the SOI epitaxial wafer to obtain a second conductivity type drift region 21;
step 3: forming a deep groove by photoetching and etching through the buried oxide layer;
step 4: implanting the substrate at the bottom of the deep trench to obtain a doped island 25 of the second conductivity type;
step 5: forming a longitudinal dielectric oxide layer 31 on the groove wall;
step 6: digging through the bottom dielectric oxide layer by photolithography and etching, and penetrating into the second conductivity type doped islands 25;
step 7: depositing polycrystal into the deep groove and etching to the silicon plane
Step 8: forming a second conductive type well region 22 by implanting a second conductive type impurity with high energy ions and pushing a junction;
step 9: forming a control gate dielectric oxide layer 32 by thermal oxidation, and forming a field dielectric oxide layer 33 by deposition and etching;
step 10: forming a first conductivity type well region 12 by ion implanting a first conductivity type impurity and junction pushing;
step 11: depositing and etching polysilicon to form a control gate polysilicon electrode 42;
step 12: the implantation activation heavy doping forms a first conductive type heavy doping emitter region 13, a second conductive type source end heavy doping region 23 and a second conductive type heavy doping collector region 24;
preferably, the process is applicable to wide bandgap semiconductors such as SiC and GaN and other types of semiconductors.
Preferably, all dielectric oxide layers are formed by thermal growth, or by deposition and etching.
Preferably, the second conductivity type drift region 21 formed by implantation and junction pushing in step 2 may also be obtained by epitaxial method; and/or the first conductivity type well region 12 and the second conductivity type well region 22 obtained by implantation and junction pushing in step 8 and step 10 are formed by implantation and activation of a plurality of different energies.
The first conductivity type is P-type and the second conductivity type is N-type, or vice versa.
The doping concentration of heavy doping is more than 1E19cm -3 。
Example 2
Fig. 2 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 2. This example differs from example 1 in that a longitudinal field plate in the drift region is introduced into the drain as a drain longitudinal field plate, the polysilicon electrode in the longitudinal field plate being connected to the drain electrode metal down into the second conductivity type doped island 25 in the substrate; this structure is capable of introducing a high potential at the drain terminal directly into the substrate, causing continuous depletion from the drain to the source substrate, and its operation principle is the same as that of example 1.
Example 3
Fig. 3 is a schematic diagram of a full-isolation substrate voltage-withstanding power semiconductor device in embodiment 3. The difference between this example and example 1 is that the longitudinal field plate is grooved through the buried oxide layer deep into the substrate, and the longitudinal field plate is used to assist in depleting the substrate, the working principle of which is the same as that of example 1.
Example 4
Fig. 4 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 4. The present example differs from embodiment 1 in that the present structure is an IGBT, i.e. the heavily doped region 23 of the second conductivity type in the original embodiment 1 is the heavily doped emitter region 13 of the first conductivity type in the present example, while there is an in-vivo buried oxide layer 34 outside the source end, which is homogenous with the drift region longitudinal field plate. On the basis of the original working principle, the on-state conductivity modulation effect exists in the on-state process, and the on-state specific on-resistance can be greatly reduced.
Example 5
Fig. 5 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 5. This example differs from embodiment 1 in that a first conductivity type doped layer 14 is introduced at the device surface. The structure introduces double charge self-balancing, the longitudinal field plate electrode high potential auxiliary depletion P type layer and the low potential auxiliary depletion N type layer, PN is mutually depleted, the doping amount of the drift region of the device can be greatly increased, and the on-state ratio on-resistance is reduced; meanwhile, the multiple depletion function ensures continuous depletion and realizes surface electric field clamping. In the process, the first conductive type doped layer 14 and the first conductive type well region 12 are formed by adopting the same plate by utilizing the blocking effect of the field oxide layer and high-energy injection, and no extra plate is needed. The principle of operation is the same as in example 1.
Example 6
Fig. 6 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 6. The difference between this example and embodiment 1 is that the first conductivity type doped layer 14 is introduced into the device body, and this example can further increase the doping amount of the drift region of the device on the basis of embodiment 5, and reduce the on-state ratio on-resistance of the device. The principle of operation is the same as in example 1.
Example 7
Fig. 7 is a schematic diagram of a structure of a fully isolated substrate voltage-resistant power semiconductor device according to embodiment 7. The difference between this example and example 1 is that after the buried oxide layer is etched through, the substrate is not etched further, and the vertical field plate polysilicon electrode in the drift region does not penetrate into the substrate, but is in contact with the doped islands of the second conductivity type in the substrate. The process is one step less substrate etching. The principle of operation is the same as in example 1.
Example 8
Fig. 8 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 8. The present example differs from embodiment 1 in that the substrate does not have the second conductivity type doped islands 25. The process is carried out after grooving, and the substrate is implanted at one step. The principle of operation is the same as in example 1.
Example 9
Fig. 9 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 9. The present example differs from embodiment 1 in that the second conductivity type doped island 25 is an entire continuous second conductivity type doped layer, located under the in-vivo buried oxide layer 34. The principle of operation is the same as in example 1.
Example 10
Fig. 10 is a schematic diagram of a structure of a full-isolation substrate voltage-resistant power semiconductor device in embodiment 10. The present example differs from embodiment 1 in that the second conductivity type doped islands 25 are second conductivity type doped stripes from source to drain, respectively, located under each row of vertical floating field plates. The principle of operation is the same as in example 1.
Claims (10)
1. The utility model provides a full isolation substrate withstand voltage power semiconductor device which characterized in that includes:
a first conductivity type semiconductor substrate (11), a first conductivity type well region (12), a first conductivity type heavily doped emitter region (13), a second conductivity type drift region (21), a second conductivity type well region (22), a second conductivity type heavily doped emitter region (23), a second conductivity type heavily doped collector region (24), a second conductivity type doped island (25), a longitudinal dielectric oxide layer (31), a control gate dielectric oxide layer (32), a field dielectric oxide layer (33), a buried oxide layer (34), a longitudinal polysilicon electrode (41), a control gate polysilicon electrode (42), a longitudinal field plate contact metal electrode (51), a source metal (52), a drain metal (53);
wherein the in-vivo buried oxide layer (34) is located above the first conductivity type semiconductor substrate (11), the second conductivity type drift region (21) is located above the in-vivo buried oxide layer (34), the first conductivity type heavily doped emitter region (13) and the second conductivity type heavily doped emitter region (23) are located in the first conductivity type well region (12), the second conductivity type well region (22) is located on the right side of the second conductivity type drift region (21), the first conductivity type well region (12) is located on the left side of the second conductivity type drift region (21), and the second conductivity type heavily doped collector region (24) is located in the second conductivity type well region (22); the control gate dielectric oxide layer (32) is positioned above the first conductive type well region (12), the left end of the control gate dielectric oxide layer is contacted with the second conductive type heavily doped emitter region (23), and the right end of the control gate dielectric oxide layer is contacted with the second conductive type drift region (21); the field dielectric oxide layer (33) is positioned on the upper surface of the second conductivity type drift region (21) between the control gate dielectric oxide layer (32) and the second conductivity type heavily doped collector region (24); the control gate polysilicon electrode (42) covers the upper surface of the control gate dielectric oxide layer (32) and extends to the upper surface of the field dielectric oxide layer (33);
the vertical dielectric oxide layer (31) and the vertical polysilicon electrode (41) form a vertical floating field plate, the vertical direction is perpendicular to the surface of the device, each second conductive type doped island (25) is respectively positioned in the substrate below each vertical field plate, the vertical floating field plates are staggered in the source-drain direction and periodically distributed in the whole second conductive type drift region (21) to form a pressure-resistant layer with a plurality of equipotential floating grooves, the equipotential floating grooves are connected with the internal buried oxide layer (34), and the vertical polysilicon electrode (41) penetrates through the internal buried oxide layer (34) to enter the second conductive type doped islands (25).
2. The fully isolated substrate voltage-resistant power semiconductor device of claim 1, wherein: the longitudinal spacing and the transverse spacing of adjacent longitudinal floating field plates distributed in the whole second conductivity type drift region (21) are equal or unequal or gradual; and the cross-sectional shape of the longitudinal floating field plates is rectangular, or circular, or elliptical, or hexagonal.
3. The fully isolated substrate voltage-resistant power semiconductor device of claim 1, wherein: the number of the longitudinal floating field plates is 1 to more.
4. The fully isolated substrate voltage-resistant power semiconductor device of claim 1, wherein: the device is an IGBT or PMOS device.
5. The fully isolated substrate voltage-resistant power semiconductor device of claim 1, wherein: the second conductivity type doped island (25) or the whole continuous second conductivity type doped layer is positioned below the buried oxide layer (34); or second conductivity type doped strips from source to drain, respectively, under each row of vertical floating field plates.
6. A full-isolation substrate voltage-resistant power semiconductor device is characterized in that: a device as claimed in any one of claims 1 to 5, wherein the doped islands (25) of the second conductivity type are removed.
7. The method for manufacturing the full-isolation substrate voltage-resistant power semiconductor device as claimed in claim 1, characterized by comprising the steps of:
step 1: selecting an SOI epitaxial wafer;
step 2: injecting a push junction into the SOI epitaxial wafer to obtain a second conduction type drift region (21);
step 3: forming a deep groove by photoetching and etching through the buried oxide layer;
step 4: implanting into the substrate at the bottom of the deep trench to obtain a doped island (25) of the second conductivity type;
step 5: forming a longitudinal dielectric oxide layer (31) on the groove wall;
step 6: digging through the bottom dielectric oxide layer by lithography and etching, and penetrating into the second conductivity type doped island (25);
step 7: depositing polycrystal into the deep groove and etching to the silicon plane
Step 8: forming a second conductivity type well region (22) by implanting a second conductivity type impurity with high-energy ions and pushing a junction;
step 9: forming a control gate dielectric oxide layer (32) by thermal oxidation, and forming a field dielectric oxide layer (33) by deposition and etching;
step 10: forming a first conductivity type well region (12) by ion implantation of a first conductivity type impurity and junction pushing;
step 11: depositing polysilicon and etching to form a control gate polysilicon electrode (42);
step 12: the implantation activates the heavily doped emitter region (13) of the first conductivity type, the heavily doped emitter region (23) of the second conductivity type and the heavily doped collector region (24) of the second conductivity type.
8. The method for manufacturing the full-isolation substrate voltage-resistant power semiconductor device according to claim 7, wherein: the method is suitable for SiC and GaN wide forbidden band semiconductors.
9. The method for manufacturing the full-isolation substrate voltage-resistant power semiconductor device according to claim 7, wherein: all dielectric oxide layers are formed by thermal growth, or by deposition and etching.
10. The method for manufacturing the full-isolation substrate voltage-resistant power semiconductor device according to claim 7, wherein: the second conduction type drift region (21) formed by implantation and junction pushing in the step 2 is obtained by an epitaxial method; and/or the first conductivity type well region (12) and the second conductivity type well region (22) obtained by implantation and junction pushing in the steps 8 and 10 are formed by implantation and activation of a plurality of different energies.
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