CN112909091A - Lateral double-diffused transistor and manufacturing method thereof - Google Patents
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The present disclosure relates to the field of semiconductor technology, and provides a lateral double-diffused transistor and a method for manufacturing the same, wherein the LDMOS device comprises: a first epitaxial layer and a second epitaxial layer provided on a substrate; two trench gate structures arranged along the first direction and distributed at intervals are arranged in the second extension; defining a first drift region and a drain terminal region on one side of the second epitaxial layer positioned on the trench gate structure in sequence along a second direction, and a source terminal region on the other side of the trench gate structure; a planar gate structure, a drain injection region arranged in the drain end region and a source injection region arranged in the source end region are arranged on the second epitaxial layer between the two trench gate structures along the first direction; the drain injection region, the source injection region and the metal contact on the gate structure are respectively and correspondingly led out to the drain electrode, the source electrode and the gate electrode. Therefore, the withstand voltage of the LDMOS device can be effectively improved, and the on-resistance of the LDMOS device is reduced.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to a lateral double-diffused transistor and a manufacturing method thereof.
Background
The lateral double-Diffused Metal Oxide Semiconductor (LDMOS) device is a unipolar multi-sub device, has the advantages of good turn-off characteristics, high input impedance, easy large-scale integration and the like, and is widely applied in many fields.
Breakdown voltage and on-resistance are two main parameters that must be considered in designing a power LDMOS device. If the breakdown voltage is increased, the on-resistance is also increased, resulting in an increase in on-state power consumption. Because there is an irreconcilable contradiction between the on-resistance and the breakdown voltage, in practical application, the on-resistance of the power LDMOS device needs to be limited.
One of the most important objectives in the optimized design of LDMOS devices is to achieve the maximum breakdown voltage while keeping the on-resistance as low as possible. Since the two indexes are contradictory to the parameter requirements of the doping concentration and the length of the drift region in the device design, the high breakdown voltage will bring about high on-resistance. Therefore, the contradiction of compromising the breakdown voltage and the on-resistance by optimizing the device structure, materials, and the like has always been a hot spot of research. Common techniques are reduced surface field (RESURF) technique, Super Junction (SJ) technique, field plate technique, and the like.
The RESURF technology is widely applied to a large number of devices, can effectively adjust an electric field of a drift region, improves a Breakdown Voltage (BV) of the device, can assist in depleting the drift region in a voltage-resistant state, and can have a higher doping concentration and a lower on-resistance under the same voltage-resistant condition.
For the LDMOS meeting the RESURF condition, the voltage withstanding property of the device is improved, but the on-resistance and the breakdown voltage of the device still have a proportional relation of 2.5 power. Therefore, the high on-resistance limits the application of LDMOS devices in high voltage applications.
In a conventional double surface field reduction (double resurf) structure, a uniform P-field reduction layer (ptop) can assist in depleting a drift region, and has a higher doping concentration and a lower on-resistance under the same withstand voltage condition, but the improvement performance is limited.
Disclosure of Invention
In order to solve the above technical problem, the present disclosure provides a lateral double-diffused transistor and a method for manufacturing the same, which can effectively improve the withstand voltage of a device and reduce the on-resistance of the device.
In one aspect the present disclosure provides a lateral double diffused transistor, comprising:
the epitaxial wafer comprises a substrate, a first epitaxial layer of a first doping type and a second epitaxial layer of a second doping type, wherein the first epitaxial layer and the second epitaxial layer are sequentially stacked on the substrate;
two trench gate structures which are arranged along a first direction and are distributed at intervals are arranged in the second epitaxial layer, and an extension line of a central connecting line of the two trench gate structures is in a second direction which is orthogonal to the first direction;
defining a first drift region and a drain terminal region on the second epitaxial layer and positioned on one side of the trench gate structure in sequence along the second direction, a source terminal region on the other side of the trench gate structure, and first doped regions arranged around the drift region and the drain terminal region;
the planar gate structure is arranged on the second epitaxial layer between the two trench gate structures along the first direction, and the planar gate structure is communicated with the same structural layer in the trench gate structures;
a drain injection region is arranged in the drain end region and an active injection region is arranged in the source end region;
and the metal contacts on the drain injection region, the source injection region and the gate structure are respectively and correspondingly led out to the drain electrode, the source electrode and the gate electrode.
Preferably, the lateral double diffused transistor further comprises:
and the first drift region is arranged on the drain end region of the second epitaxial layer, which is positioned at one side of the trench gate structure.
Preferably, the lateral double diffused transistor further comprises:
and the bottoms of the two trenches are positioned on the upper surface of the first epitaxial layer.
Preferably, the two trench-gate structures comprise a gate oxide layer and a polysilicon layer arranged in sequence in each of the trenches,
the gate oxide layer covers the bottom and the side wall of the trench, and the top of the gate oxide layer extends to stop at the upper surface of the second epitaxial layer for isolating the polysilicon layer from the second epitaxial layer,
the polycrystalline silicon layer in each groove gate structure fills the groove, and the top surface of the polycrystalline silicon layer is flush with the upper surface of the second epitaxial layer.
Preferably, the aforementioned planar gate structure comprises: a gate oxide layer and a polysilicon layer sequentially stacked on the second epitaxial layer between the two trench gate structures along the first direction,
the gate oxide layer in the planar gate structure is communicated with the gate oxide layer in the trench gate structure in the first direction, and the polysilicon layer is communicated with the polysilicon layer in the trench gate structure in the first direction.
Preferably, the drain implant region includes:
a first implantation region located in at least one of the first doped regions of the drain region;
and, the source implant region includes:
at least one first implantation region and at least one second implantation region in the source region, the first implantation region and the second implantation region having opposite doping types.
Preferably, the metal contacts on the drain injection region, the source injection region and the gate structure respectively and correspondingly led out to the drain electrode, the source electrode and the gate electrode comprise:
the first injection region of at least one of the first doping regions in the drain terminal region is correspondingly led out to the drain electrode through metal contact;
at least one first injection region and at least one second injection region which are positioned in the source end region are correspondingly led out to a source electrode through metal contact;
and the polycrystalline silicon layers which are positioned in the groove gate structure and the plane gate structure and communicated with each other are correspondingly led out to the gate electrode through metal contact.
In another aspect, the present disclosure further provides a method for manufacturing a lateral double diffused transistor, including:
sequentially forming a first epitaxial layer of a first doping type and a second epitaxial layer of a second doping type on a substrate;
forming two trench gate structures which are arranged along a first direction and are distributed at intervals in the second epitaxial layer, wherein an extension line of a central connecting line of the two trench gate structures is in a second direction which is orthogonal to the first direction;
defining a first drift region and a drain terminal region on the second epitaxial layer and positioned on one side of the trench gate structure in sequence along the second direction, a source terminal region positioned on the other side of the trench gate structure, and forming a first doped region around the first drift region and the drain terminal region through ion implantation;
forming a planar gate structure on the second epitaxial layer between the two trench gate structures along the first direction, wherein the planar gate structure is communicated with the same structural layer in the trench gate structures;
forming a drain injection region and a source injection region in the drain end region and the source end region respectively through ion injection;
and metal contacts are respectively formed on the drain injection region, the source injection region and the gate structure and are correspondingly led out to the drain electrode, the source electrode and the gate electrode.
Preferably, the step of forming a first doped region by ion implantation in the drain region includes:
forming a first drift region of a first doping type between the drain terminal region and the trench gate structure along the second direction on the second epitaxial layer through ion implantation;
forming the first doped region on the second epitaxial layer along the second direction at a side thereof away from the trench gate structure by ion implantation,
the first doping region is formed to contact with the first drift region and bottom-diffused into the substrate.
Preferably, the step of sequentially forming the epitaxial layer of the first doping type and the second epitaxial layer of the second doping type on the substrate includes:
forming a first epitaxial layer on the substrate through epitaxial growth;
forming a second drift region in the epitaxial layer by ion implantation of the first doping type; and
the aforementioned second epitaxial layer of the second doping type is formed on the first epitaxial layer by epitaxial growth.
Preferably, the step of forming two trench gate structures arranged along the first direction and spaced apart from each other in the second epitaxial layer includes:
forming two trenches which are arranged along a first direction and distributed at intervals in the second epitaxial layer, wherein the bottoms of the two formed trenches are positioned in the epitaxial layer;
depositing and growing a gate oxide layer in each groove, wherein the formed gate oxide layer covers the bottom and the side wall of each groove, and the top of the gate oxide layer extends and stops on the upper surface of the second epitaxial layer;
depositing and growing a polysilicon layer on the gate oxide layer, forming the trench gate structure in each trench,
the polysilicon layer in each trench gate structure fills the trench, and the top surface of the polysilicon layer is flush with the upper surface of the second epitaxial layer.
Preferably, the step of forming a planar gate structure on the second epitaxial layer between the two trench gate structures along the first direction includes:
depositing and growing a gate oxide layer on the second epitaxial layer between the two trench gate structures along the first direction, wherein the formed gate oxide layer extends and grows in the first direction and is communicated with the gate oxide layer in the trench gate structures; and
and depositing and growing a polycrystalline silicon layer on the gate oxide layer to form the planar gate structure, wherein the formed polycrystalline silicon layer extends and grows in the first direction to be communicated with the polycrystalline silicon layer in the trench gate structure.
Preferably, the step of forming source and drain implanted regions in the drain region and the source region by ion implantation respectively includes:
forming at least one first implanted region in the first doped region of the drain region by ion implantation;
and forming at least one first implantation region and at least one second implantation region in the source terminal region by ion implantation, wherein the doping types of the first implantation region and the second implantation region are opposite.
Preferably, the step of forming metal contacts on the drain injection region, the source injection region and the gate structure respectively and correspondingly leading out to the drain electrode, the source electrode and the gate electrode comprises:
forming a metal contact on the first injection region of at least one of the first doping regions and leading the metal contact to the drain electrode;
forming metal contacts on at least one first injection region and at least one second injection region in the source region and leading out to a source electrode together;
and forming metal contacts on the polycrystalline silicon layers communicated with each other in the groove gate structure and the plane gate structure and leading out the metal contacts to the gate electrode.
The beneficial effects of this disclosure are: the present disclosure provides a lateral double diffused transistor and a method of fabricating the same, the LDMOS device formed using the method of fabricating the same including: the epitaxial layer structure comprises a first epitaxial layer and a second epitaxial layer which are sequentially stacked on a substrate; two trench gate structures which are arranged in the second epitaxial layer along a first direction and are distributed at intervals, and an extension line of a central connecting line of the two trench gate structures is in a second direction which is orthogonal to the first direction; defining a first drift region and a drain terminal region on the second epitaxial layer and positioned on one side of the trench gate structure in sequence along the second direction, a source terminal region on the other side of the trench gate structure, and a first doped region around the first drift region and the drain terminal region; the planar gate structure is arranged on the second epitaxial layer between the two trench gate structures along the first direction, and the planar gate structure is communicated with the same structural layer in the trench gate structures; a drain injection region and a source injection region respectively arranged in the drain end region and the source end region; the drain injection region, the source injection region and the metal contact on the gate structure are respectively and correspondingly led out to the drain electrode, the source electrode and the gate electrode. Therefore, when the LDMOS device is in a conducting state and the gate electrode is at a high potential, a channel is formed on the side wall of the trench gate structure at the bottom of the planar gate structure, and the area of the channel is effectively increased;
meanwhile, electrons flow from the source electrode through the channel region and respectively flow to the drain electrode through the high-concentration N-type (the first epitaxial layer (also the second drift region) and the first drift region) region and the low-concentration N-type (the first epitaxial layer (also the second drift region)) region, so that the conduction current path is increased, and the conduction resistance is reduced. In a voltage-resistant state, a p-type region (second epitaxial layer) between two high-concentration N-type (first epitaxial layer (second drift region) and first drift region) regions can play a role in assisting in depleting the drift region, effectively reducing an electric field of the drift region and increasing the voltage resistance of the LDMOS device.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 illustrates a schematic perspective view of a lateral double-diffused transistor device provided in an embodiment of the present disclosure;
FIG. 2a illustrates a front view of the lateral double diffused transistor device structure shown in FIG. 1;
FIG. 2b illustrates a right side view of the lateral double diffused transistor device structure shown in FIG. 1;
FIG. 3a shows a top view of the lateral double diffused transistor device structure shown in FIG. 1;
fig. 3b shows a schematic cross-sectional view of the lateral double diffused transistor device of fig. 1 in a right view direction along a cut plane at the tangent of BB' in fig. 3 a;
fig. 4 is a schematic flow chart illustrating a method for fabricating a lateral double diffused transistor device according to an embodiment of the present disclosure;
fig. 5a1 to 5e show schematic sectional structures of the manufacturing method shown in fig. 4 at various stages in the front view direction along the section corresponding to the AA 'tangent line in fig. 3a and in the right view direction along the section corresponding to the BB' tangent line in fig. 3a, respectively.
Detailed Description
Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Also as used in this disclosure, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Unless otherwise specified below, various layers or regions of a semiconductor device may be composed of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge. The gate conductor, electrode layer may be formed of various conductive materials such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the foregoing various conductive materials.
In the present disclosure, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
In addition, the term "semiconductor field" used in this disclosure is a term commonly used by those skilled in the art, for example, for P-type and N-type impurities, in order to distinguish doping concentrations, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
Specific embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and examples.
Fig. 1 shows a schematic perspective view of a lateral double-diffused transistor device provided by an embodiment of the present disclosure, fig. 2a shows a front view of the structure of the lateral double-diffused transistor device shown in fig. 1, fig. 2b shows a right side view of the structure of the lateral double-diffused transistor device shown in fig. 1, fig. 3a shows a top view of the structure of the lateral double-diffused transistor device shown in fig. 1, and fig. 3b shows a schematic cross-sectional view of the lateral double-diffused transistor device shown in fig. 1 along a cut plane of a cut line BB' in fig. 3a in a right view direction, wherein the LDMOS device in the embodiment of the present disclosure is illustrated by taking an N-type as an example, but the content of the present disclosure is not limited thereto, and the same principle can be similarly applied to a P-type LDMOS device and a manufacturing method thereof, and such an alternative.
Referring to fig. 1 to fig. 3b, in one aspect, an NLDMOS device 100 according to an embodiment of the present disclosure includes: a first epitaxial layer 103 of a first doping type and a second epitaxial layer 104 of a second doping type are sequentially stacked on the P-type substrate 101;
two trench gate structures G1 and G2 (shown in fig. 3 b) are disposed in the second epitaxial layer 104 and are arranged in a first direction at intervals, and an extension line of a central connecting line of the two trench gate structures G1 and G2 is in a second direction orthogonal to the first direction;
defining a first drift region 107 and a drain region on the second epitaxial layer 104 located at one side of the trench gate structure in sequence along the second direction, a source region located at the other side of the trench gate structure, and a first doped region 109 around the first drift region 107 and the drain region;
a planar gate structure G3 (shown in fig. 3 b) disposed in the first direction on the second epitaxial layer 104 between the two trench gate structures G1 and G2, the planar gate structure G3 being in communication with the same structural layers in the trench gate structure;
a drain injection region and a source injection region respectively arranged in the drain end region and the source end region;
metal contacts located on the aforementioned drain, source and gate structures (G1, G2 and G3) are respectively led out to the drain, source and gate electrodes (not shown).
The first direction is, for example, a direction of a BB 'tangent shown in fig. 3a, and the second direction orthogonal to the first direction is, for example, a direction of an AA' tangent shown in fig. 3a, and both the first direction and the second direction are directions consistent with the definition, and will not be described again.
Further, in the NLDMOS device 100, the first drift region 107 of the first doping type is disposed on the second epitaxial layer 104 along the second direction between the trench gate structure and the drain region.
Further, the NLDMOS device 100 further includes:
two trenches are arranged in the second epitaxial layer 104 along the first direction and spaced apart from each other, and the bottoms of the two trenches are located on the upper surface of the first epitaxial layer 103.
Further, the aforementioned two trench gate structures include a gate oxide layer 105 and a polysilicon layer 106 sequentially disposed in each trench,
the gate oxide layer 105 covers the bottom and sidewalls of the trench, and the top extends to stop at the upper surface of the second epitaxial layer 104 for isolating the polysilicon layer 106 from the second epitaxial layer 104, the polysilicon layer 106 in each of the trench gate structures fills the trench, and the top surface is flush with the upper surface of the second epitaxial layer 104.
Further, the aforementioned planar gate structure G3 includes: and a gate oxide layer 105 and a polysilicon layer 106 sequentially stacked on the second epitaxial layer 104 between the two trench gate structures G1 and G2 along the first direction, wherein the gate oxide layer 105 in the planar gate structure G3 is in communication with the gate oxide layers 105 in the trench gate structures G1 and G2 in the first direction, and the polysilicon layer 106 is in communication with the polysilicon layer 106 in the trench gate structures G1 and G2 in the first direction.
Further, in the NLDMOS device 100, the drain implant region includes:
a first implant area 1103 located in at least one of the first doped regions 109 of the drain region,
the source implant region includes:
at least one first implant region 1102 and at least one second implant region 1101 located in the aforementioned source region, and the first implant region (1103 and 1102) is of opposite doping type to the second implant region 1101.
Specifically, in one embodiment, the first implanted region is N-type doped, the second implanted region is P-type doped, and the second implanted region 1101 is a body contact region with an electrode leading to a body electrode. According to the related art, the body contact region 1101 is generally led out together with the source implant region (i.e., the first implant region 1102) to the source electrode (the body electrode is connected to the source electrode) in the process of leading out the electrode, so a detailed description thereof is omitted.
Further, the metal contacts on the drain injection region, the source injection region and the gate structure are respectively led out to the drain electrode, the source electrode and the gate electrode correspondingly, and the metal contacts comprise:
the first implantation region 1103 of at least one of the first doping regions 109 located in the aforementioned drain region is correspondingly led out to the drain electrode through a metal contact;
at least one first implantation region 1102 and at least one second implantation region 1101 located in the aforementioned source region are commonly extracted to the source electrode through metal contacts;
the polysilicon layer 106 located in the trench gate structure (G1 and G2) and the planar gate structure G3 and communicated with each other is correspondingly led out to the gate electrode through metal contact.
Further, the first doping type is an N type, and the second doping type is a P type; or the first doping type is P type, and the second doping type is N type.
Further, in the NLDMOS device 100 of this embodiment, the first epitaxial layer 103 of the first doping type may also be referred to as a second drift region, and the first drift region 107 and the second epitaxial layer 104 are both N-type high doping concentration and P-type high doping concentration, so as to form a drift region with a variable doping profile in the longitudinal direction.
In this embodiment, in an on state, when the gate electrode is at a high potential, at the bottom of the planar gate structure, the carriers (electrons or holes) on the sidewall of the trench gate structure are accumulated to form a conductive channel, so that the channel area is effectively increased, and the loss is reduced;
meanwhile, electrons flow from the source electrode through the channel region and respectively flow to the drain electrode through the high-concentration and low-concentration N-type (the first epitaxial layer 103 (also referred to as a second drift region) and the first drift region 107) regions, so that the conduction current path is increased, and the on-resistance is reduced. In a state of voltage resistance, a p-type region (second epitaxial layer 104) between two high-concentration N-type regions (first epitaxial layer 103 (also referred to as second drift region) and first drift region 107) can play a role of assisting in depletion of the drift region, effectively lower the electric field of the drift region, and increase the voltage resistance of the NLDMOS device 100.
Fig. 4 is a schematic flow chart illustrating a method for manufacturing a lateral double diffused transistor device according to an embodiment of the present disclosure, and fig. 5a 1-5 e respectively illustrate schematic cross-sectional structures at various stages of the manufacturing method shown in fig. 4 in a front view direction along a cut plane corresponding to a cut line AA 'in fig. 3a and in a right view direction along a cut plane corresponding to a cut line BB' in fig. 3 a.
Referring to fig. 4 to 5e, in another aspect, a method for manufacturing an NLDMOS device according to an embodiment of the present disclosure includes:
step S110: a first epitaxial layer of a first doping type and a second epitaxial layer of a second doping type are sequentially formed on a substrate.
In step S110, a first epitaxial layer is first formed on the P-type substrate 101 by epitaxial growth; forming a second drift region of the first doping type on the first epitaxial layer through ion implantation; and forming a second epitaxial layer 104 of a second doping type on the first epitaxial layer 103 by epitaxial growth, as shown in figure 5a 1. Fig. 5a1 is a schematic cross-sectional view of the semiconductor structure formed in this step, taken along a tangent plane corresponding to the tangent line BB' in fig. 3a in a right-view direction (first direction). Here, in order to obtain a semiconductor device with uniform threshold voltage, the second epitaxial layer 104 can only be epitaxially grown.
Step S120: and forming two trench gate structures which are arranged along the first direction and distributed at intervals in the second epitaxial layer.
In step S120, two trenches arranged along the first direction and spaced apart from each other are etched in the second epitaxial layer 104 by a trench process, and bottoms of the two trenches are located in the first epitaxial layer 103, as shown in fig. 5b1 and fig. 5b 2. Fig. 5b1 is a schematic cross-sectional view of the semiconductor structure formed in this step along the tangent plane corresponding to the BB 'in fig. 3a in the right viewing direction (the first direction), and fig. 5b2 is a schematic cross-sectional view of the semiconductor structure formed in this step along the tangent plane corresponding to the AA' in fig. 3a in the main viewing direction (the second direction).
And then sequentially depositing and growing a gate oxide layer 105 and a polysilicon layer 106 in each trench to form the trench gate structures G1 and G2, as shown in FIGS. 5c1 and 5c 2. Fig. 5c1 is a schematic cross-sectional view of the semiconductor structure formed in this step along the tangent plane corresponding to the BB 'in fig. 3a in the right viewing direction (the first direction), and fig. 5c2 is a schematic cross-sectional view of the semiconductor structure formed in this step along the tangent plane corresponding to the AA' in fig. 3a in the main viewing direction (the second direction). The gate oxide layer 105 is formed to cover the bottom and the sidewall of the trench, and the top of the gate oxide layer extends to stop at the upper surface of the first epitaxial layer 103, and the polysilicon layer 106 in each of the trench gate structures G1 or G2 fills the trench, and the top surface of the trench gate structure is flush with the upper surface of the second epitaxial layer 104, and simultaneously the extension line of the central connecting line of the two trench gate structures G1 and G2 is in the second direction orthogonal to the first direction.
Step S130: and defining a first drift region and a drain terminal region on one side of the second epitaxial layer positioned on the trench gate structure along the second direction, and a source terminal region on the other side of the trench gate structure, and forming a first doped region around the first drift region and the drain terminal region by ion implantation.
In step S130, a first drift region 107 of the first doping type is formed on the second epitaxial layer 104 between the trench gate structure and the drain region along the second direction by ion implantation, and then a first doped region 109 is formed on the second epitaxial layer 104 along the second direction at the drain region on the side away from the trench gate structure by ion implantation, the formed first doped region 109 contacts the first drift region 107, and the bottom of the first doped region 109 is diffused onto the substrate 101, as shown in fig. 5d 1. Fig. 5d1 is a schematic cross-sectional view of the semiconductor structure formed in this step along the cut plane corresponding to the cut line AA' in fig. 3a in the front view direction (second direction).
Step S140: and forming a planar gate structure on the second epitaxial layer between the two trench gate structures along the first direction.
In step S140, a gate oxide layer 105 and a polysilicon layer 106 are sequentially deposited and grown on the second epitaxial layer 104 between the two trench gate structures along the first direction to form a planar gate structure G3, and the planar gate structure G3 is formed to communicate with the same structural layer in the trench gate structures. As shown in fig. 5d1 and 5d 2. Fig. 5d1 is a schematic cross-sectional view of the semiconductor structure formed in this step along the cut plane corresponding to the cut line AA 'in fig. 3a in the main viewing direction (second direction), and fig. 5d2 is a schematic cross-sectional view of the semiconductor structure formed in this step along the cut plane corresponding to the cut line BB' in fig. 3a in the right viewing direction (first direction). Specifically, the gate oxide layer 105 in the planar gate structure G3 is formed to extend in the first direction and communicate with the gate oxide layer 105 in the trench gate structure; and the formed polysilicon layer 106 is grown in the first direction and is communicated with the polysilicon layer 106 in the trench gate structure.
Step S150: and respectively forming a drain injection region and a source injection region in the drain end region and the source end region through ion injection.
In step S150, at least one first implantation region 1103 is formed as the drain implantation region by ion implantation in the first doping region 109 of the drain region, and at least one first implantation region 1102 and at least one second implantation region 1101 are formed as the source implantation region by ion implantation in the source region, as shown in fig. 5e, and the doping types of the first implantation region (1103 and 1102) and the second implantation region 1101 are opposite. Specifically, in one embodiment, the doping type of the first implant region (1103 and 1102) is N-type, the doping type of the second implant region 1101 is P-type, and the second implant region 1101 is a body contact region, and its electrodes are led out to the body electrodes. According to the related art, the body contact region 1101 is generally led out together with the source implant region (i.e., the first implant region 1102) to the source electrode (the body electrode is connected to the source electrode) in the process of leading out the electrode, so a detailed description thereof is omitted.
Further, the first doping type is N-type, and the second doping type is P-type; or the first doping type is P type, and the second doping type is N type.
Further, in the method for manufacturing the NLDMOS device of this embodiment, the first epitaxial layer 103 of the first doping type may also be referred to as a second drift region, and the first drift region 107 and the second epitaxial layer 104 are both N-type high doping concentration and P-type high doping concentration, so as to form a drift region with a variable doping profile in the longitudinal direction.
Step S160: and metal contacts are respectively formed on the drain injection region, the source injection region and the gate structure and are correspondingly led out to the drain electrode, the source electrode and the gate electrode.
In step S160, a metal contact is formed on the first implantation region 1103 in the drain terminal region and led out to the drain electrode, a metal contact is formed on the first implantation region 1102 and the second implantation region 1101 in the source terminal region and led out to the source electrode in common, and a metal contact is formed on the polysilicon layer 106 communicating in the trench gate structure (G1 and G2) and the planar gate structure G3 and led out to the gate electrode, thereby forming the NLDMOS device provided in the foregoing embodiment.
In summary, the present disclosure provides a lateral double diffused transistor and a method for manufacturing the same, where the NLDMOS device formed by using the method for manufacturing the lateral double diffused transistor includes: a first epitaxial layer 103 (also referred to as a second drift region) and a second epitaxial layer 104 which are sequentially stacked on the P-type substrate 101; two trench gate structures arranged along a first direction and distributed at intervals are arranged on the second epitaxial layer 104, and an extension line of a central connecting line of the two trench gate structures is in a second direction orthogonal to the first direction; defining a first drift region 107 and a drain region on the second epitaxial layer 104 located at one side of the trench gate structure in sequence along the second direction, a source region located at the other side of the trench gate structure, and a first doped region 109 around the first drift region 107 and the drain region; a planar gate structure disposed on the second epitaxial layer 104 between the two trench gate structures along a first direction, the planar gate structure being in communication with the same structural layer in the trench gate structure, and a drain injection region and a source injection region being disposed in the drain end region and the source end region, respectively; the metal contacts on the drain injection region, the source injection region and the gate structure (trench gate structure and planar gate structure) are respectively and correspondingly led out to the drain electrode, the source electrode and the gate electrode. Therefore, when the gate electrode of the NLDMOS device is at a high potential in an on state, a channel is formed on the side wall of the trench gate structure at the bottom of the planar gate structure, and the area of the channel is effectively increased; meanwhile, electrons flow from the source electrode through the channel region and respectively flow to the drain electrode through the high-concentration and low-concentration N-type (the first epitaxial layer 103 (also referred to as a second drift region) and the first drift region 107) regions, so that the conduction current path is increased, and the on-resistance is reduced. In a voltage-resistant state, a p-type region (second epitaxial layer 104) between two high-concentration N-type (first epitaxial layer 103 (also called as a second drift region) and first drift region 107) regions can play a role of assisting in depletion of the drift region, effectively lower and regulate an electric field of the drift region, and increase the voltage resistance of the NLDMOS device.
It should be noted that in the description of the present disclosure, it is to be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.
Claims (10)
1. A lateral double diffused transistor, comprising:
the epitaxial wafer comprises a substrate, a first epitaxial layer of a first doping type and a second epitaxial layer of a second doping type, wherein the first epitaxial layer and the second epitaxial layer are sequentially stacked on the substrate;
two trench gate structures which are arranged along a first direction and distributed at intervals are arranged in the second epitaxial layer, and an extension line of a central connecting line of the two trench gate structures is in a second direction which is orthogonal to the first direction;
defining a first drift region and a drain terminal region on one side of the second epitaxial layer positioned on the trench gate structure in sequence along the second direction, a source terminal region on the other side of the trench gate structure, and a first doped region arranged around the drift region and the drain terminal region;
a planar gate structure is arranged on the second epitaxial layer between the two trench gate structures along the first direction, and the planar gate structure is communicated with the same structural layer in the trench gate structures;
a drain injection region arranged in the drain end region and a source injection region arranged in the source end region;
and the metal contacts on the drain injection region, the source injection region and the gate structure are respectively and correspondingly led out to the drain electrode, the source electrode and the gate electrode.
2. The lateral double diffused transistor of claim 1 further comprising:
the two trenches are arranged in the second epitaxial layer along the first direction and distributed at intervals, and the bottoms of the two trenches are located on the upper surface of the first epitaxial layer.
3. The lateral double diffused transistor of claim 2 wherein said two trench gate structures comprise a gate oxide layer and a polysilicon layer disposed in sequence in each of said trenches,
the gate oxide layer covers the bottom and the side wall of the groove, the top of the gate oxide layer extends and stops on the upper surface of the second epitaxial layer and is used for isolating the polycrystalline silicon layer from the second epitaxial layer,
and the polycrystalline silicon layer in each groove gate structure fills the groove, and the top surface of the polycrystalline silicon layer is flush with the upper surface of the second epitaxial layer.
4. The lateral double diffused transistor of claim 3 wherein the planar gate structure comprises: a gate oxide layer and a polysilicon layer sequentially stacked on the second epitaxial layer between the two trench gate structures along the first direction,
the gate oxide layer in the planar gate structure is communicated with the gate oxide layer in the trench gate structure in the first direction, and the polycrystalline silicon layer is communicated with the polycrystalline silicon layer in the trench gate structure in the first direction.
5. The lateral double diffused transistor of claim 4 wherein the drain implant region comprises:
a first implant region located in at least one of the first doped regions of the drain terminal region,
and, the source implant region includes:
at least one first implantation region and at least one second implantation region in the source region, the first implantation region being of opposite doping type to the second implantation region.
6. A method of fabricating a lateral double diffused transistor, comprising:
sequentially forming a first epitaxial layer of a first doping type and a second epitaxial layer of a second doping type on a substrate;
forming two trench gate structures which are arranged along a first direction and are distributed at intervals in the second epitaxial layer, wherein an extension line of a central connecting line of the two trench gate structures is in a second direction which is orthogonal to the first direction;
defining a first drift region and a drain terminal region on the second epitaxial layer and positioned on one side of the trench gate structure in sequence along the second direction, a source terminal region on the other side of the trench gate structure, and forming a first doped region around the first drift region and the drain terminal region through ion implantation;
forming a planar gate structure on the second epitaxial layer between the two trench gate structures along the first direction, wherein the planar gate structure is communicated with the same structural layer in the trench gate structures;
forming a drain injection region and a source injection region in the drain end region and the source end region respectively through ion injection;
and respectively forming metal contacts on the drain injection region, the source injection region and the gate structure, and correspondingly leading out the metal contacts to the drain electrode, the source electrode and the gate electrode.
7. The method of manufacturing of claim 6, wherein the step of forming a first doped region around the first drift region and drain end region by ion implantation comprises:
forming the first drift region of the first doping type on the second epitaxial layer along the second direction between the drain terminal region and the trench gate structure through ion implantation;
forming the first doped region by ion implantation in a drain region on the second epitaxial layer on a side away from the trench gate structure along the second direction,
the first doped region is formed in contact with the first drift region and bottom diffused into the substrate.
8. The manufacturing method of claim 7, wherein the step of sequentially forming a first epitaxial layer of a first doping type and a second epitaxial layer of a second doping type on a substrate comprises:
forming a first epitaxial layer on the substrate through epitaxial growth;
forming a second drift region in the first epitaxial layer by ion implantation of a first doping type; and
and forming the second epitaxial layer of the second doping type on the first epitaxial layer by utilizing epitaxial growth.
9. The manufacturing method of claim 8, wherein the step of forming two trench gate structures arranged along the first direction and spaced apart in the second epitaxial layer comprises:
forming two trenches which are arranged along a first direction and distributed at intervals in the second epitaxial layer, wherein the bottoms of the two formed trenches are positioned on the upper surface of the first epitaxial layer;
depositing and growing a gate oxide layer in each groove, wherein the formed gate oxide layer covers the bottom and the side wall of each groove, and the top of the gate oxide layer extends and stops on the upper surface of the second epitaxial layer;
depositing and growing a polysilicon layer on the gate oxide layer, forming the trench gate structure in each trench,
and filling the groove with a polysilicon layer in each groove gate structure, wherein the top surface of the polysilicon layer is flush with the upper surface of the second epitaxial layer.
10. The method of manufacturing of claim 9, wherein forming a planar gate structure on the second epitaxial layer between the two trench gate structures along the first direction, the step of communicating between the planar gate structure and a same structural layer of the trench gate structure comprises:
depositing and growing a gate oxide layer on the second epitaxial layer between the two trench gate structures along the first direction, wherein the formed gate oxide layer extends and grows in the first direction and is communicated with the gate oxide layer in the trench gate structures; and
and depositing and growing a polycrystalline silicon layer on the gate oxide layer to form the planar gate structure, wherein the formed polycrystalline silicon layer extends and grows in the first direction to be communicated with the polycrystalline silicon layer in the groove gate structure.
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| CB02 | Change of applicant information |
Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Applicant after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Applicant before: JOULWATT TECHNOLOGY Inc.,Ltd. |
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210604 |