CN114361250A - Mosfet with enhanced high frequency performance - Google Patents

Mosfet with enhanced high frequency performance Download PDF

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Publication number
CN114361250A
CN114361250A CN202111547635.XA CN202111547635A CN114361250A CN 114361250 A CN114361250 A CN 114361250A CN 202111547635 A CN202111547635 A CN 202111547635A CN 114361250 A CN114361250 A CN 114361250A
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Prior art keywords
gate
region
conductivity type
trench gate
trench
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Inventor
许曙明
吴健
陈劲甫
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Shanghai Bright Power Semiconductor Co Ltd
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Lilaito Semiconductor Shanghai Co ltd
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Priority to CN202111547635.XA priority Critical patent/CN114361250A/en
Priority to US17/684,849 priority patent/US20220384594A1/en
Publication of CN114361250A publication Critical patent/CN114361250A/en
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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Abstract

The present invention provides a metal oxide semiconductor field effect transistor with enhanced high frequency performance, comprising a semiconductor substrate serving as a drain region and an epitaxial region disposed on an upper surface of the substrate. The MOSFET device includes a plurality of body regions and a plurality of source regions formed in an epitaxial region. The body regions are disposed adjacent an upper surface of the epitaxial region and are laterally spaced apart from one another, and each source region is disposed in a corresponding body region proximate the upper surface of the body region. The MOSFET device includes a gate structure having a plurality of planar gates and a trench gate. Each planar gate is disposed on an upper surface of the epitaxial region and overlaps a corresponding body region. The trench gate is formed partially through the epitaxial regions and between the body regions, with an upper surface of the trench gate recessed below an upper surface of the epitaxial regions.

Description

Mosfet with enhanced high frequency performance
Technical Field
The present invention relates generally to electrical, electronic and computer technology, and more particularly to power transistor devices and methods of fabrication.
Background
Power transistors, such as power metal-oxide-semiconductor field effect transistors (MOSFETs), are typically designed to maintain a high source-to-drain current density in the on state and a high blocking voltage between the drain and source in the off state. There are many transistor device types, such as lateral and vertical devices, planar and trench gates, unipolar and bipolar transistors, each designed for a specific application. Many design parameters are mutually exclusive such that an improvement in one parameter results in a degradation of another parameter. Thus, there are certain performance tradeoffs in different transistor designs.
The design and performance criteria of a transistor can be measured by several attributes, including the drain-source Breakdown Voltage (BV)ds) Characteristic on-resistance (R)sp) Grid capacitance (C)g) And gate-drain capacitance (C)gd). These performance characteristics depend in large part on factors such as the design, structure, and material selection of the transistor. Furthermore, these transistor performance characteristics often follow opposing trends in key design parameters, such as gate length, channel and drift region doping concentrations, drift region length, total gate width, and so forth, making the design of transistor devices challenging. For example, increasing the drift region doping concentration in a transistor decreases the characteristic on-resistance and also decreases the breakdown voltage, which may make the transistor device unable to meet the breakdown voltage rating for a particular application. Similarly, a large gate width may reduce the overall on-resistance of the transistor device, but at the same time may also increase the parasitic gate capacitance, thereby increasing the switching losses of the transistor. Therefore, transistor design often involves some critical devices in practiceThe choice of parameters is taken into account in order to achieve a compromise between the performance characteristics.
One important performance parameter that determines the efficiency and reliability of a transistor device is the miller capacitance, or gate-to-drain capacitance. As the demand for higher efficiency continues to increase, power MOSFET designs tend to have smaller gate sizes with correspondingly lower gate charges (Q)g) And lower threshold voltage (V)t) Which makes the device more susceptible to drain voltage spikes due to miller capacitance coupling effects. At the same time, the higher transistor switching frequency, and the increased parasitic inductance, result in an increase in the drain ringing voltage. The combined effect of these effects makes present day power transistor devices prone to drain voltages causing false turn-on, thereby damaging the device. Another very challenging fact is that miller capacitance is particularly difficult to reduce and, as a design compromise, often leads to increased on-resistance of the device. Conventional approaches to reducing parasitic gate-drain capacitance inevitably result in higher device on-resistance, and therefore reducing miller capacitance in power transistor devices is likely one of the most difficult design goals to achieve, and is a key requirement for product performance and application reliability.
Chinese application CN112614891A filed by the present inventor on 12/17/2020 (priority date 2020/3/4) discloses a mosfet with enhanced high frequency performance comprising an epitaxial region formed on an upper surface of a substrate and at least two body regions formed in the epitaxial region, the body regions being located close to the upper surface of the epitaxial region and laterally spaced from each other. The device also comprises at least two source regions which are arranged in the corresponding body regions and are close to the upper surface of the body regions, and a gate structure which comprises at least two planar gates and a trench gate. Each planar gate is located on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region. The trench gate is positioned between the two body regions and at least partially positioned in the epitaxial region; and a drain contact located on the back side of the substrate and electrically connected to the substrate. The technical scheme of the application can obtain lower on resistance, lower grid-drain (Miller) capacitance, lower switching loss and higher off-state blocking voltage.
However, the disadvantage of this invention is that it is very difficult to further improve the performance based on the lower on-resistance, lower gate-to-drain (miller) capacitance, lower switching loss, and higher off-state blocking voltage.
On the basis of the technical scheme, the metal oxide semiconductor field effect transistor device further reduces the grid coupling capacitance, and obtains lower on resistance, lower grid-drain (Miller) capacitance, lower switching loss and higher off-state blocking voltage.
Disclosure of Invention
A first object provided by the present invention is to provide a mosfet device with a further reduced gate coupling capacitance and resulting in a lower on-resistance, a lower gate-to-drain (miller) capacitance, a lower switching loss, a higher off-state blocking voltage.
A second object of the present invention is to provide a method of manufacturing a mosfet device with a further reduced gate coupling capacitance and resulting in a lower on-resistance, a lower gate-to-drain (miller) capacitance, a lower switching loss, a higher off-state blocking voltage.
It is a third object of the present invention to provide a capacitor that produces a further reduced gate coupling capacitance.
It is a fourth object of the present invention to provide a method of manufacturing a capacitor that produces a further reduced gate coupling capacitance.
A first aspect of the present invention provides a metal oxide semiconductor field effect transistor device comprising:
a semiconductor substrate having a first conductivity type, the substrate serving as a drain region of the metal oxide semiconductor field effect transistor;
an epitaxial region having a first conductivity type disposed on an upper surface of the substrate;
a plurality of body regions of a second conductivity type formed in the epitaxial region, the second conductivity type being opposite the first conductivity type, the body regions being disposed adjacent an upper surface of the epitaxial region and laterally spaced apart from one another;
a plurality of source regions of a first conductivity type, each of the source regions being disposed in a corresponding body region and adjacent to an upper surface of the body region; and
a gate structure comprising: one or more planar gates and a trench gate, each planar gate being located on the upper surface of the epitaxial region and overlapping at least a portion of a corresponding body region; the trench gate is formed in at least part of the epitaxial region and between the body regions; an upper surface of the trench gate is configured to be recessed in the upper surface of the epitaxial region.
A second aspect of the invention provides a method of fabricating a metal oxide semiconductor field effect transistor device, the method comprising:
forming an epitaxial region of a first conductivity type on at least a portion of an upper surface of a substrate of the first conductivity type, the substrate serving as a drain region of the mosfet;
forming a plurality of body regions of a second conductivity type opposite in polarity to the first conductivity type in the epitaxial region, the body regions being disposed adjacent an upper surface of the epitaxial region and laterally spaced apart from one another;
forming a plurality of source regions having a first conductivity type, each of the source regions being disposed in a corresponding body region and adjacent to an upper surface of the body region; and
forming a gate structure including one or more planar gates and a trench gate, each planar gate being disposed on the upper surface of the epitaxial region and overlapping at least a portion of a corresponding body region; the trench gate is formed in at least part of the epitaxial region and between the body regions; an upper surface of the trench gate is configured to be recessed in the upper surface of the epitaxial region.
A third aspect of the present invention provides a capacitor, comprising:
a semiconductor substrate having a first conductivity type;
an epitaxial region having a first conductivity type disposed on at least a portion of the upper surface of the substrate, the epitaxial region constituting a first plate of the capacitor;
the trench gate is formed in at least part of the epitaxial region and is close to the upper surface of the epitaxial region; the trench gate comprising a conductor or semiconductor material forming a second plate of the capacitor surrounded by a dielectric layer electrically isolating the conductor or semiconductor from the epitaxial region;
a plurality of doped regions of the first conductivity type disposed in the epitaxial region and on opposite sides of the trench gate and proximate an upper surface of the epitaxial region; and
a plurality of doped regions of a second conductivity type opposite in polarity to the first conductivity type, each doped region of the second conductivity type having a first end adjacent a respective one of the doped regions of the first conductivity type and a second end opposite the first end and adjacent a respective sidewall of the trench gate.
A fourth aspect of the present invention provides a method of manufacturing a capacitor, the method comprising:
forming an epitaxial region of a first conductivity type on at least a portion of an upper surface of the substrate, the epitaxial region constituting a first plate of the capacitor;
forming a trench gate in at least part of the epitaxial region and close to the upper surface layer of the epitaxial region; the trench gate contains a conductor or semiconductor material that serves as a second plate of the capacitor and is surrounded by a dielectric layer that electrically isolates the conductor or semiconductor from the epitaxial region;
forming a plurality of doped regions with a first conductivity type on opposite sides of the trench gate in the epitaxial region and near an upper surface of the epitaxial region; and
forming a plurality of doped regions having a second conductivity type, the second conductivity type being opposite in polarity to the first conductivity type; a first end of each of the doped regions of the second conductivity type abuts a respective one of the doped regions of the first conductivity type and a second end opposite the first end abuts a respective sidewall of the trench gate.
The invention can bring at least one of the following beneficial effects:
lower on-resistance
Lower gate-drain (miller) capacitance;
lower switching losses;
higher off-state blocking voltage.
Lower coupling capacitance between planar and trench gates.
These and other features and advantages of the present invention will be set forth in the detailed description of illustrative embodiments which follows, in conjunction with the accompanying drawings.
Drawings
The foregoing features, technical features, advantages and embodiments are further described in the following detailed description of the preferred embodiments, which is to be read in connection with the accompanying drawings.
The embodiments of the invention described with reference to the following figures, given as examples only, are non-limiting and non-exhaustive. Unless otherwise specified, reference numbers used in the figures identify identical elements in the various views.
FIGS. 1A and 1B are cross-sectional views of at least a portion of a vertical double diffused metal oxide semiconductor field effect transistor (VDMOSFET) device including an on-resistance and a parasitic gate-to-drain capacitance illustration, respectively;
FIGS. 2A to 2C are cross-sectional views of at least a portion of a trench-gate MOSFET device showing reduced on-resistance and illustrating some of the effects of variation in depth of the body region in the device;
FIGS. 3A through 3C are at least a portion of cross-sectional views of a split trench WMOSFET device showing reduced parasitic gate-to-drain capacitance and increased off-state blocking voltage and illustrating some of the effects of body region depth variation in the device;
FIG. 4A shows a perspective view of at least a portion of a super-gated MOSFET device according to a comparative embodiment of the present invention;
FIG. 4B is a cross-sectional view of the super-gated MOSFET device along A-A' in FIG. 4A;
fig. 4C is a cross-sectional view of the super-gate MOSFET device shown in fig. 4B with an accumulation layer formed adjacent to the trench-gate structure;
FIG. 5 conceptually illustrates the relationship between the characteristic on-resistance, Rsp, and the breakdown voltage of three different types of MOSFET devices;
FIG. 6 shows a perspective view of at least a portion of a super-gated MOSFET device according to another comparative embodiment of the present invention;
FIGS. 7A to 7I are schematic cross-sectional views illustrating the fabrication of at least a portion of a super-gated MOSFET device of a comparative embodiment of the present invention shown in FIG. 4B;
FIG. 8 is a cross-sectional view of at least a portion of a super-gated MOSFET device having a gate structure with enhanced voltage blocking capability in a comparative embodiment of the present invention;
FIGS. 9A to 9L are schematic cross-sectional views of the fabrication of at least a portion of a super-gated MOSFET device of a comparative embodiment of the invention shown in FIG. 8;
FIG. 10 is a cross-sectional view of at least a portion of a super-gate MOSFET device with an enhanced source contact in a comparative embodiment of the present invention;
FIG. 11 is a graphical representation of the drain voltage as a function of time for a super-gated MOSFET device according to one or more comparative embodiments of the present invention as compared to a standard MOSFET device; and
fig. 12 is a graph illustrating the gate voltage of a super-gated MOSFET device according to one or more comparative embodiments of the invention as a function of time, as compared to a standard MOSFET device.
FIG. 13 illustrates a cross-sectional view of at least a portion of an exemplary super-gated MOSFET device having reduced gate coupling capacitance in accordance with one or more embodiments of the invention;
FIG. 14 illustrates a cross-sectional view of at least a portion of an exemplary capacitor including a trench structure;
FIG. 15 illustrates an electrical schematic diagram of at least a portion of an exemplary switching DC-DC voltage regulator circuit to which one or more embodiments of the present invention may be applied;
FIG. 16 illustrates a cross-sectional view of at least a portion of an exemplary capacitor according to one or more embodiments of the present invention, the capacitor including a trench structure as shown in FIG. 14, the trench structure being modified to provide increased capacitance; and
fig. 17 illustrates a cross-sectional view of at least a portion of an exemplary power structure including an exemplary super-gate MOSFET device integrated with an exemplary trench capacitor structure, in accordance with one or more embodiments of the present invention.
It will be appreciated that elements shown in the figures are for simplicity and clarity of illustration. In a commercially feasible embodiment, some elements that may be useful or necessary but are well known in the art may not be shown in order to facilitate a less obstructed view of these various embodiments.
Detailed Description
The principles of the present invention, as illustrated in one or more embodiments, will be described herein in connection with Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices and methods for fabricating LDMOS devices that enhance high frequency performance without significantly degrading power and linearity performance. It should be understood, however, that the present invention is not limited to the particular devices and/or methods illustratively set forth herein. Rather, those skilled in the art will readily appreciate that many modifications are possible in the embodiments in light of the teachings herein and that such modifications are within the scope of the invention as claimed. That is, the examples herein are not intended as, and should not be construed as, limitations of the present invention.
For the purposes of describing and protecting embodiments of the present invention, the term MISFET as may be used herein should be broadly construed to include any type of metal-insulator-semiconductor field-effect transistor (MISFET). For example, the term MISFET may include semiconductor field effect transistors (i.e., MOSFETs) that utilize an oxide material as the gate dielectric, as well as other semiconductor field effect transistors that do not use an oxide material. In addition, although the term "metal" is mentioned in the acronym MISFET and MOSFET, the MISFET and MOSFET also include a semiconductor field effect transistor in which a gate is formed of a non-metal material (e.g., polysilicon), in which case the MISFET and MOSFET may be used interchangeably.
While the overall fabrication methods and structures formed in the present invention are entirely new, certain individual processing steps required to implement one or more portions of the methods of one or more embodiments of the present invention may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tools. Such techniques and tools are well known to those of ordinary skill in the art. In addition, numerous prior publications describe numerous processing steps and tools for fabricating semiconductor devices, including, for example, the composite semiconductor handbook by P.H. Holloway et al: growth, Processing, characteristics and Devices (Handbook of Compound Semiconductors: Growth, Processing, Characterification, and Devices), Cambridge university Press, 2008; and Processing and Properties of Compound Semiconductors, academic Press, 2001, by Willardson et al, which is incorporated herein by reference. It is emphasized that although individual process steps are set forth herein, these steps are merely illustrative and that other equally suitable alternatives, which may be familiar to those skilled in the art, are also included within the scope of the present invention.
It will be appreciated that the various layers and/or regions illustrated in the figures are not necessarily drawn to scale. Furthermore, for economy of description, one or more of the semiconductor layers typically used in an integrated circuit device may not be shown in the illustrated figures. However, this does not mean that these semiconductor layers, which are not explicitly shown, are omitted in the actual integrated circuit device.
Fig. 1A illustrates a cross-sectional view of at least a portion of a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOSFET) device 100. The VDMOSFET device 100 includes a substrate 102, the substrate 102 can be formed of monocrystalline silicon that changes the conductivity (e.g., N-type or P-type) of the material by the addition of impurities or dopants (e.g., boron, phosphorus, arsenic, etc.). In the present conventional gate comparative example, the substrate 102 has an N conductive type, and thus may be referred to as an N-type substrate (N + SUB).
An epitaxial region 104 is formed on the upper surface of the substrate 102. In the present conventional gate comparative example, the epitaxial region 104 has an N conductivity type (N-EPI) by adding an impurity or a dopant. In the VDMOSFET device 100, the epitaxial region 104 serves as a lightly doped drift region of the device. BODY regions 106(P-BODY) having a P-type conductivity type in the present conventional gate comparative example are formed near the upper surface of the epitaxial region 104 and are laterally spaced apart from each other. The VDMOSFET device 100 also includes a source region 108 formed in at least a portion of each body region 106 and proximate an upper surface of the body region. Preferably, the source region 108 may be doped with impurities at a known concentration level using a conventional implantation process to selectively alter the conductivity of the material as desired. For example, the source region 108 is of N-type conductivity (N +). A heavily doped region 110, formed near the top surface of body region 106 and having the same conductivity type as body region 106 (e.g., P-type in this example), is laterally adjacent to a corresponding source region 108 to form a body region contact of VDMOSFET device 100. Each of the source regions 108 is electrically connected to a corresponding body region contact 110.
In a VDMOSFET structure, the substrate 102 serves as the drain region of the device. A drain contact 112 formed on the back side of substrate 102 provides an electrical connection to the substrate/drain 102.
A gate 114 is formed over at least a portion of the body region 106 between the source regions 108 and the epitaxial drift region 104. A thin oxide layer 116 (e.g., silicon dioxide, SiO) is formed under the gate 1142) As a gate oxide for electrically isolating the gate from the source region 108, body region 106 and epitaxial region 104 in the VDMOSFET device 100. Insulating spacers 118 are formed on the sides of gate 114 and gate oxide 116 to electrically isolate the gate from source region 108. As is well known to those skilled in the art,the bias applied to the gate forms a channel in the body region 106 under the gate for controlling current flow between the source region 108 and the substrate 102, which is the drain region.
The VDMOSFET device 100 adopts a planar gate structure on the surface of the device, and has the advantages of simple manufacturing process, good application reliability and the like. However, VDMOSFET designs also exhibit significant drawbacks, including having a high on-resistance and a large parasitic gate-to-drain capacitance (i.e., miller capacitance), which makes such devices unsuitable for high power, high frequency applications. Higher on-resistance RONMainly due to the body region (P-body) channel resistance RBODY(which may be referred to as MOSFET channel resistance), Junction Field Effect Transistor (JFET) channel resistance RJFETAnd an epitaxial drift region resistance REPIIn combination (i.e. R)ON＝RBODY+RJFET+REPI). Wherein R isEPIIs a major factor (in 100 volt devices, it accounts for the total on-resistance RONAbout fifty percent or more).
Fig. 1B is a cross-sectional view of at least a portion of the exemplary VDMOSFET device 100 of fig. 1A, illustrating a parasitic gate-to-drain capacitance (e.g., miller capacitance). As shown in fig. 1B, a large parasitic gate-drain capacitance CgdPrimarily due to the large overlap region between the gate 114 and the epitaxial drift region 104. This large parasitic gate-drain capacitance CgdThe components cause significant switching power losses in high frequency applications and are therefore undesirable.
Efforts have been made to reduce the on-resistance of VDMOSFET devices and thereby increase conductivity. In particular, it is desirable to increase the channel density of the VDMOSFET device 100 by reducing the lateral spacing of the body region 106. However, the junction field effect transistor effect resulting from narrower body region spacing increases the JFET resistance R between body regions 106JFETThereby offsetting the benefit of increasing channel density, it is always desirable to have a channel resistance R in the MOSFETBODYAnd JFET channel resistance RJFETTaking a trade between them. Also, while the JFET channel resistance can be reduced by increasing the doping concentration in the upper surface of the epitaxial region 104(JFET region), such a reduction in JFET channel resistance can also lead to undesirable device turn-off behaviorThe reduction of avalanche breakdown voltage in the state. In this regard, there is also an attempt to balance the positive charges in the N-type epitaxial drift region 104 with the negative charges in the P-type body region 106 using a charge balancing method to increase the doping concentration of the epitaxial drift region 104 and thereby reduce the drift region on-state resistance R in the off state of the deviceEPIHowever, for a given dimension, the doping concentration is limited to a particular level, typically below 1017/cm3Left and right.
Fig. 2A-2C are cross-sectional views of at least a portion of exemplary trench-gate MOSFET devices 200, 230, and 250, respectively, that exhibit reduced on-resistance and conceptually illustrate some of the effects of body region depth variations in the devices. Referring to fig. 2A, a trench-gate MOSFET device 200 includes a substrate 202, and the substrate 202 may be formed of monocrystalline silicon formed by adding impurities or dopants having an N conductivity type, and thus may be referred to as an N-type substrate (N + SUB).
An epitaxial region 204 is formed on the upper surface of the substrate 202. In this example, the epitaxial region 204 has an N conductivity type (N-EPI) by adding impurities or dopants. Similar to the VDMOSFET device 100 shown in fig. 1A, in the VDMOSFET device 200, the epitaxial region 204 serves as a lightly doped drift region of the device. BODY regions (P-BODY)206 having a P-type conductivity type in this embodiment are formed near the upper surface of epitaxial region 204 and are laterally spaced apart from each other. The MOSFET device 200 also includes a source region 208 formed in at least a portion of each body region 206 and proximate an upper surface of the body region. Preferably, the source region 208 may be doped with impurities at a known concentration level to have an N-type conductivity (N +) using a conventional implantation process. A heavily doped region 210 of P conductivity type is formed near the upper surface of body region 206 and laterally adjacent to a corresponding source region 208 to form a source contact for the MOSFET device 200. Each of the source regions 208 is electrically connected to a corresponding body region contact 210.
Similar to the VDMOSFET device 100 shown in fig. 1A, in this MOSFET device 200, the substrate 202 serves as the drain region of the device. A drain contact 212, preferably formed on the back side of substrate/drain 202, provides an electrical connection to substrate/drain 202.
The MOSFET device 200 further includes a trench gate 214, the trench gate 214 comprising polysilicon formed through the upper surface of the epitaxial region 204 between the body region 206 and the source region 208. Trench gate 214 may be fabricated by forming a channel (i.e., a trench) partially through epitaxial region 204 and between body region 206 and source region 208, and filling the channel with dielectric material 216. The dielectric material is preferably an oxide, such as silicon dioxide. Trench gate 214 is then formed partially through dielectric material 216, extending vertically and beyond source region 208 and body region 206. The thickness of the dielectric material 216 around the sidewalls of the trench gate 214 is preferably just enough to prevent direct electrical contact between the trench gate 214 and the adjacent source region 208 and body region 206.
In contrast to the planar gate design in the VDMOSFET device 100 shown in FIG. 1A, the trench-gate MOSFET device 200 is formed by eliminating the JFET resistance factor RJFETThe advantage of having a lower on-resistance is achieved. However, the parasitic gate-drain (Miller) capacitance CgdStill high. As shown in the exemplary trench MOSFET device 230 of fig. 2B, the gate-to-drain capacitance can be reduced slightly by increasing the thickness of the dielectric material 216 at the bottom of the trench. The trench MOSFET device 230 is substantially the same as the device 200 shown in fig. 2A, except that the depth of the body region 206 into the epitaxial drift region 204 is slightly reduced. Although device 230 reduces parasitic gate-drain capacitance CgdHowever, a weak point 232 is created between the bottom corner of the polysilicon trench gate 214 and the epitaxial region 204, which weak point 232 can lead to an undesirable reduction in the breakdown voltage of the device.
Further complicating this process of forming a channel within body region 206 is that the depth of the body region in epitaxial region 204 must be tightly controlled with respect to the depth of trench gate 214. The body region 206 cannot be too shallow because it would result in a weak spot 232 that is prematurely broken down at a high blocking voltage, as shown by the MOSFET device 230 shown in fig. 2B. Similarly, as shown in trench-gate MOSFET device 250 in fig. 2C, body region 206 cannot be too deep in epitaxial region 204 either, because this would increase the gate oxide thickness near the bottom of trench-gate 214, as indicated by thick oxide region 252 in fig. 2C, as opposed to what would be desirable. The thick oxide region 252 in the trench-gate MOSFET device 250 reduces gate control over the channel formed in the body region 206, making the device difficult to turn on; that is, MOSFET device 250 will exhibit an undesirable increase in the threshold voltage of the device.
Fig. 3A-3C are cross-sectional views of at least a portion of exemplary split trench gate MOSFET devices 300, 330, 350, respectively. As shown in fig. 3A, the split trench gate MOSFET device 300 includes a substrate 302, and the substrate 302 may be formed of single crystal silicon formed by adding impurities or dopants having an N conductivity type, and thus may be referred to as an N-type substrate (N + SUB). An epitaxial region 304 is formed on the upper surface of the substrate 302. In this example, the epitaxial region 304 has an N conductivity type (N-EPI) by adding impurities or dopants. Similar to the VDMOSFET device 100 shown in fig. 1A and the trench-gate MOSFET device 200 shown in fig. 2A, in the MOSFET device 300, the epitaxial region 304 serves as a lightly doped drift region of the device. BODY regions (P-BODY)306 having a P-type conductivity type in this conventional gate comparative example are formed near the upper surface of epitaxial region 304 and are laterally spaced apart from each other. The MOSFET device 300 also includes a source region 308 formed in at least a portion of each body region 306 and proximate an upper surface of the body region. Preferably, the source region 308(N +) having an N-type conductivity may be formed using a conventional implantation of N-type impurities. In this embodiment, heavily doped regions 310 of P conductivity type are formed near the upper surface of body regions 306 laterally adjacent to corresponding source regions 308 to form body region contacts for MOSFET device 300. Thus, each of the source regions 308 is electrically connected to a corresponding body region contact 310.
In this split trench-gate MOSFET device 300, the substrate 302 serves as the drain region of the device, similar to the VDMOSFET device 100 shown in fig. 1A and the trench-gate MOSFET device 200 shown in fig. 2A. A drain contact 312 formed on the back side of the substrate/drain 302 provides an electrical connection to the substrate/drain 302.
The MOSFET device 300 further includes a dielectric trench 314 filled with a dielectric material (e.g., silicon dioxide), the dielectric trench 314 extending vertically in the epitaxial region 304 and between the body region 306 and the source region 308. A trench gate 316, which may comprise polysilicon, is formed in the dielectric trench 314, the depth of the trench gate 316 being just below the bottom of the body region 306. A shield gate 318 is also formed in trench 314 vertically below the trench gate 316. The shield gate 318 is electrically isolated from the trench gate 316 and the epitaxial region 304 by the dielectric material in the dielectric trench 314. In this comparative example, trench gate 316 is slightly wider than shield gate 318 so that the shield gate is surrounded by a thicker layer of dielectric material than the trench gate. Preferably, shield gate 318 is connected to source region 308.
In the MOSFET device 300, the shield gate 318 helps to reduce the parasitic gate-to-drain capacitance CgdAnd the off-state blocking voltage is increased. However, any improvement provided by such split trench gate MOSFET designs is only applicable in the off-state of the device, i.e., there is substantially no improvement in the on-state performance where the maximum doping concentration is determined by the required breakdown voltage of the device. A similar difficulty is faced by the split trench gate design in precisely controlling the depth and thickness of the body region 306.
For example, a split trench gate MOSFET device 330 with shallow body regions 306 as shown in fig. 3B. As previously described in connection with fig. 2B, the shallow body region 306 in the MOSFET device 330 can create a weak point region 332 near the bottom corner of the trench gate 316, which can lead to premature device breakdown at high blocking voltages.
Also, fig. 3C shows a split trench-gate MOSFET device 350 with deep body regions 306 such that the bottom of the body regions extend below the bottom of the trench-gate 316. As previously described in connection with fig. 2C, the deep body region 306 in the MOSFET device 350 forms a thick oxide region 352 near the bottom corner of the trench gate 316, and the thick oxide region 352 reduces gate control of the channel formed in the body region 306, thereby increasing the threshold voltage of the device and making it difficult to turn on the device.
As shown in one or more comparative examples, the present inventors have attempted to exploit the beneficial properties of planar gate and trench gate structures to provide MOSFET devices having what are referred to herein as super-gate structures, which advantageously achieve enhanced high frequency performance without significantly degrading power and linearity performance in the device. Fig. 4A and 4B show a perspective view and a cross-sectional view, respectively, of at least a portion of a supergate MOSFET device 400 of the present invention as a comparative example (see CN112614891A for details).
The MOSFET device 400 includes a substrate 402, the substrate 402 may be formed of single crystal silicon (e.g., having a crystal orientation of < 100 > or < 111 >) that is formed to a desired conductivity type (e.g., N-type or P-type) and doping level by the addition of impurities or dopants (e.g., boron, phosphorus, arsenic, antimony, etc.). The P-type substrate may be formed by adding a specified concentration level (e.g., about 10 per cubic centimeter) to the substrate material14To about 1018Individual atoms) or dopants (e.g., group III elements such as boron), for example, by diffusion or implantation processes, as desired to alter the conductive properties of the material. In other embodiments, an N-type substrate may be formed by adding a specified concentration level of an N-type impurity or dopant (e.g., a group V element such as phosphorus) to the substrate material. In this embodiment, the substrate 402 is doped to have an N-type conductivity type and thus may be referred to as an N-type substrate (N + SUB). Similar other materials may be used to form substrate 402 such as, but not limited to, germanium, gallium arsenide, silicon carbide, gallium nitride, indium phosphide, and the like.
An epitaxial region 404 is formed on the upper surface of the substrate 402. In the present supergate comparative example, the epitaxial region 404 has an N conductivity type (N-EPI) by adding impurities or dopants, and similarly, P-type epitaxy (e.g., by adding P-type dopants) is also contemplated. Similar to the VDMOSFET device 100 shown in fig. 1A and the trench-gate MOSFET device 200 shown in fig. 2A, in the MOSFET device 400, the epitaxial region 404 serves as a lightly doped drift region of the device. BODY regions (P-BODY)406 having a P-type conductivity type in this embodiment are formed adjacent to the upper surface of the epitaxial region 404 and are laterally spaced apart from each other. Body region 406 in this embodiment may be formed by implanting P-type impurities (e.g., boron) into designated areas of epitaxial region 404 using standard Complementary Metal Oxide Semiconductor (CMOS) fabrication techniques. Phase (C)For the doping level of the substrate, body region 406 is preferably more heavily doped, e.g., about 5 × 1016One atom per cubic centimeter (cm)3) To about 1X 1018Atom/cm3. In one or more alternative embodiments employing P-type epitaxial regions, body region 406 may include an N-type well formed using similar CMOS fabrication techniques.
The MOSFET device 400 also includes source regions 408 formed in at least a portion of each body region 406 and proximate to an upper surface of the body region. Preferably, the source regions 408 are doped with an impurity of opposite conductivity type to the body regions 406. In this supergate comparative example, the source region 408 is of N-type conductivity (N +). In this comparative supergate example, heavily doped regions 410 of P-type conductivity are formed adjacent the upper surface of body regions 406 and laterally adjacent the corresponding source regions 408, thereby forming body region contacts for the MOSFET device 400. A respective source (S) electrode 412 electrically connects each source region 408 to a corresponding body region contact 410.
Similar to the VDMOSFET device 100 shown in fig. 1A, in this MOSFET device 400, the substrate 402 serves as the drain region of the device. A drain (D) electrode 414 is preferably formed on the back of substrate/drain 402, which provides an electrical connection to the substrate/drain. Unlike a standard lateral MOSFET device in which both the drain and source electrodes are formed on the top surface of the device, the drain contact 414 of the MOSFET device 400 is formed on the bottom surface of the device opposite the source electrode 414, i.e., the drain electrode 414 and the source electrode 412 are distributed on opposite surfaces in the vertical direction of the MOSFET device 400.
The MOSFET device 400 also includes a gate structure that includes at least two portions, a planar gate (G1)416 and a trench gate (G2) 418. In the illustration of the supergate comparative example, two planar gates 416 are disposed on either side of trench gate 418. The planar gate 416 and the trench gate 418 are preferably formed in a comb-like (stripe-like) structure physically separated from each other even though the planar gate and the trench gate are electrically connected at one or both ends of the stripe-like structure thereof (not shown in the drawings, but are well-defined). In one or more alternative embodiments, planar gate 416 and trench gate 418 may form a contiguous gate structure that functions as both a planar and trench gate, as described in further detail below in conjunction with fig. 6.
In one or more supergate comparative examples, a trench gate 418, which may comprise polysilicon, is formed substantially vertically through the upper surface of the epitaxial region 404 between the body region 406 and the source region 408, such that there is one source region 408 on both sides of the trench gate 418. More specifically, trench gate 418 may be fabricated by opening (e.g., trenching or trenching) partially through epitaxial region 404 and between body region 406 and source region 408 and filling the opening with dielectric material 420. In one or more supergrid comparative examples, the dielectric material 420 is an oxide, such as silicon dioxide, although the invention is not limited to any particular electrically insulating material. The trench gate 418 is then formed partially through the dielectric material 420 and extends vertically further below the source regions 408 and body regions 406. Thus, the dielectric material 420 electrically isolates the trench gate 418 from the surrounding epitaxial region 404, thereby preventing direct electrical contact between the trench gate 418 and the adjacent source region 408 and body region 406, and thus the dielectric material 420 may be referred to as a trench gate oxide layer.
In one or more embodiments, each planar gate 416 is disposed on an upper surface of epitaxial region 404, which overlaps at least a portion of a corresponding body region 406. A dielectric layer 422 is formed between each planar gate 416 and the upper surface of body region 406 and epi region 404 to electrically isolate planar gate 416 from the body region and epi region, and thus may be referred to as a planar gate oxide. Although not explicitly shown in fig. 4A, dielectric spacers 424 are preferably formed on the sidewalls of planar gate 416 and a portion of the sidewalls of trench gate 418 that extends above the upper surface of epitaxial layer 404, as shown in fig. 4B. As shown in fig. 4B, the gate sidewall spacers 424 electrically isolate the planar gate from the trench gate and electrically isolate the planar gate 416 from the corresponding source electrode 412.
With continued reference to fig. 4B, the MOSFET device 400 further includes a first gate electrode 426 electrically connected to the planar gate 416, and a second gate electrode 428 electrically connected to the trench gate 418. Gate electrodes 426 and 428 may be implemented by forming a metal silicide layer on at least a portion of the upper surface of gates 416 and 418, respectively. As known to those skilled in the art, in a gate silicidation process, a metal film (e.g., titanium, tungsten, platinum, cobalt, nickel, etc.) is deposited on an upper surface of a polysilicon gate, and a reaction between the deposited metal film and silicon in the polysilicon gate occurs through annealing, eventually forming a metal silicide contact.
When a positive bias voltage exceeding the threshold voltage is applied to the N-channel MOSFET device, a channel is formed in the body region 406 under the planar gate, for example by applying a positive voltage between the planar gate 416 and the corresponding source region 408, thereby turning on the MOSFET device 400. Meanwhile, since the trench gate 418 is electrically connected to the planar gate 416, a positive bias will be applied to the trench gate, thereby forming a strong accumulation layer 430 with majority carriers (e.g., electrons in this embodiment) at the surface of the epitaxial region 404 near the trench gate oxide layer 420, as shown in fig. 4C. This accumulation layer 430 advantageously increases the conductance of the MOSFET device 400, which enables the device to achieve very low on-resistance, for example, on the order of two milliohms-mm (2m Ω -mm) at a blocking voltage rating of 30 volts2). As will be described below, the super-gate MOSFET device 400 achieves a substantial performance improvement over conventional planar gate and trench gate devices.
FIG. 5 conceptually illustrates the characteristic on-resistance R of three different types of MOSFET devicessp(ohm-cm) and breakdown voltage (volts). Specifically, reference numeral 502 denotes the characteristic on-resistance R of a trench-gate MOSFET device consistent with the trench-gate MOSFET device 200 shown in fig. 2AspProportional relationship with breakdown voltage. Reference numeral 504 represents the proportional relationship between the characteristic on-resistance Rsp and the breakdown voltage of a split trench-gate MOSFET device consistent with the split trench-gate MOSFET device 300 shown in fig. 3A. Reference numeral 506 designates a characteristic on-resistance R of a super-gated MOSFET device (e.g., the super-gated MOSFET device 400 shown in FIG. 4A) formed in accordance with one or more comparative embodiments of the present inventionspProportional relationship with breakdown voltage. Ideally, a MOSFET device would exhibit a high breakdown voltage and low characteristic on-resistance, however,in practice, the device characteristics are often contradictory, that is, a MOSFET device with very low on-resistance will also have a very low breakdown voltage, and vice versa, as are the trench-gate and split-trench-gate MOSFET devices shown at 502 and 504, respectively.
As shown in fig. 5, the super-gate comparative example formed according to the present invention, super-gate MOSFET device 506, has at least two distinct advantages over trench-gate MOSFET device 502 or split trench-gate MOSFET device 504. First, the characteristic on-resistance R is shown compared to 502 and 504spThe slope of the proportional relationship 506 with the breakdown voltage is significantly reduced, i.e., the super MOSFET device has a significantly smaller characteristic on-resistance than a trench-gate MOSFET device or a split trench-gate MOSFET device having the same rated breakdown voltage. Thus, the size of the chip can be scaled down in proportion to the chip size, further resulting in a significant reduction in parasitic gate capacitance and gate-drain capacitance.
Typically, the capacitance value C of the parallel plate capacitance is determined according to the following equation:
Figure BDA0003416190290000091
where ε 0 is the absolute permittivity (i.e., the vacuum permittivity ε 0 is 8.854 × 10-12F/m, ε r is the relative permittivity of the dielectric or dielectric material between the parallel plates, A is the surface area of one side of each parallel plate, and d is the distance between the parallel plates (i.e., the thickness of the dielectric material between the parallel plates). The surface area of one or both parallel plates of the parasitic gate capacitance and/or parasitic gate-to-drain capacitance can be reduced by reducing the chip size.
With continued reference to fig. 5, a second significant advantage of the comparative example super-gated MOSFET device of the present invention, as shown by the trapezoidal shape labeled 506, is that the super-gated MOSFET device is capable of adjusting the characteristic on-resistance during device operation, whereas conventional MOSFET devices have a fixed characteristic on-resistance. This is primarily due to the fact that in conventional MOSFET designs, the doping concentration, and its associated carrier concentration, is fixed after device fabrication is complete. In contrast, in a super-gate MOSFET device according to one or more embodiments of the present invention, the carrier concentration is not fixed, but can be conveniently adjusted depending on the bias applied to the trench-gate structure. This provides a number of benefits including greater flexibility in device design, a wider process window, and greater reliability in the operation of super-gated MOSFET devices.
Fig. 6 is a perspective view of at least a portion of an exemplary super-gated MOSFET device 600 according to another comparative example of the present invention. More specifically, the super-gate MOSFET device 600 is similar to the exemplary super-gate MOSFET device 400 shown in fig. 4A and 4B, except that the MOSFET device 600 includes a simplified gate design incorporating a planar gate (416 in fig. 4B) and a trench gate (418 in fig. 4B) that form a T-shaped gate 602 with both planar gate and trench gate functionality in the MOSFET device 600. Specifically, the gate 602 includes a planar gate portion 604 and a trench gate portion 606 as a connected structure.
The trench gate portion 606 is located between the two body regions 406 and extends at least partially vertically in the epitaxial region 404. The trench-gate portion 606 in the supergate comparative embodiments of the present invention is not limited to any particular size, but the depth of the trench-gate portion 606 is preferably about 1-2 microns (μm). The planar gate portion 604 begins at the trench gate portion 606 and extends in two opposite lateral directions (i.e., horizontal directions) along the upper surfaces of the epitaxial region 404 and the body region 406 to the edge of the corresponding source region 408. An insulating layer 608 is formed under the gate 602 to electrically isolate the gate from adjacent structures and regions. Preferably, dielectric spacers 610 are disposed on sidewalls of the gate 602 to prevent electrical contact between the gate and the source electrode 412.
The planar gate and trench gate portions 604 and 606 preferably operate in the same manner as the planar gate 416 and trench gate 418, respectively, in the example MOSFET device 400 in fig. 4 b. More specifically, by applying a gate bias signal between the gate 602 and the source region 408 that is greater than the threshold voltage of the MOSFET device 600, each planar gate portion 604 will induce the formation of a channel in the corresponding body region 406 directly beneath the planar gate portion; the channel is fundamentally closed when the applied gate bias signal is below the device threshold voltage. At the same time, the applied gate bias signal will cause trench-gate portion 606 to form a strongly accumulating layer 612 with the majority of carriers and the profile of the trench-gate portion near gate oxide 608. As previously described, the strong accumulation layer 612 can increase the conductance of the MOSFET device 600, thereby decreasing the on-resistance of the device, even though there is only a narrow space between the body regions 406. Connecting the gate 602 to the source electrode 412 closes the channel in the body region 406, thereby turning off the MOSFET device 600.
By way of example only, and not limitation, fig. 7A-7I illustrate cross-sectional views of an exemplary fabrication process of at least a portion of a super MOSFET device of a comparative embodiment of the present invention in fig. 4B.
Referring to fig. 7A, the exemplary fabrication process begins with a substrate 702, and in one or more embodiments, the substrate 702 comprises single crystal silicon or other alternative semiconductor materials, such as, but not limited to, germanium, silicon carbide, gallium arsenide, gallium nitride, and the like. In the illustrative embodiment, the substrate 702 is doped with an N-type impurity or dopant (e.g., phosphorus, etc.) to form an N conductivity type substrate (N + SUB). The use of a P conductivity type substrate is also contemplated in embodiments of the present invention. The substrate 702 is preferably cleaned and surface treated.
An epitaxial layer 704 is then formed on the upper surface of the substrate 702, for example, by an epitaxial growth process. In one or more embodiments, the epitaxial layer has an N conductivity type (N-EPI), although similar P conductivity type epitaxial layers are also contemplated. The doping concentration of epitaxial layer 704 is preferably lower than the doping concentration of substrate 702.
As shown in fig. 7B, a hard mask layer 706 is formed on the surface of the epitaxial layer 704. In one or more embodiments, the hard mask layer 706, which may comprise silicon nitride, is preferably formed using a standard deposition process. The hard mask layer 706 is then patterned (e.g., using standard photolithography and etching) and etched to form a trench 708 that is at least partially in the epitaxial layer 704. In one or more supergate contrast embodiments, Reactive Ion Etching (RIE) may be used to form the trench 708. A first dielectric layer 710 is then formed on the inner walls (e.g., sidewalls and bottom) of the trench 708, as shown in fig. 7C, which first dielectric layer 710 may be an oxide layer in one or more embodiments. Although the supergate comparative embodiments of the present invention are not limited to any particular dielectric material, in one or more embodiments, the first dielectric layer 710 comprises silicon dioxide formed using a dry or wet oxidation process. This first dielectric layer 710 will form the gate oxide (e.g., 418 in fig. 4A) of the trench gate in the super-gate MOSFET device of this example.
Referring now to fig. 7D, the hard mask layer (706 in fig. 7C) is removed, for example, by using a wet or dry etch process, such as a chemical or plasma etch. A second dielectric layer 711, which in one or more embodiments can be an oxide layer, is then formed on the upper surface of epitaxial layer 704. This second dielectric layer 711 will form the gate oxide (e.g., 416 in fig. 4A) of the planar gate of the super-gate MOSFET device. The first and second dielectric layers 710, 711 are typically formed by a chemical reaction between oxygen and silicon driven by a high temperature environment (e.g., about 800 degrees celsius (° c) to 1200 ℃), yielding silicon dioxide; however, even at room temperature, a thin layer (e.g., about 1-3 angstroms) may form in the ambient environment
Figure BDA0003416190290000111
) Of (4) a natural oxide. To grow thicker oxides in a controlled environment, several known methods can be used, such as oxidation by in situ generation of steam or a remote plasma source (e.g., Remote Plasma Oxidation (RPO)).
Next, as shown in fig. 7E, a gate structure including a planar gate 712 and a trench gate 714 is formed. The planar and trench gates 712, 714 preferably comprise polysilicon and are formed using standard deposition processes, then patterned (e.g., using standard photolithography and etching) and etched. In the present supergate comparative example, one planar gate 712 is disposed on each side of the trench gate 714. Although not explicitly shown in fig. 7E, the planar gate 712 and the trench gate 714 are preferably formed in a comb-like (i.e., stripe-like) structure separated from each other in a structure in which the planar gate and the trench gate are electrically connected at one end or (opposite) both ends of the stripe-like structure. In one or more alternative embodiments, planar gate 712 and trench gate 714 may form a contiguous structure having the functionality of a planar gate and a trench gate as described previously in connection with fig. 6.
As shown in fig. 7F, the exposed portions of the second dielectric layer (711 in fig. 7E) at the upper surface of epitaxial layer 704 (i.e., the portions of the second dielectric layer not covered by planar gate 712 and trench gate 714) are removed using, for example, a standard selective etch process. A self-aligned body region 716 is then formed in the epitaxial layer 704 near the upper surface of the epitaxial layer. In the present exemplary super-gate contrast embodiment, body region 716 is preferably formed by implanting a specified concentration level of P-type dopants into epitaxial layer 704, followed by a thermal treatment (e.g., annealing) to drive the dopants into the epitaxial layer.
Alternatively, in the super-gate contrast embodiment shown in fig. 7F, the implant region 718 is preferably formed in the epitaxial layer 704 near the upper surface of the epitaxial layer and between the body region 716 and the trench gate 714. In one or more supergate comparative examples, the implant region 718 is formed by implanting a specified concentration level of N-type dopants into the epitaxial layer 704 between the planar gate 712 and the trench gate 714. During the implantation, the planar gate and the trench gate are used as masks. Preferably, the implant region 718 is configured to increase an N-type doping concentration level at an edge of a channel formed in the body region 716, thereby reducing an on-resistance of the MOSFET device. The implant region 718 may also confine the channel region under the gate 712, thereby improving high frequency performance. Although embodiments of the present invention are not limited to any particular doping concentration, in one or more embodiments, the preferred doping concentration of the implanted regions 718 is approximately 1 x 1016To 1X 1018One atom per cubic centimeter.
As shown in fig. 7G, dielectric spacers 720 are then formed on the sidewalls of the planar gate 712 and the trench gate 714. Although the invention is not limited to any particular dielectric material, the dielectric sidewalls 720 may comprise silicon dioxide or silicon nitride in one or more supergate contrast embodiments. An etch process is then used to create the required patterning, forming source region contacts (e.g., N-type) and body region pick-up contacts (e.g., P-type) in the device.
In fig. 7H, source regions 722 are formed in the corresponding body regions 716 near the top surface of the body regions and the self-aligned planar gate 712. In the present exemplary comparative embodiment, the source region 722 having the N conductive type is formed using, for example, a standard implantation process (e.g., ion implantation). In this comparative embodiment, a heavily doped region 724 of P conductivity type is formed near the upper surface of the body region 716 and laterally adjacent to the corresponding source region 722 to form the body region contact of the super-gate MOSFET device. Thus, each source region 722 is electrically connected to a respective body region contact 724.
Referring now to fig. 7I, metal silicide contacts 726 are formed in the source regions 722 and metal silicide contacts 728 and 730 are formed in the planar gate and trench gate, respectively, using a standard front-end silicidation process. It is known that during silicidation, a layer of metal is deposited on the upper surface of the wafer and then subjected to a thermal treatment (e.g. thermal annealing) to form an alloy (metal silicide) where the metal contacts the exposed silicon. Unreacted metal is then removed using, for example, a standard etch process to form a low resistance silicide at the source and gate contacts. The front side interconnect and passivation is then performed with metal (e.g., aluminum, etc.), and dielectric deposition and patterning is performed in a front-end-of-line (FEOL) process. After the FEOL process, the wafer is flipped for backside thinning (e.g., using chemical mechanical polishing, CMP) and backside metallization to form the drain contact 732 for the super-gate MOSFET device.
Fig. 8 is a cross-sectional view of at least a portion of a super-gated MOSFET device 800 in a comparative embodiment of the invention. The MOSFET device 800 is similar to the super-gated MOSFET device 400 shown in fig. 4B, except that its gate structure is configured to have enhanced voltage blocking capability. As shown in fig. 8, a super-gate MOSFET device 800 includes a substrate 802, which substrate 802 may be formed of single crystal silicon modified by the addition of impurities or dopants (e.g., boron, phosphorus, arsenic, antimony, etc.) having the desired conductivity type (N-type or P-type) and doping levels. In the present exemplary embodiment, the substrate 802 is doped to have an N conductive type, and thus may be referred to as an N type substrate (N + SUB). Other materials are also contemplated for forming substrate 802 such as, but not limited to, germanium, gallium arsenide, silicon carbide, gallium nitride, indium phosphide, and the like.
An epitaxial region 804 is formed on the upper surface of the substrate 802. In the present supergate comparative example, the epitaxial region 804 is denatured by adding an impurity or dopant having an N conductivity type (N-EPI), although a P-type epitaxy is also contemplated. In the MOSFET device 800, the epitaxial region 804 serves as a lightly doped drift region of the device. Two BODY regions (P-BODY)806, which in this embodiment have a P-type conductivity type, are formed near the upper surface of epitaxial region 804 and are laterally spaced apart from each other. The body region 806 in this embodiment may be formed by implanting P-type impurities (e.g., boron) into designated areas of the epitaxial region 804 using standard Complementary Metal Oxide Semiconductor (CMOS) fabrication techniques.
A source region 808 is formed in at least a portion of the corresponding body region 806 and proximate to an upper surface of the body region. Preferably, in this exemplary MESFET device 800, the source regions 808 have an N-type conductivity. In this supergate comparative embodiment, heavily doped regions 810 formed near the upper surface of body regions 806 and laterally adjacent to corresponding source regions 808 have a P-type conductivity, thereby forming body region contacts for the MOSFET device 800. A respective source (S) electrode 812 electrically connects each source region 808 to a corresponding body region contact 810.
In the super-gated MOSFET device 800, the substrate 802 serves as the drain region of the device. Accordingly, a drain (D) electrode 814 is preferably formed on the back side of the substrate/drain 802, which provides an electrical connection to the substrate/drain, for example, in a back-end-of-line (BEOL) process. Similar to the MOSFET device 400 shown in fig. 4B, the drain electrode 814 is formed on the back side of the MOSFET device 800 on the side opposite to the source electrode 812 formed on the upper/front surface of the device, that is, the drain electrode 814 and the source electrode 812 are distributed on two surfaces opposite in the vertical direction of the MOSFET device 800.
The MOSFET device 800 also includes a gate structure that includes at least two portions, a planar gate (G1)816 and a trench gate (G2) 818. In the illustration of the inventive supergate comparative example, two planar gates 816 are disposed on two sides of the trench gate 818, respectively. The planar gate 816 and the trench gate 818 are preferably formed in a comb-like (stripe-like) structure separated from each other, i.e. the planar gate and the trench gate are electrically connected at one or both ends of their stripe-like structure (not explicitly shown, but implicitly implied). In one or more alternative embodiments, planar gate 816 and trench gate 818 may form a contiguous gate structure that functions as both a planar and a trench gate.
In one or more embodiments, the trench gate 818, which may comprise polysilicon, may be formed generally vertically through the upper surface of the epitaxial region 804 between the body regions 806 and also between the source regions 808, such that there is one source region 808 on both sides of the trench gate 818. The MOSFET device 800 further includes a dielectric layer 820 that electrically isolates the trench-gate 818 from the surrounding epitaxial region 804, thereby preventing direct electrical contact between the trench-gate 818 and the adjacent source 808 and body 806 regions. In one or more supergate comparative embodiments, the dielectric layer 820 comprises an oxide, such as silicon dioxide, which may be referred to as a trench gate oxide, although the approach is not limited to any particular electrically insulating material.
In one or more comparative embodiments, each planar gate 816 is disposed on the upper surface of the epitaxial region 804, at least a portion of which overlaps a corresponding body region 806. A second dielectric layer 822 is formed between each planar gate 816 and the upper surface of body region 806 and epitaxial region 804 to electrically isolate the planar gate 816 from the body region and epitaxial region, and thus may be referred to as a planar gate oxide. Dielectric spacers 824 are preferably formed on the sidewalls of planar gate 816 and the sidewalls of trench gate 818. The gate sidewall spacers 824 electrically isolate the planar gate from the trench gate and electrically isolate the planar gate 816 from the corresponding source electrode 812.
With continued reference to fig. 8, the super-gate MOSFET device 800 further includes a first gate electrode 826 connected to the planar gate 816 and a second gate electrode 828 connected to the trench gate 818. Gate electrodes 826 and 828 may be implemented by forming a metal silicide layer on at least a portion of the upper surfaces of gates 816 and 818, respectively.
To optimize the voltage blocking capability of the super-gate MOSFET device 800, the trench-gate structure is preferably configured with a trench-gate oxide layer 820, with the trench-gate oxide layer 820 being thicker in a lower portion 830 of the trench-gate structure than in an upper portion 832 of the trench-gate structure. Although the super-gate comparative embodiments of the present invention are not limited to any particular dimensions, in one or more of the super-gate comparative embodiments, the thickness of the trench gate oxide 820 at the upper portion 832 of the trench-gate structure is about 10-50nm, while the thickness of the trench gate oxide at the lower portion 830 of the trench-gate structure is about 50-500 nm. The planar gate oxide 822 under each planar gate (G1)816 is preferably around 5-50 nm. A method of configuring a super-gate MOSFET device having a trench-gate structure is illustratively described below in conjunction with fig. 9A through 9L.
Specifically, fig. 9A to 9L are schematic cross-sectional views of a process for fabricating at least a portion of the super-gated MOSFET device 800 in the embodiment shown in fig. 8 of the comparative super-gate of the present invention shown in fig. 8. Referring to fig. 9A, the exemplary fabrication process begins with a substrate 902, which in one or more embodiments, the substrate 902 comprises single crystal silicon or other alternative semiconductor materials, such as, but not limited to, germanium, silicon carbide, gallium arsenide, gallium nitride, and the like. In the illustrative embodiment, the substrate 902 is doped with an N-type impurity or dopant (e.g., phosphorous, etc.) to form an N conductivity type substrate (N + SUB). The use of P conductivity type substrates is also contemplated in the supergate comparative embodiments of the present invention. The substrate 902 is preferably cleaned and surface treated.
An epitaxial layer 904 is then formed on the upper surface of the substrate 902, for example, by an epitaxial growth process. In one or more embodiments, the epitaxial layer has an N conductivity type (N-EPI), although similar P conductivity type epitaxial layers are also contemplated. The doping concentration of epitaxial layer 904 is preferably lower than the doping concentration of substrate 902.
As shown in fig. 9B, a hard mask layer 906 is formed on the surface of epitaxial layer 904. In one or more embodiments, the hard mask layer 906, which may comprise silicon nitride, is formed, preferably using a standard deposition process. The hard mask layer 906 is then patterned using, for example, standard photolithography and etching, after which a trench 908 is formed at least partially in the epitaxial layer 904 using, for example, an etching process; in one or more supergate contrast embodiments, the trench 908 may be formed using Reactive Ion Etching (RIE). The hard mask layer 906 is then removed, for example, by etching, as shown in FIG. 9 c.
The first two steps in the fabrication of the super-gated MOSFET device 800 are the same as the fabrication of the exemplary super-gated MOSFET device 400 depicted in fig. 4B and depicted in fig. 7A and 7B. Referring now to fig. 9D, an insulating layer 910 is formed in the trench 908 and on at least a portion of the upper surface of the epitaxial layer 904. In one or more embodiments, the insulating layer 910 includes an oxide (e.g., silicon dioxide) grown or deposited in the trenches 908 and on the upper surface of the epitaxial layer 904. Then, as shown in fig. 9E, an etch-back process, such as a wet etch, is used to remove the insulating layer 910 on the top surface of the epitaxial layer 904 and the insulating layer 910 on the partial sidewall in the trench 908, allowing a portion of the insulating layer 910 to remain at the bottom of the trench, and as shown in fig. 9F, the wafer is subjected to a thermal oxidation process to form a thin conformal gate oxide layer 912. Although the inventive supergate comparative example is not limited to any particular dimensions, in one or more embodiments, the thickness of the oxide layer 912 on the upper surface of the epitaxial layer 904 and on the sidewalls of the trench 908 is about 30-50 nm.
As shown in fig. 9G, in one or more supergate contrast embodiments, an anisotropic etch (e.g., RIE) is used to form a narrow trench 914 in insulating layer 910. Then, as shown in fig. 9H, a thin gate oxide layer 916 (e.g., about 30-50nm) is grown on the upper portion of the sidewalls of the first trench 908 and on the upper surface of the epitaxial layer 904. Next, as shown in fig. 9I, a gate structure including a planar gate 918 and a trench gate 920 is formed. Each planar and trench gate 918, 920 preferably comprises polysilicon and is formed using standard deposition processes, then patterned (e.g., using standard photolithography and etching) and etched. In this embodiment, two planar gates 918 are disposed on two sides of the trench gate 920. Although not explicitly shown in fig. 9I, the planar gate 918 and the trench gate 920 are preferably formed in a comb-like (i.e., stripe-like) structure separated from each other in a structure in which the planar gate and the trench gate are electrically connected at one end or (opposite) both ends of the stripe-like structure.
Referring now to fig. 9J, the exposed portions of the gate oxide (916 in fig. 9I) located on the upper surface of the epitaxial layer 904 (i.e., the portions of the gate oxide not covered by the planar gate 918 and the trench gate 920) are removed using, for example, a selective etching process. A self-aligned body region 922 is then formed in the epitaxial layer 904 near the upper surface of the epitaxial layer. In the present exemplary embodiment, body region 922 is preferably formed by implanting a prescribed concentration level of P-type dopants into epitaxial layer 904, followed by a thermal process (e.g., annealing) to drive the dopants into the epitaxial layer.
Optionally, in the super-gate contrast embodiment shown in fig. 9J, the implant region 924 is preferably formed in the epitaxial layer 904 near the upper surface of the epitaxial layer and between the body region 922 and the trench gate 920. In one or more embodiments, the implant region 924 is formed by implanting a prescribed concentration level of N-type dopants into the epitaxial layer 904 between the planar gate 918 and the trench gate 920. During the implantation, the planar gate and the trench gate are used as masks. As with the implant region 718 shown in fig. 7F, the implant region 924 is preferably configured to increase the N-type dopant concentration level at the edge of the channel formed in the body region 922, thereby reducing the on-resistance of the MOSFET device. The implant region 924 may also confine the channel region under the gate 918, thereby improving high frequency performance. Although embodiments of the present invention are not limited to any particular doping concentration, in one or more embodiments, the preferred doping concentration of the implanted region 924 is approximately 1 x 1016To 1X 1018One atom per cubic centimeter.
As shown in fig. 9K, dielectric spacers 926 are then formed on the sidewalls of the planar gate 918 and the trench gate 920. Although the invention is not limited to any particular dielectric material, in one or more embodiments, the dielectric sidewall spacers 926 may comprise silicon dioxide. An etch process is then used to create the desired patterning, forming source region contacts (e.g., N-type) and body region contacts (e.g., P-type) in the device.
In fig. 9L, source regions 928 are formed in the corresponding body region 922 near the top surface of the body region and the self-aligned planar gate 918. In the present exemplary embodiment, source regions 928 having an N conductivity type are formed using, for example, a standard implantation process (e.g., ion implantation). In this supergate contrast embodiment, a heavily doped region 930 of P conductivity type is formed near the upper surface of body region 922 and laterally adjacent to a corresponding source region 928 to form the body region contact of the supergate MOSFET device. Thus, each source region 928 is electrically connected to a respective body region contact 930.
Standard front-end silicidation processes are used to form metal silicide contacts (812) in source regions 928 and to form metal silicide contacts (826 and 828) in planar gates 918 and trench gates 920, respectively. The front side interconnect and passivation is then performed with metal (e.g., aluminum, etc.), and dielectric deposition and patterning is performed in a front-end-of-Tine (FEOL) process. After the FEOL process, the wafer is flipped for backside thinning (e.g., CMP) and backside metallization to form drain contacts (814), thereby forming the super-gate MOSFET device 800 shown in fig. 8.
Fig. 10 is a cross-sectional view of at least a portion of another supergate MOSFET device of another comparative supergate embodiment of the invention having an enhanced source contact. The MOSFET device 1000 is identical to the super-gated MOSFET device 400 shown in fig. 4B, except for the source contact. Specifically, as shown in fig. 10, the super-gate MOSFET device 1000 includes an embedded source contact 1002 formed in the corresponding body region 406, the source contact 1002 being proximate to an upper surface of the body region and electrically connected to the adjacent source region 408. In one or more embodiments, each recessed source contact 1002 comprises a metal, such as tungsten, although embodiments of the invention are not limited to tungsten. Such a source contact structure provides a larger contact area between the source metal and the source region 408, thus advantageously reducing the resistance of the source contact. It is to be appreciated that such a source contact structure can be used with any of the super-gated MOSFET device structures described herein, as would be apparent to one of ordinary skill in the art based on this teaching. Although not explicitly shown in fig. 10, a metal suicide may also be formed around the embedded source contact 1002 using the same metal silicidation process as that used to form the planar gate and trench gate contacts 426 and 428, as will be apparent to those skilled in the art in view of this teaching.
The MOSFET devices of the comparative examples of the super-gate of the present invention achieved superior performance compared to standard MOSFET device designs. For example, fig. 11 is a graphical representation of drain voltage as a function of time for a super-gated MOSFET device (reference numeral 1102), such as the super-gated MOSFET device 400 shown in fig. 4B, as compared to a standard MOSFET device (reference numeral 1104). It can be seen from fig. 11 that the drain voltage of the new super-gate MOSFET device rises much faster over time (i.e., dv/dt) relative to the standard MOSFET device. This demonstrates the progress in switching speed of the new super-gate MOSFET device.
Fig. 12 is a graphical representation of gate voltage as a function of time for a super-gated MOSFET device (reference numeral 1202), such as the super-gated MOSFET device 400 shown in fig. 4B, as compared to a standard MOSFET device (reference numeral 1204). As can be seen in fig. 12, the gate voltage of a standard MOSFET device exhibits a severe perturbation 1206 when the device is off. This perturbation is mainly due to the large parasitic miller capacitance (C) associated with standard MOSFET devicesgd) Caused by the drain voltage coupling effect (as described above), which may exceed the threshold voltage of the device, thereby causing the device to mis-turn on. Misconduction of such devices can lead to short circuit conditions, particularly when MOSFET devices are used as low side transistors in power switching applications, such as DC-DC converters. By comparison, the super-gated MOSFET device represented by reference numeral 1202 appears to be very smallThe gate voltage disturbance is far lower than the threshold voltage of the device, so that the problem of misconduction of the device is well solved. Thus, the inventive super-gate MOSFET devices of each of the comparative embodiments have higher efficiency and higher reliability in higher frequency DC-DC converter applications than conventional MOSFET devices.
For the illustrative embodiment of the super-gate MOSFET device 1000 shown in fig. 10, the coupling capacitance between the planar gate G1 or the trench control gate G2 can be further reduced by recessing the trench gate G2 below the upper silicon surface of the device.
Fig. 13 illustrates, by way of example only and not by way of limitation, a cross-sectional view of at least a portion of an exemplary super-gate MOSFET device 1300 having reduced gate coupling capacitance in accordance with one or more embodiments of the invention. MOSFET device 1300 is similar to the illustrative MOSFET device 100 shown in fig. 10, except that the control gate is recessed below the upper surface of the device.
More specifically, referring to fig. 13, MOSFET device 1300 includes a control gate (G2) formed as a trench gate 1302. Trench gate 1302 may be fabricated in a manner consistent with trench gate 418 shown in fig. 10, for example by forming an opening (e.g., a trench or channel) partially through epitaxial region 404 between P-type body regions 406 and filling the opening with a dielectric material 1304. The dielectric material 1304 may be an oxide, such as silicon dioxide, although the invention is not limited to any particular electrically insulating material. Trench gate 1302 is then formed to extend vertically and below the source 408 and body 406 regions, partially through dielectric material 1304. Accordingly, the dielectric material 1304 electrically isolates the trench-gate 1304 from the surrounding epitaxial region 404, thereby preventing direct electrical contact between the trench-gate 1302 and the adjacent source and body regions 408, 406, and thus may be referred to as a "trench-gate oxide".
In one or more embodiments, an additional layer of dielectric material 1306 is formed over the upper surface of trench gate 1302, filling the trench and making it substantially flush with the upper surface of epitaxial layer 404. A thin gate oxide layer 1308 (e.g., about 3-50nm) is then formed (e.g., grown) on the upper surface of the epitaxial layer 404 and the upper surface of the dielectric material layer 1306. A planar gate (G1)416 is formed on the upper surface of the gate oxide 1308. Each planar gate 416 preferably comprises polysilicon and is formed using a standard Chemical Vapor Deposition (CVD) process, followed by patterning (e.g., using standard photolithography and etching). In this illustrative embodiment, there are two planar gates 416 disposed on either side of recessed trench gate 1302. Although not explicitly shown in fig. 13, the planar gate 416 and the trench gate 1302 may be formed as finger-like (i.e., lift-off) structures that are physically separated from each other, wherein the planar gate and the trench gate are electrically connected at one or both (opposite) ends of the finger.
As shown in fig. 13, the thickness of the trench gate oxide 1304 of the trench gate 1302 is substantially constant. However, it should be appreciated that in one or more alternative embodiments, the thickness of the trench gate oxide 1304 may be varied such that the trench gate 1302 has a tapered profile. For example, in one or more embodiments, the thickness of the trench gate oxide layer 1304 may be formed such that the thickness at the bottom of the trench is greater than the thickness at the top of the trench, consistent with the formation of the exemplary trench gate 920 shown in fig. 9I.
As shown in fig. 13, by separating the gate 418 shown in fig. 10 into a planar gate 1310 and a trench-like trench gate 1302 (recessed gate), the trench-like trench gate 1302 is recessed below the upper surface of the MOSFET device 1300, whereby when the trench gate 1302 is grounded and functions as a shield gate during the turn-off cycle, the coupling capacitance between the drain terminal and the control gate (G2) is advantageously reduced, thereby providing improved high frequency switching performance in the MOSFET device 1300.
In an alternative embodiment of the present invention, the planar gate 1310 may be eliminated (specifically, as shown in fig. 17, this is an example of eliminating the planar gate 1310). In the case of removing the planar gate 1310, the overlapping area of the trench gate and the planar gate becomes smaller due to the recess of the trench gate, the distance is further increased by the corner, and the coupling capacitance is significantly reduced, so that the object of the present invention can be achieved.
In another alternative embodiment of the present invention, the planar gate may also be configured in a shape similar to the T-shaped gate shown in fig. 6, which also achieves the object of the present invention.
In summary, since the trench gate is close to the source region and is easily coupled with a high voltage, if the capacitance is too large, the high voltage coupled by the trench gate can be easily further coupled to the planar gate, and if the coupling voltage exceeds the threshold voltage, the device is turned on by mistake. The arrangement of the MOSFET device 1300 of fig. 13 and the alternative embodiment thereof of the present invention can further reduce the planar gate to trench gate capacitance (relative to the MOSFET devices shown in fig. 1-12), thereby solving this technical problem.
In some applications, such as in a DC-DC voltage regulator, trench-gate 1302 may also be used to form a capacitor integrated on the same substrate as the MOSFET device and other circuit components, which is more efficient than conventional capacitor structures. For example, fig. 14 illustrates a cross-sectional view of at least a portion of an exemplary capacitor 1400, the capacitor 1400 including a trench structure adapted for integration with MOSFET devices and other circuit components on a common substrate. Referring to fig. 14, a capacitor 1400 includes a trench structure including a conductive or semiconductor material 1402 (e.g., polysilicon) forming a first plate of the capacitor, surrounded by a layer of dielectric material 1404, and a substrate material 404 forming a second plate of the capacitor.
The trench structure is preferably fabricated in a manner consistent with the formation of the trench gate structure of the MOSFET device 1300 shown in fig. 13. More specifically, in one or more embodiments, the trench structure of the capacitor 1400 is fabricated by forming an opening (e.g., a trench or channel) extending partially through the epitaxial region 404 and vertically and filling the opening with a dielectric material 1404. Alternatively, a dielectric material 1404 may be deposited or grown on the sidewalls of the opening. As with the dielectric material 1304 shown in fig. 13, the dielectric material 1404 may comprise an oxide (e.g., silicon dioxide), although the invention is not limited to any particular insulating material. After an opening is formed partially through the dielectric material 1404 in the trench, the opening is filled with a conductive or semiconductor material 1402 that forms a first plate of the capacitor 1400. Thus, the dielectric material 1404 electrically isolates the conductive or semiconductor material 1402 from the surrounding epitaxial region 404, thereby preventing direct electrical contact between the first and second plates.
More dielectric material is then deposited/grown in the trenches on the upper surface of the conductive or semiconductor material 1402 such that the upper surface of the trenches is substantially planar with the upper surface of the epitaxial layer 404. Subsequently, an insulating layer 1406 is formed over the trenches and the upper surface of epitaxial layer 404.
Fig. 15 illustrates an electrical schematic diagram of at least a portion of an exemplary switching DC-DC voltage regulator circuit 1500, implemented as a Buck converter, in which various aspects of one or more embodiments of the invention may be utilized. The voltage regulator circuit 1500 includes a first MOSFET device M1 (which may be referred to herein as a high-side device) and a second MOSFET device M2 (which may be referred to herein as a low-side device). The drain (D) of the high side device M1 is connected to the input voltage VINThe source (S) of M1 is connected to the output switch node SW, and the gate (G) of M1 is connected to the first drive circuit 1502. The drain of the low side device M2 is connected to the output switch node SW, the source of M2 is connected to ground, or an alternate voltage loop of the circuit 1500, and the gate of M2 is connected to the second driver circuit 1504.
The first and second drive circuits 1502, 1504 form part of a controller circuit 1506 for generating first and second control signals provided to the gates of the MOSFET devices M1 and M2, respectively. The first driving circuit 1502 is coupled between the switching node SW and the BOOT supply voltage BOOT, and the second driving circuit 1504 is coupled between the driving supply voltage VDRAnd ground. In one or more embodiments, each of the drive circuits 1502, 1504 can be implemented using an inverter. Driver supply voltage VDRIs preferably provided to the second driver circuit 1504 and the BOOT supply voltage BOOT is preferably provided to the first driver circuit 1502. A diode D1 is connected, having a voltage V equal to the driver supply voltageDRAn anode coupled to the power supply and having a cathode connected to a pilot supply voltage. The capacitor C1 is preferably connected between the BOOT supply voltage BOOT and the switch node SW. Diode D1 and capacitor C1 together form a bootstrap circuit for generating a sufficiently high voltage VG(VGNot shown) to fully open the N-channel MOSFET as a high-side switch, which is typically required when using an N-channel MOSFET for the high-side transistor of a Buck converter.
Voltage regulator circuit 1500 also includes a voltage regulator circuit coupled to the input voltage VINAnd an input capacitor C between groundINAnd is connected to the regulated output voltage VOUTAnd an output capacitor C between groundOUT. Output inductor L coupled between switch node SW and the output of voltage regulator circuit 1500OUTFor generating a regulated output voltage VOUT. Inductor L1 and output capacitor COUTTogether may serve as an energy storage element for the regulator circuit 1500.
When the capacitor 1400 shown in fig. 14 is used in a DC-DC voltage regulator application (e.g., the voltage regulator circuit 1500 shown in fig. 15), the first plate of the capacitor (including the conductor/semiconductor material 1402 in the trench) is preferably connected to ground (e.g., one or both ends of the trench) and the second plate of the capacitor is connected to the input voltage V via the drain terminal 414 of the high side MOSFET device M1IN. Thus, input capacitor C may be implemented using capacitor 1400INAnd integrated with the MOSFET device. However, since the drain is connected to a high potential voltage, a large depletion region will be formed within epitaxial layer 404. The boundary 1408 of the depletion region in epitaxial layer 404 is conceptually illustrated in fig. 14. This large depletion region results in a reduction in the capacitance of capacitor 1400, which is undesirable.
To increase capacitance without significantly increasing the area consumed by the capacitor, the illustrative capacitor 1400 of fig. 14 may be modified as shown in fig. 16. In particular, fig. 16 is a cross-sectional view illustrating at least a portion of an exemplary capacitor 1600 in accordance with one or more embodiments of the invention, the exemplary capacitor 1600 including a trench structure, consistent with the exemplary capacitor 1400 shown in fig. 14, which has been modified to provide increased capacitance.
Referring now to fig. 16, capacitor 1600 includes a first doped region 1602, i.e., an N + region in this embodiment, of the same conductivity type as epitaxial layer 404, formed in the epitaxial layer near its upper surface. N + regions 1602 are formed on opposite sides of the trench structures 1402, 1404. The second doped region 1604 has a conductivity type opposite to the first doped region 1602 in this embodiment, i.e., a P + region in this embodiment, and is formed in the epitaxial layer 404 and near the upper surface thereof. Each P + region 1604 has a first end contiguous with a respective N + region 1602 and has a second end opposite the first end, contiguous with a respective sidewall of the trench 1404. The N + regions 1602 are connected to respective P + regions 1604 with a conductive material 1606 formed on at least a portion of the upper surfaces of the N + and P + regions. In one or more embodiments, the conductive material 1606 used as an electrode for the capacitor 1600 is preferably formed using a silicide process.
With this improved design of capacitor 1600, drain 414 is at a high potential and holes are the predominant carrier in P + region 1604. In addition, the P + region 1604 will serve as a hole source that supplies holes along the periphery of the trench dielectric layer 1404. This creates a narrower depletion region in the device, conceptually depicted as boundary 1608. When the voltage potential between the electrode 1606 and ground increases by more than a prescribed amount, an inversion layer 1610 is formed at the oxide semiconductor interface near the periphery of the trench 1404. The inversion layer 1610 serves as a second plate of the capacitor 1600. Depletion region 1608 is connected to heavily doped p-type polysilicon layer 1604, which is in turn connected to heavily doped n-type polysilicon 1602 via silicide layer 1606. As the voltage potential is further increased, the width of the depletion region 1608 does not increase significantly because the charge in the inversion layer 1610 increases exponentially with the surface potential. In this manner, the capacitance of capacitor 1600 is advantageously increased.
In the illustrative DC-DC buck regulator circuit 1500, the source node of the high side MOSFET device M1 is connected to the drain node of the low side MOSFET device M2, and the voltage at the source node of M1 may ring to a high voltage. To reduce the potential ringing voltage, the input voltage V may be connected toINA decoupling capacitor is placed between the drain of the high side device M1 and ground. The decoupling capacitor is preferably placed as close as possible to the drain of the high side device M1. However, traditionally, such decoupling capacitors are packaged with power devices (power devices), which introduce some parasitic loop inductance. This parasitic loop inductance will weaken the filtering effect of the decoupling capacitor. To minimize this parasitic loop inductance, it is preferable to integrate decoupling capacitors into the switches. Part of the control gate in the trenchCan be used as a decoupling capacitor.
Fig. 17 illustrates a cross-sectional view of at least a portion of an exemplary power supply structure 1700 in accordance with one or more embodiments of the invention. On a common substrate 1706, the power structure 1700 integrates one or more power MOSFET devices 1702, each formed in a manner consistent with the illustrative MOSFET device 1300 shown in fig. 13, and one or more capacitor devices 1704, each formed in a manner consistent with the illustrative capacitor shown in fig. 16. Advantages of the power structure 1700 include reduced coupling capacitance between the planar gate (CG) and the control gate (gate) in the MOSFET device 1702, increased capacitance of the trench capacitor 1704, reduced parasitic inductance, and thus reduced ringing in the integrated device.
Accordingly, with reference to the illustrative embodiments shown in fig. 13-17, aspects of the present invention advantageously provide a high density capacitor formed using processes and structures compatible with MOSFET devices. In this manner, capacitors according to embodiments of the present invention can be easily monolithically integrated with power MOSFET transistors, which is an effective way to overcome the voltage ringing problem that plagues conventional buck converter circuits.
At least part of the techniques of the present invention may be implemented in an integrated circuit. In forming integrated circuits, the same mold is typically fabricated in a repetitive pattern on the surface of a semiconductor wafer. Each die includes a device as described herein, and may also include other structures and/or circuitry. A single die is cut from a wafer and then packaged into an integrated circuit one skilled in the art will know how to cut and package a die from a wafer to form an integrated circuit. Any of the exemplary structures or circuits shown in the figures, or portions thereof, may be part of an integrated circuit. Such integrated circuit fabrication methods are also considered to be part of the present invention.
Those skilled in the art will appreciate that the above-described exemplary structures in one or more embodiments of the present invention may be implemented in devices having power MOSFETs, e.g., Radio Frequency (RF) power amplifiers, power management integrated circuits, power system integration, etc., in raw form (i.e., a single wafer having a plurality of unpackaged chips), bare chip, or in packaged form, or as an intermediate or end product as an integral part of.
Substantially any high frequency, high power application and/or electronic system, such as, but not limited to, radio frequency power amplifiers, power management integrated circuits, and the like, may use integrated circuits consistent with the present disclosure. Systems suitable for implementing embodiments of the present invention may include, but are not limited to, DC-DC converters/regulators. Systems incorporating such integrated circuits are considered part of the present invention. Those of ordinary skill in the art, in view of the teachings of the present invention provided herein, will be able to contemplate other implementations and applications of embodiments of the present invention.
The illustrations presented herein for embodiments of the invention are intended to provide a general understanding of various embodiments, and are not intended to be a complete description of all the elements and features of apparatus and systems that might make use of the circuits and techniques of the invention. Many other embodiments will be apparent to those skilled in the art or may be derived therefrom, based on the teachings herein, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. The figures are also representative and are not drawn to scale. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Embodiments of the invention set forth herein may be referred to, individually and/or collectively, by the term "embodiment" merely for convenience and without intending to limit the scope of this invention in its application to any single or few embodiments or inventive concepts. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that an arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown; that is, the present invention is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the article singular may also include the plural unless the context clearly dictates otherwise. Further, when the terms "comprises" and/or "comprising" are used in this specification, the presence of stated features, steps, operations, elements, and/or components alone does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. And terms such as "above," "below," "upper" and "lower" are used to indicate relative positional relationships between elements or structures, rather than absolute positions.
Those of ordinary skill in the art, with the benefit of the teachings of the various embodiments of the invention, will be able to implement other implementations and applications of the techniques of the embodiments of the invention. Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the embodiments of the invention are not limited to those precise embodiments, and that various other modifications may be effected therein by one skilled in the art without departing from the scope of the claims.

Claims (20)

1. A metal oxide semiconductor field effect transistor device, comprising:
-a semiconductor substrate having a first conductivity type, said substrate serving as a drain region of said mosfet;
-an epitaxial region of a first conductivity type provided on an upper surface of the substrate;
a plurality of body regions of a second conductivity type formed in the epitaxial region, the second conductivity type being opposite the first conductivity type, the body regions being disposed adjacent an upper surface of the epitaxial region and laterally spaced apart from one another;
a plurality of source regions of a first conductivity type, each of the source regions being disposed in a corresponding body region and adjacent to an upper surface of the body region; and
-a gate structure comprising: one or more planar gates and a trench gate,
each planar gate is positioned on the upper surface of the epitaxial region and is overlapped with at least one part of the corresponding body region;
the trench gate is formed in at least part of the epitaxial region and between the body regions; an upper surface of the trench gate is configured to be recessed in the upper surface of the epitaxial region.
2. The device of claim 1, wherein the trench gate comprises:
a conductor or semiconductor structure; and
a dielectric layer at least surrounding the sidewalls, bottom and top of the conductor or semiconductor structure, the dielectric layer electrically isolating the conductor or semiconductor structure from the epitaxial region.
3. The device of claim 1, wherein the plurality of planar gates and the trench gate form finger structures physically separated from each other, the finger structures being electrically connected together by one or both ends thereof.
4. The device of claim 1, wherein at least one of the trench gate and the planar gate comprises a doped polysilicon material.
5. The device of claim 1, wherein the gate structure is configured to form a channel in each body region under the planar gate when a forward bias voltage applied exceeds a threshold voltage of an n-channel metal oxide semiconductor field effect transistor device, thereby turning on the device; meanwhile, a strong accumulation layer of majority carriers is formed in the epitaxial region close to the surface of the trench gate.
6. The device of claim 5, wherein the gate structure is configured such that a concentration of majority carriers in the device is a function of a bias voltage applied to the trench gate.
7. The device of claim 1, further comprising a dielectric layer disposed between the trench gate and the adjacent epitaxial region, the dielectric layer comprising:
a first portion forming a trench gate bottom wall and extending partially up to a sidewall of the trench gate; and
a second portion which is a side wall of the trench gate and extends upwards to the upper surface of the epitaxial region;
the first portion has a first thickness, the second portion has a second thickness, and the first thickness is greater than the second thickness.
8. The device of claim 1 further comprising at least two doped regions of a second conductivity type formed in respective body regions and adjacent to said upper surfaces of said body regions and laterally adjacent to said respective source regions, said two doped regions forming respective body region contacts of said device.
9. The device of claim 1, wherein each body region has a doping concentration of 5 x 1016Atom/cm3To 1X 1018Atom/cm3。
10. The device of claim 1, further comprising a plurality of gate electrodes electrically connected to the respective planar and trench gates of the gate structure; each of the gate electrodes includes a metal silicide layer formed on at least a portion of an upper surface of a corresponding one of the planar gate and the trench gate.
11. The device of claim 1, further comprising at least two recessed source region contacts, each source region contact being formed at a respective one of the body regions and adjacent to the upper surface of the body region and electrically connected to and in adjacent position to a respective one of the source regions.
12. A method of fabricating a metal oxide semiconductor field effect transistor device, the method comprising:
forming an epitaxial region of a first conductivity type on at least a portion of an upper surface of a substrate of the first conductivity type, the substrate serving as a drain region of the mosfet;
forming a plurality of body regions of a second conductivity type opposite in polarity to the first conductivity type in the epitaxial region, the body regions being disposed adjacent an upper surface of the epitaxial region and laterally spaced apart from one another;
forming a plurality of source regions having a first conductivity type, each of the source regions being disposed in a corresponding body region and adjacent to an upper surface of the body region; and
forming a gate structure including one or more planar gates and a trench gate, each planar gate being disposed on the upper surface of the epitaxial region and overlapping at least a portion of a corresponding body region; the trench gate is formed in at least part of the epitaxial region and between the body regions; an upper surface of the trench gate is configured to be recessed in the upper surface of the epitaxial region.
13. The method of claim 12, further comprising configuring the gate structure,
such that when an applied forward bias voltage exceeds the threshold voltage of an n-channel mosfet device, a channel is formed in each body region under the planar gate, thereby turning on the device; meanwhile, a strong accumulation layer of majority carriers is formed in the epitaxial region close to the surface of the trench gate.
14. The method of claim 12, wherein the step of forming the trench gate comprises:
forming a conductor or semiconductor structure; and
and forming a dielectric layer at least surrounding the side wall, the bottom and the top of the conductor or the semiconductor structure, wherein the dielectric layer electrically isolates the conductor or the semiconductor structure from the epitaxial region.
15. The method of claim 12, further comprising forming the plurality of planar gates and the trench gate as fingers physically separated from each other, the fingers being electrically connected together by one or both ends thereof.
16. A capacitor, comprising:
a semiconductor substrate having a first conductivity type;
an epitaxial region having a first conductivity type disposed on at least a portion of the upper surface of the substrate, the epitaxial region constituting a first plate of the capacitor;
the trench gate is formed in at least part of the epitaxial region and is close to the upper surface of the epitaxial region; the trench gate comprising a conductor or semiconductor material forming a second plate of the capacitor surrounded by a dielectric layer electrically isolating the conductor or semiconductor from the epitaxial region;
a plurality of doped regions of the first conductivity type disposed in the epitaxial region and on opposite sides of the trench gate and proximate an upper surface of the epitaxial region; and
a plurality of doped regions of a second conductivity type opposite in polarity to the first conductivity type, each doped region of the second conductivity type having a first end adjacent a respective one of the doped regions of the first conductivity type and a second end opposite the first end and adjacent a respective sidewall of the trench gate.
17. A capacitor according to claim 16, wherein the upper surface of the conductor or semiconductor is arranged to be recessed below the upper surface of the epitaxial region.
18. The capacitor of claim 16, further comprising a second dielectric layer disposed on an upper surface of said conductor or semiconductor forming said trench gate.
19. A method of manufacturing a capacitor, the method comprising:
forming an epitaxial region of a first conductivity type on at least a portion of an upper surface of the substrate, the epitaxial region constituting a first plate of the capacitor;
forming a trench gate in at least part of the epitaxial region and close to the upper surface layer of the epitaxial region; the trench gate contains a conductor or semiconductor material that serves as a second plate of the capacitor and is surrounded by a dielectric layer that electrically isolates the conductor or semiconductor from the epitaxial region;
forming a plurality of doped regions with a first conductivity type on opposite sides of the trench gate in the epitaxial region and near an upper surface of the epitaxial region; and
forming a plurality of doped regions having a second conductivity type, the second conductivity type being opposite in polarity to the first conductivity type; a first end of each of the doped regions of the second conductivity type abuts a respective one of the doped regions of the first conductivity type and a second end opposite the first end abuts a respective sidewall of the trench gate.
20. The method of claim 19, wherein the method comprises:
when the trench gate is formed, the method includes recessing an upper surface of the conductor or semiconductor below the upper surface of the epitaxial region.
CN202111547635.XA 2020-03-04 2021-12-16 Mosfet with enhanced high frequency performance Pending CN114361250A (en)

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US17/684,849 US20220384594A1 (en) 2020-03-04 2022-03-02 Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117038710A (en) * 2023-10-10 2023-11-10 艾科微电子(深圳)有限公司 Semiconductor device and method for manufacturing the same
CN117038738A (en) * 2023-10-10 2023-11-10 艾科微电子(深圳)有限公司 Semiconductor device and method for manufacturing the same
CN117352555A (en) * 2023-12-06 2024-01-05 无锡锡产微芯半导体有限公司 Integrated shielded gate trench MOSFET and preparation process thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117038710A (en) * 2023-10-10 2023-11-10 艾科微电子(深圳)有限公司 Semiconductor device and method for manufacturing the same
CN117038738A (en) * 2023-10-10 2023-11-10 艾科微电子(深圳)有限公司 Semiconductor device and method for manufacturing the same
CN117038738B (en) * 2023-10-10 2024-01-26 艾科微电子(深圳)有限公司 Semiconductor device and method for manufacturing the same
CN117038710B (en) * 2023-10-10 2024-01-26 艾科微电子(深圳)有限公司 Semiconductor device and method for manufacturing the same
CN117352555A (en) * 2023-12-06 2024-01-05 无锡锡产微芯半导体有限公司 Integrated shielded gate trench MOSFET and preparation process thereof
CN117352555B (en) * 2023-12-06 2024-04-09 无锡锡产微芯半导体有限公司 Integrated shielded gate trench MOSFET and preparation process thereof

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