CN117038738B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN117038738B CN117038738B CN202311305778.9A CN202311305778A CN117038738B CN 117038738 B CN117038738 B CN 117038738B CN 202311305778 A CN202311305778 A CN 202311305778A CN 117038738 B CN117038738 B CN 117038738B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
Abstract
The present disclosure provides a semiconductor device and a method of manufacturing the same, relating to the field of semiconductor technology, the device comprising: a substrate having a first conductivity type and an epitaxial region; a first trench and a second trench in the epitaxial region, the first trench having a depth greater than a depth of the second trench; a first gate structure including a first gate at least partially in the first trench and a first gate dielectric layer between the first gate and the epitaxial region; a second gate structure including a second gate at least partially in the second trench and a second dielectric layer between the second gate and the epitaxial region; a body region of a second conductivity type spaced apart from the first gate dielectric layer adjacent the second gate dielectric layer; a first electrode region having a first conductivity type; a third gate structure on a surface of the epitaxial region away from the substrate and partially overlapping the body region; and a second electrode. In this way, the avalanche resistance of the semiconductor device is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
The power transistor is a semiconductor device capable of operating under high voltage and high current conditions, and has wide application in high-power electronic equipment such as frequency converters, motor controllers, direct current-direct current converters, power supplies and the like.
Disclosure of Invention
According to an aspect of the embodiments of the present disclosure, there is provided a semiconductor device including: a substrate having a first conductivity type; an epitaxial region of a first conductivity type over the substrate; a first trench and a second trench, both located in the epitaxial region, wherein a depth of the first trench in the epitaxial region is greater than a depth of the second trench in the epitaxial region in a direction from the epitaxial region to the substrate; a first gate structure comprising a first gate at least partially in the first trench, and a first gate dielectric layer between the first gate and the epitaxial region; a second gate structure comprising a second gate at least partially in the second trench, and a second gate dielectric layer between the second gate and the epitaxial region; a body region of a second conductivity type in the epitaxial region between the first gate structure and the second gate structure, the body region being spaced apart from and contiguous with the first gate dielectric layer, the second conductivity type being different from the first conductivity type; a first electrode region of a first conductivity type located in the body region; the third grid structure is positioned on one surface of the epitaxial region, which is far away from the substrate, and is partially overlapped with the body region; and a second electrode located under the substrate.
According to another aspect of the embodiments of the present disclosure, there is provided a semiconductor device including: a substrate having a first conductivity type; an epitaxial region of a first conductivity type over the substrate; a first trench and a second trench both located in the epitaxial region, wherein a bottom of the first trench is closer to the substrate than a bottom of the second trench; a first gate structure comprising a first gate at least partially in the first trench, and a first gate dielectric layer between the first gate and the epitaxial region; a second gate structure comprising a second gate at least partially in the second trench, and a second gate dielectric layer between the second gate and the epitaxial region; a body region of a second conductivity type in the epitaxial region between the first gate structure and the second gate structure, the body region being spaced apart from the first gate dielectric layer, the second conductivity type being different from the first conductivity type; a first electrode region of a first conductivity type located in the body region; the third grid structure is positioned on one surface of the epitaxial region, which is far away from the substrate, and is partially overlapped with the body region; and a second electrode located under the substrate.
In some embodiments, the first and second grooves extend in a first direction, the first groove having a dimension in a second direction that is greater than a dimension of the second groove in the second direction, the second direction being perpendicular to the first direction.
According to still another aspect of the embodiments of the present disclosure, there is provided a semiconductor device including: a substrate having a first conductivity type; an epitaxial region of a first conductivity type over the substrate; a first gate structure comprising a first gate at least partially in the epitaxial region, and a first gate dielectric layer between the first gate and the epitaxial region; a second gate structure comprising a second gate at least partially in the epitaxial region, and a second gate dielectric layer between the second gate and the epitaxial region, wherein a depth of the first gate in the epitaxial region is greater than a depth of the second gate in the epitaxial region in a direction from the epitaxial region to the substrate; a body region of a second conductivity type in the epitaxial region between the first gate structure and the second gate structure, the body region being spaced apart from and contiguous with the first gate dielectric layer, the second conductivity type being different from the first conductivity type; a first electrode region of a first conductivity type located in the body region; the third grid structure is positioned on one surface of the epitaxial region, which is far away from the substrate, and is partially overlapped with the body region; and a second electrode located under the substrate.
In some embodiments, the extension direction of the first gate and the second gate is a first direction, and a dimension of the first gate in a second direction is greater than a dimension of the second gate in the second direction, the second direction being perpendicular to the first direction.
In some embodiments, the third gate structure comprises: a third gate; and a third gate dielectric layer between a side of the epitaxial region remote from the substrate and the third gate; wherein the third gate structure partially overlaps the first gate dielectric layer.
In some embodiments, the third gate structure does not overlap the first gate.
In some embodiments, the extension direction of the third gate structure is a first direction, and a dimension of an overlapping portion of the third gate structure and the first gate dielectric layer in a second direction is less than or equal to a micrometer, the second direction being perpendicular to the first direction.
In some embodiments, the device further comprises: a doped region of a second conductivity type is located in the epitaxial region and adjacent the first gate dielectric layer, the doped region being spaced apart from the body region by the epitaxial region.
In some embodiments, the first gate dielectric layer includes a first portion located at a first sidewall of a first trench where the first gate is located, a second portion located at a second sidewall of the first trench, and a third portion located at a bottom of the first trench, the third portion connected between the first portion and the second portion; the device comprises two body regions positioned on two sides of the first gate structure, wherein the third gate structure is partially overlapped with the first part and is partially overlapped with one of the two body regions; the device further comprises: and a fourth gate structure located on a side of the epitaxial region away from the substrate, comprising a fourth gate and a fourth gate dielectric layer located between the side of the epitaxial region away from the substrate and the fourth gate, wherein the fourth gate structure is partially overlapped with the second part and is partially overlapped with the other one of the two body regions.
In some embodiments, the device includes two of the doped regions on either side of the first gate structure; one of the two doped regions and one of the two body regions are separated by the epitaxial region and are contiguous with the first portion; the other of the two doped regions is separated from the other of the two body regions by the epitaxial region and is contiguous with the second portion.
In some embodiments, the device further includes a first spacer layer and a second spacer layer on both sides of the third gate structure, the first spacer layer being on a surface of the first gate dielectric layer and the second spacer layer being on a surface of the body region.
In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type; the first electrode region is a source region and the second electrode is a drain.
According to still another aspect of the embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: providing a substrate having a first conductivity type; forming an epitaxial region having a first conductivity type over the substrate; forming a first trench and a second trench in the epitaxial region, wherein a depth of the first trench in the epitaxial region is greater than a depth of the second trench in the epitaxial region in a direction from the epitaxial region to the substrate; forming a first gate structure in the first trench and forming a second gate structure in the second trench, the first gate structure including a first gate at least partially in the first trench and a first gate dielectric layer between the first gate and the epitaxial region, the second gate structure including a second gate at least partially in the second trench and a second gate dielectric layer between the second gate and the epitaxial region; forming a third grid structure on one surface of the epitaxial region, which is far away from the substrate; after forming the third gate structure, performing a doping process to form a body region of a second conductivity type in the epitaxial region between the first gate structure and the second gate structure, the body region partially overlapping the third gate structure, the body region being spaced apart from the first gate dielectric layer and contiguous with the second gate dielectric layer, the second conductivity type being different from the first conductivity type; forming a first electrode region having a first conductivity type in the body region; a second electrode is formed under the substrate.
According to still another aspect of the embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: providing a substrate having a first conductivity type; forming an epitaxial region having a first conductivity type over the substrate; forming a first trench and a second trench in the epitaxial region, wherein a bottom of the first trench is closer to the substrate than a bottom of the second trench; forming a first gate structure in the first trench and forming a second gate structure in the second trench, the first gate structure including a first gate at least partially in the first trench and a first gate dielectric layer between the first gate and the epitaxial region, the second gate structure including a second gate at least partially in the second trench and a second gate dielectric layer between the second gate and the epitaxial region; forming a third grid structure on one surface of the epitaxial region, which is far away from the substrate; after forming the third gate structure, performing a doping process to form a body region of a second conductivity type in the epitaxial region between the first gate structure and the second gate structure, the body region partially overlapping the third gate structure, the body region being spaced apart from the first gate dielectric layer, the second conductivity type being different from the first conductivity type; forming a first electrode region having a first conductivity type in the body region; a second electrode is formed under the substrate.
In some embodiments, the first and second grooves extend in a first direction, the first groove having a dimension in a second direction that is greater than a dimension of the second groove in the second direction, the second direction being perpendicular to the first direction.
In some embodiments, forming a first gate structure in the first trench and forming a second gate structure in the second trench includes: forming a dielectric material layer on the bottom and the side wall of the first groove, the bottom and the side wall of the second groove and one surface of the epitaxial region away from the substrate; filling conductive material in the first trench and the second trench after forming the dielectric material layer to form the first gate and the second gate; and removing the part of the dielectric material layer on the surface of the epitaxial region, which is far away from the substrate, wherein the part of the dielectric material layer on the bottom and the side wall of the first groove is used as the first gate dielectric layer, and the part of the dielectric material layer on the bottom and the side wall of the second groove is used as the second gate dielectric layer.
According to still another aspect of the embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: providing a substrate having a first conductivity type; forming an epitaxial region having a first conductivity type over the substrate; forming a first gate structure and a second gate structure in the epitaxial region, the first gate structure comprising a first gate at least partially located in the epitaxial region and a first gate dielectric layer located between the first gate and the epitaxial region, the second gate structure comprising a second gate at least partially located in the epitaxial region and a second gate dielectric layer located between the second gate and the epitaxial region, wherein a depth of the first gate in the epitaxial region is greater than a depth of the second gate in the epitaxial region in a direction from the epitaxial region to the substrate; forming a third grid structure on one surface of the epitaxial region, which is far away from the substrate; after forming the third gate structure, performing a doping process to form a body region of a second conductivity type in the epitaxial region between the first gate structure and the second gate structure, the body region partially overlapping the third gate structure, the body region being spaced apart from the first gate dielectric layer and contiguous with the second gate dielectric layer, the second conductivity type being different from the first conductivity type; forming a first electrode region having a first conductivity type in the body region; a second electrode is formed under the substrate.
In some embodiments, the extension direction of the first gate and the second gate is a first direction, and a dimension of the first gate in a second direction is greater than a dimension of the second gate in the second direction, the second direction being perpendicular to the first direction.
In some embodiments, the method further comprises: at least one of the first gate and the second gate is doped.
In some embodiments, the doping is performed on at least one of the first gate and the second gate prior to forming the body region; the method further comprises the steps of: after forming the body region, a first anneal is performed.
In some embodiments, the forming the third gate structure includes: forming a third gate dielectric layer on one surface of the epitaxial region away from the substrate; performing a second anneal after forming the third gate dielectric layer; forming a third gate on a surface of the third gate dielectric layer away from the substrate; wherein at least one of the first gate and the second gate is doped prior to forming the third gate dielectric layer.
In some embodiments, the third gate structure comprises: a third gate; and a third gate dielectric layer between a side of the epitaxial region remote from the substrate and the third gate; wherein the third gate structure partially overlaps the first gate dielectric layer.
In some embodiments, the extension direction of the third gate structure is a first direction, and a size of an overlapping portion of the third gate structure with the first gate dielectric layer in a second direction is less than or equal to 0.1 micrometers, the second direction being perpendicular to the first direction.
In some embodiments, the doping process also forms a doped region in the epitaxial region, the doped region being contiguous with the first gate dielectric layer, the doped region being separated from the body region by the epitaxial region.
In some embodiments, the method further comprises: and forming a first spacer layer and a second spacer layer on two sides of the third gate structure, wherein the first spacer layer is positioned on the surface of the first gate dielectric layer, and the second spacer layer is positioned on the surface of the body region.
In some embodiments, the method further comprises: forming a first silicide layer, a second silicide layer, a third silicide layer, and a fourth silicide layer after forming the first spacer layer and the second spacer layer; the first silicide layer is located on one surface of the first grid electrode, which is far away from the substrate, the second silicide layer is located on one surface of the second grid electrode, which is far away from the substrate, the third silicide layer is located on one surface of the third grid electrode, which is far away from the substrate, and the fourth silicide layer is located on one surface of the first electrode area, which is far away from the substrate.
In the embodiment of the disclosure, the current path of the semiconductor device in normal conduction is different from the current path in avalanche breakdown. The region of the epitaxial region through which the current path flows in normal conduction is relatively closer to the first gate structure, while the region of the epitaxial region through which the current path flows in avalanche breakdown is relatively closer to the second gate structure. Therefore, the possibility of conducting parasitic triodes in the semiconductor device during avalanche breakdown is reduced, so that the avalanche resistance of the semiconductor device is improved, and the possibility of damaging the device is reduced. In addition, the adverse effect of hot carriers at avalanche breakdown on the dielectric layer in the third gate structure is reduced.
Other features, aspects, and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the disclosure, which is to be read in connection with the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The present disclosure will be more clearly understood from the following detailed description with reference to the accompanying drawings.
Fig. 1A to 4 are cross-sectional views of semiconductor devices according to other embodiments of the present disclosure.
Fig. 5 is a schematic perspective view of a semiconductor device according to some embodiments of the present disclosure.
Fig. 6 is a cross-sectional view of a semiconductor device of some embodiments in the related art.
Fig. 7 is a top view of a semiconductor device according to some embodiments of the present disclosure.
Fig. 8A through 10 are cross-sectional views of semiconductor devices according to further embodiments of the present disclosure.
Fig. 11 is a flow chart of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.
Fig. 12-27 are cross-sectional views of various stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.
Fig. 28 is a flow chart of a method of manufacturing a semiconductor device according to further embodiments of the present disclosure.
It should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to actual scale. Further, the same or similar reference numerals denote the same or similar members.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative, and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments should be construed as exemplary only and not limiting unless otherwise specifically stated.
The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises" and the like means that elements preceding the word encompass the elements recited after the word, and not exclude the possibility of also encompassing other elements. "upper", "lower", etc. are used merely to denote relative positional relationships, which may also change accordingly when the absolute position of the object to be described changes.
In this disclosure, when a particular element is described as being located between a first element and a second element, there may or may not be intervening elements between the particular element and the first element or the second element. When it is described that a specific component is connected to other components, the specific component may be directly connected to the other components without intervening components, or may be directly connected to the other components without intervening components.
All terms (including technical or scientific terms) used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs, unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In the related art, a power transistor (e.g., a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) is susceptible to avalanche multiplication of internal carriers under the influence of a change in an electrical quantity (e.g., a drain-source voltage) under certain conditions (e.g., reverse bias), and thus an avalanche breakdown phenomenon occurs, which easily causes a parasitic transistor inside a semiconductor device to be turned on, thereby causing the semiconductor device to be damaged.
In view of this, the present disclosure proposes a solution that can improve the avalanche resistance of a semiconductor device to reduce the likelihood of device damage.
Fig. 1A-4 are cross-sectional views of semiconductor devices according to some embodiments of the present disclosure.
As shown in fig. 1A and 1B, the semiconductor device 1000 includes a substrate 110 and an epitaxial region 120 located over the substrate 110. For example, epitaxial region 120 may be located on first surface 111 of substrate 110.
The substrate 110 and the epitaxial region 120 each have a first conductivity type. The first conductivity type may be one of N-type and P-type. The semiconductor device 1000 may be, for example, a power MOSFET.
The semiconductor device 1000 further includes a first gate structure 130, a second gate structure 140, and a body region 150.
The first gate structure 130 includes a first gate TG1 at least partially located in the epitaxial region 120, and a first gate dielectric layer 131 located between the first gate TG1 and the epitaxial region 120. Here, a portion of the first gate TG1 located in the epitaxial region 120 is surrounded by the first gate dielectric layer 131.
As some implementations, a surface of the first gate TG1 remote from the substrate 110 is flush with a surface of the epitaxial region 120 remote from the substrate 110, i.e., the first gate TG1 may be entirely located in the first trench T1.
As other implementations, a surface of the first gate TG1 away from the substrate 110 is higher than a surface of the epitaxial region 120 away from the substrate 110, i.e., the first gate TG1 protrudes from the epitaxial region 120. That is, the first gate TG1 may be partially located in the first trench T1, and the first gate TG1 may include a portion located in the first trench T1 and another portion located outside the first trench T1 in the epitaxial region 120.
The second gate structure 140 includes a second gate TG2 at least partially located in the epitaxial region 120, and a second gate dielectric layer 141 located between the second gate TG2 and the epitaxial region 120. Here, a portion of the second gate TG2 located in the epitaxial region 120 is surrounded by the second gate dielectric layer 141.
As some implementations, a surface of the second gate TG2 remote from the substrate 110 is flush with a surface of the epitaxial region 120 remote from the substrate 110, i.e., the second gate TG2 may be entirely located in the second trench T2.
As other implementations, a surface of the second gate TG2 away from the substrate 110 is higher than a surface of the epitaxial region 120 away from the substrate 110, i.e., the second gate TG2 protrudes from the epitaxial region 120. That is, the second gate TG2 may be partially located in the second trench T2, and the second gate TG2 may include a portion located in the second trench T2 and another portion located outside the second trench T2 in the epitaxial region 120.
In some embodiments, the material of the first gate TG1 and the second gate TG2 may include a conductive material such as doped polysilicon or metal.
The body region 150 is located in the epitaxial region 120 between the first gate structure 130 and the second gate structure 140. The body region 150 is spaced apart from the first gate dielectric layer 131. Here, the body region 150 is spaced apart from the first gate dielectric layer 131 by the epitaxial region 120. Body region 150 may extend from epitaxial region 120 away from substrate 110 in a facing epitaxial region 120.
In some embodiments, body region 150 also abuts second gate dielectric layer 141.
In some embodiments, as shown in fig. 1B, semiconductor device 1000 further includes doped region 180. Doped region 180 is located in epitaxial region 120 and abuts first gate dielectric layer 131. This will be further described later.
The body region 150 has a second conductivity type different from the first conductivity type. For example, in the case where the first conductivity type is N-type, the second conductivity type may be P-type, i.e., the body region 150 is a P-type body region (i.e., P-body).
The semiconductor device 1000 further includes a third gate structure PG', a first electrode region 160, and a second electrode 170.
The third gate structure PG' is located on a side of the epitaxial region 120 away from the substrate 110 and partially overlaps the body region 150. For example, as shown in fig. 1A, the third gate structure PG' may cover a portion of the surface of the epitaxial region 120 and a portion of the surface of the body region 150.
In some embodiments, as shown in fig. 1A, the third gate structure PG' partially overlaps the body region 150 and does not overlap the first gate dielectric layer 131.
In other embodiments, as shown in fig. 1B, the third gate structure PG' partially overlaps the body region 150 and partially overlaps the first gate dielectric layer 131. This will be further described later.
The first electrode region 160 is located in the body region 150 and has a first conductive type. The second electrode 170 is located under the substrate 110. For example, the second electrode 170 may be located on the second surface 112 of the substrate 110 facing away from the first surface 111.
For example, the first electrode region 160 may be a source region and the second electrode 170 may be a drain electrode.
In some embodiments, the semiconductor device 1000 may further include a doped region 161 located in the body region 150. The doped region 161 has the second conductivity type. For example, the doped region 161 may be located between the first electrode region 160 and the second gate structure 140. For example, the doped region 161 is a heavily doped region.
In some embodiments, the semiconductor device 1000 may further include a first trench T1 and a second trench T2 in the epitaxial region 120. In these embodiments, at least a portion of the first gate TG1 may be located in the first trench T1 in the epitaxial region 120, the portion of the first gate TG1 located in the first trench T1 being surrounded by the first gate dielectric layer 131; at least a portion of the second gate TG2 may be located in the second trench T2 in the epitaxial region 120, and a portion of the second gate TG2 located in the second trench T2 is surrounded by the second gate dielectric layer 141.
As shown in fig. 2, in the semiconductor device 1000, a depth h1 of the first gate TG1 in the epitaxial region 120 is greater than a depth h2 of the second gate TG2 in the epitaxial region 120 in a direction from the epitaxial region 120 to the substrate 110.
As shown in fig. 3, in the case where the semiconductor device 1000 further includes the first trench T1 and the second trench T2, a depth h3 of the first trench T1 in the epitaxial region 120 is greater than a depth h4 of the second trench T2 in the epitaxial region 120 in a direction from the epitaxial region 120 to the substrate 110, that is, a bottom of the first trench 130 is closer to the substrate 110 than a bottom of the second trench 140. In some embodiments, the thicknesses of the first gate dielectric layer 131 and the second gate dielectric layer 141 are substantially the same, in which case the depth h1 of the first gate TG1 in the epitaxial region 120 is greater than the depth h2 of the second gate TG2 in the epitaxial region 120.
For example, the depth h3 of the first trench T1 in the epitaxial region 120 is about 2.1 microns, the depth h4 of the second trench T2 in the epitaxial region 120 is about 2.0 microns, and the thicknesses of the first gate dielectric layer 131 and the second gate dielectric layer 141 are each about 0.2 microns, then the depth h1 (about 1.9 microns) of the first gate TG1 in the epitaxial region 120 is greater than the depth h2 (about 1.8 microns) of the second gate TG2 in the epitaxial region 120.
Fig. 4 shows a partial schematic view of a semiconductor device 1000. The flow of current in different scenarios will be described below using the semiconductor device 1000 as an N-type transistor.
When the semiconductor device 1000 is normally on, current from the second electrode 170 flows in the direction indicated by the four thin arrows on the left side in fig. 4, through the region of the epitaxial region closer to the first gate structure 130, to the channel region under the third gate structure PG', and further to the first electrode region 160.
In the case of avalanche breakdown of the semiconductor device 1000, since the first gate TG1 and the second gate TG2 having different depths change the electric field structure in the epitaxial region 120, the avalanche current is concentrated to the first electrode region 160 through the shortest path between the second electrode 170 and the first electrode region 160 (i.e., through the region of the epitaxial region closer to the second gate structure 140) in the direction indicated by the thick arrow on the right side in fig. 4.
Similarly, the first and second trenches T1 and T2 having different depths also change the electric field structure in the epitaxial region 120, so that the avalanche current is concentrated to the first electrode region 160 through the shortest path between the second electrode 170 and the first electrode region 160 in the direction indicated by the thick arrow on the right in fig. 4.
As can be seen, according to the semiconductor device of the embodiment of the present disclosure, the current path of the semiconductor device at the time of normal conduction and the current path at the time of avalanche breakdown are different. The region of the epitaxial region 120 through which the current path during normal conduction flows is relatively closer to the first gate structure 130, while the region of the epitaxial region 120 through which the current path during avalanche breakdown flows is relatively closer to the second gate structure 140. Therefore, the possibility of conducting parasitic triodes in the semiconductor device during avalanche breakdown is reduced, so that the avalanche resistance of the semiconductor device is improved, and the possibility of damaging the device is reduced. In addition, the adverse effect of hot carriers at avalanche breakdown on the dielectric layer in the third gate structure PG' is reduced.
Fig. 5 is a schematic perspective view of a semiconductor device according to some embodiments of the present disclosure.
As shown in fig. 5, the extending directions of the first trench T1 and the second trench T2 and the extending directions of the first gate TG1 and the second gate TG2 are both the first direction Y. The second direction X is perpendicular to the first direction Y. The direction from epitaxial region 120 to substrate 110 (i.e., the direction perpendicular to substrate 110) is a third direction Z.
In some embodiments, referring to fig. 2, in the third direction Z, the depth h1 of the first gate TG1 in the epitaxial region 120 is greater than the depth h2 of the second gate TG2 in the epitaxial region 120, and the dimension w1 of the first gate TG1 in the second direction X is greater than the dimension w2 of the second gate TG2 in the second direction.
In some embodiments, referring to fig. 3, in the third direction Z, the depth h3 of the first trench T1 in the epitaxial region 120 is greater than the depth h4 of the second trench T2 in the epitaxial region 120, and the dimension w3 of the first trench T1 in the second direction X is greater than the dimension w4 of the second trench T2 in the second direction. For example, the dimension w3 of the first trench T1 in the second direction X is about 0.65 micron, and the dimension w4 of the second trench T2 in the second direction is about 0.55 micron.
Because the etching gas enters more at the larger part of the photomask opening, the groove formed after etching is deeper, and the etching gas enters less at the smaller part of the photomask opening, so that the groove formed after etching is shallower. In the case where the dimension w3 of the first trench T1 in the second direction X is greater than the dimension w4 of the second trench T2 in the second direction, two trenches having different depths may be formed by the same etching process, thereby reducing the manufacturing cost of the semiconductor device and improving the manufacturing efficiency.
Fig. 6 is a cross-sectional view of a semiconductor device of some embodiments in the related art.
In the related art, as shown in fig. 6, the third gate structure PG' and the first gate structure 130 do not overlap, and there is a large gap therebetween. If the actual position of the third gate structure PG 'is shifted with respect to the expected position during the formation of the third gate structure PG', the body region 150 formed later is also shifted, and the dimension d of the epitaxial region 120 between the body region 150 and the first gate structure 130 in the second direction X is changed, thereby adversely affecting the semiconductor device.
For example, in the case that the actual position of the third gate structure PG' is shifted rightward relative to the expected position, the body region 150 is shifted rightward, so that the dimension d of the epitaxial region 120 between the body region 150 and the first gate structure 130 in the second direction X is increased, and the parasitic transistor inside the semiconductor device is further turned on more easily, that is, the breakdown voltage of the semiconductor device is reduced, which results in poor avalanche resistance of the semiconductor device and a high possibility of damage to the device.
For another example, in the case that the actual position of the third gate structure PG' is shifted leftward with respect to the expected position, the body region 150 is shifted leftward therewith, resulting in a decrease in the dimension d of the epitaxial region 120 between the body region 150 and the first gate structure 130 in the second direction X, which in turn results in an increase in the on-resistance of the semiconductor device, thereby adversely affecting the normal conduction of the semiconductor device.
In view of this, the present disclosure also proposes the following solution.
Fig. 7 is a top view of a semiconductor device according to some embodiments of the present disclosure. Fig. 8A to 10 are cross-sectional views of semiconductor devices according to other embodiments of the present disclosure. Fig. 8C is a cross-sectional view taken along the section line in fig. 7.
As shown in fig. 8A-8C, a semiconductor device 1001 includes a substrate 110 and an epitaxial region 120 at a first surface 111 of the substrate 110. The substrate 110 and the epitaxial region 120 each have a first conductivity type.
The semiconductor device 1001 further includes a first trench T1 and a first gate structure 130 in the epitaxial region 120.
The first gate structure 130 includes a first gate TG1 located in the first trench T1, and a first gate dielectric layer 131 located between the first gate TG1 and the epitaxial region 120.
The semiconductor device 1001 further includes a body region 150, a first electrode region 160, a second electrode 170, and a third gate structure PG'.
A body region 150 is located in the epitaxial region 120 and is spaced apart from the first gate dielectric layer 131. The body region 150 has a second conductivity type different from the first conductivity type. For example, the second conductivity type is P-type and the first conductivity type is N-type.
The first electrode region 160 is located in the body region 150 and has a first conductive type.
The second electrode 170 is located on the second surface 112 of the substrate 110 facing away from the first surface 111. For example, the second electrode 170 is a drain electrode, and the first electrode region 160 is a source region.
The third gate structure PG' is located on a side of the epitaxial region 120 away from the substrate 110, and includes a third gate PG, and a third gate dielectric layer GOX located between the side of the epitaxial region 120 away from the substrate 110 and the third gate PG. The third gate structure PG' partially overlaps the first gate dielectric layer 131 and partially overlaps the body region 150.
In other words, the orthographic projections of the third gate PG and the third gate dielectric layer GOX on the substrate 110 partially overlap with the orthographic projections of the first gate dielectric layer 131 on the substrate 110. For example, the third gate dielectric layer GOX is in contact with a portion of the surface of the first gate dielectric layer 131.
It is to be understood that the semiconductor device 1001 may further include a second trench T2 and a second gate structure 140, as shown in fig. 8B and 8C. In the semiconductor device 1001, the depth of the first trench T1 in the epitaxial region and the depth of the second trench T2 in the epitaxial region may be the same (as shown in fig. 8B) or different (as shown in fig. 8C) in the direction from the epitaxial region 120 to the substrate 110. The depth of the first gate TG1 in the epitaxial region and the depth of the second gate TG2 in the epitaxial region may be the same (as shown in fig. 8B) or may be different (as shown in fig. 8C).
Other specific descriptions of the substrate 110, the epitaxial region 120, the first trench T1, the first gate structure 130, the body region 150, the third gate structure PG', the first electrode region 160 and the second electrode 170 in the semiconductor device shown in fig. 8A can be found in the foregoing related embodiments of fig. 1A to 5, and will not be repeated here.
In some embodiments, the material of the third gate PG may include a conductive material such as doped polysilicon or metal. The material of the third gate PG may be the same as or different from the material of the first gate TG1 and the second gate TG 2.
In some embodiments, the extension direction of the third gate structure PG 'is the first direction Y, and the size of the overlapping portion of the third gate structure PG' and the first gate dielectric layer 131 in the second direction X may be less than or equal to 0.1 micrometer.
In some embodiments, the third gate structure PG' does not overlap the first gate TG1, i.e., the third gate dielectric layer GOX extends to the surface of the first gate dielectric layer 131, but does not extend to the surface of the first gate TG 1. In this way, adverse effects caused by too little silicide on the first gate TG1 can be avoided.
In some embodiments, the semiconductor device 1001 may further include a doped region 180 (which may also be referred to as an angle doped region) having a second conductivity type. Doped region 180 is located in epitaxial region 120 and abuts first gate dielectric layer 131. In addition, doped region 180 is spaced apart from body region 150 by epitaxial region 120 therebetween. In some embodiments, the doped region 180 and the body region 150 may be formed in the same process. This will be further described later.
Since the third gate structure PG 'partially overlaps the body region 150 and partially overlaps the first gate dielectric layer 131, the dimension of the epitaxial region 120 between the body region 150 and the first gate structure 130 in the second direction X may remain substantially unchanged even if the actual position of the third gate structure PG' is shifted with respect to the intended position.
The right end of the third gate structure PG 'determines the dimension of the body region 150 in the second direction X, and the left end of the third gate structure PG' determines the dimension of the doped region 180 in the second direction X. Thus, even if the actual position of the third gate structure PG 'is shifted with respect to the expected position, whether (1) the third gate structure PG' is shifted to the left, the size of the body region 150 in the second direction X is increased, and the size of the doped region 180 in the second direction X is reduced; or (2) the third gate structure PG ' is shifted rightward, so that the dimension of the body region 150 in the second direction X is reduced, and the dimension of the doped region 180 in the second direction X is increased, so that the dimension of the epitaxial region 120 under the third gate structure PG ' in the second direction X can be kept substantially unchanged, thereby reducing the adverse effect caused by the shift of the position of the third gate structure PG '. For example, the impact on the breakdown voltage of the semiconductor device is reduced, thereby improving the avalanche resistance of the semiconductor device and reducing the likelihood of device damage.
This is further described below in conjunction with fig. 9 and 10. Fig. 9 and 10 show a part of the semiconductor device 1001 in fig. 7.
In some embodiments, as shown in fig. 9, in the semiconductor device 1001, the first gate dielectric layer 131 includes a first portion 1311 located at a first sidewall of the first trench T1, a second portion 1312 located at a second sidewall of the first trench T1, and a third portion 1313 located at a bottom of the first trench T1, wherein the third portion 1313 is connected between the first portion 1311 and the second portion 1312.
The semiconductor device 1001 includes a third gate structure PG ', a fourth gate structure PG1', and two body regions 150 (i.e., a body region 150A and a body region 150B) located at both sides of the first gate structure 130.
The fourth gate structure PG1' is located at a side of the epitaxial region 120 away from the substrate 110, and the fourth gate structure PG1' includes a fourth gate PG1, and a fourth gate dielectric layer GOX ' located between the side of the epitaxial region 120 away from the substrate 110 and the fourth gate PG 1.
Here, the third gate structure PG' partially overlaps the first portion 1311 of the first gate dielectric layer 131 and partially overlaps the body region 150A. The fourth gate structure PG1' partially overlaps the second portion 1312 of the first gate dielectric layer 131 and partially overlaps the body region 150B. For example, a third gate dielectric layer GOX is in partial surface contact with the first portion 1311 and with a partial surface of the body region 150A, and a fourth gate dielectric layer GOX' is in partial surface contact with the second portion 1312 and overlaps with a partial surface of the body region 150B.
In some embodiments, the semiconductor device 1001 may include two doped regions 180A, 180B located on both sides of the first gate structure 130.
Doped region 180A is spaced apart from body region 150A by epitaxial region 120, and doped region 180A abuts first portion 1311 of first gate structure 130. Doped region 180B is spaced apart from body region 150B by epitaxial region 120, and doped region 180B abuts second portion 1312 of first gate structure 130. For example, one doped region 180B and one bulk region 150B located to the left of the first gate structure 130 may be separated by the epitaxial region 120 to the left of the first gate structure 130, and another doped region 180A and another bulk region 150A located to the right of the first gate structure 130 may be separated by the epitaxial region 120 to the right of the first gate structure 130.
As shown in fig. 10, if the actual positions of the third gate structure PG 'and the fourth gate structure PG1' are shifted left with respect to the expected positions, the body regions 150 located at both sides of the first gate structure 130 are shifted left accordingly. In this case, during the subsequent formation of the body region 150, the larger doped region 180B will be formed on the left side of the first gate structure 130 and the smaller doped region 180A or the undoped region 180A will be formed on the right side of the first gate structure 130, so that the dimension d1 of the epitaxial region 120 under the fourth gate structure PG1' in the second direction X and the dimension d2 of the epitaxial region 120 under the third gate structure PG ' in the second direction X can be substantially maintained, thereby reducing the adverse effect caused by the positional deviation of the third gate structure PG '.
It should be appreciated that if the actual positions of the third gate structure PG 'and the fourth gate structure PG1' are shifted to the right with respect to the expected positions, the body regions 150 located at both sides of the first gate structure 130 are shifted to the right accordingly. In this case, during the subsequent formation of the body region 150, the smaller doped region 180B or the undoped region 180B will be formed at the left side of the first gate structure 130, and the larger doped region 180A will be formed at the right side of the first gate structure 130, so that the dimension d1 of the epitaxial region 120 under the fourth gate structure PG1' in the second direction X and the dimension d2 of the epitaxial region 120 under the third gate structure PG ' in the second direction X can be substantially maintained unchanged, thereby reducing the adverse effect caused by the positional deviation of the third gate structure PG '.
It should also be appreciated that if the actual positions of the third gate structure PG 'and the fourth gate structure PG1' are not shifted with respect to the expected positions, then in this case, the dimension d1 of the epitaxial region 120 under the fourth gate structure PG1 'in the second direction X (the dimension of the epitaxial region 120 between the doped region 180B and the body region 150B) and the dimension d2 of the epitaxial region 120 under the third gate structure PG' in the second direction X (the dimension of the epitaxial region 120 between the doped region 180A and the body region 150A) will not change.
In some embodiments, referring to fig. 1A to 1B and fig. 8A to 8C, the semiconductor device 1000/1001 may further include a first spacer layer SP1 and a second spacer layer SP2 located at both sides of the third gate structure PG'. The first spacer layer SP1 is located on the surface of the first gate dielectric layer 131 and the second spacer layer SP2 is located on the surface of the body region 150. Thus, the first spacer layer SP1 does not extend to the surface of the first gate TG 1. In this way, adverse effects caused by too little silicide on the first gate TG1 can be further avoided.
In some embodiments, the semiconductor device 1000/1001 may further include a first silicide layer SA1, a second silicide layer SA2, a third silicide layer SA3, and a fourth silicide layer SA4. The first silicide layer SA1 is located on a surface of the first gate TG1 away from the substrate 110; the second silicide layer SA2 is located on a surface of the second gate TG2 away from the substrate 110; the third silicide layer SA3 is located on a surface of the third gate structure PG' away from the substrate 110; the fourth silicide layer SA4 is located on a side of the first electrode region 160 remote from the substrate 110.
In some embodiments, the material of one or more of the first, second, third, and fourth silicide layers SA1, SA2, SA3, and SA4 may include cobalt silicide, nickel silicide, tungsten silicide, titanium silicide, or the like.
In some embodiments, semiconductor device 1000/1001 may further include a metal layer 190 and an insulating layer 191. The metal layer 190 may be located on a side of the fourth silicide layer SA4 away from the substrate 110 and electrically coupled with the first electrode region 160 through the fourth silicide layer SA 4. The metal layer 190 and the third gate structure PG' are separated by an insulating layer 191. For example, the first electrode region 160 is a source region, and the metal layer 190 may serve as a source.
Fig. 11 is a flow chart of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. As shown in fig. 11, the manufacturing method of the semiconductor device includes steps 101 to 107. It should be noted that steps 101 to 107 may be sequentially performed in a sequence other than the sequence described later. For example, step 107 may be performed after step 101, i.e. step 107 may be performed before step 102.
The method of manufacturing the semiconductor device shown in fig. 11 is explained below with reference to fig. 12 to 27 for ease of understanding. Fig. 12-27 are cross-sectional views of various stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.
In step 101, a substrate 110 having a first conductivity type is provided.
As shown in fig. 12, the substrate 110 has opposing first and second surfaces 111, 112. In some embodiments, the material of the substrate 110 may be a semiconductor material such as silicon.
In step 102, an epitaxial region 120 having a first conductivity type is formed over a substrate 110, as shown in fig. 12. For example, an epitaxial region 120 having a first conductivity type is formed on the first surface 111 of the substrate 110. The first conductivity type may be one of N-type and P-type.
In step 103, a first gate structure 130 and a second gate structure 140 are formed in the epitaxial region 120.
Here, the first gate structure 130 includes a first gate TG1 at least partially located in the epitaxial region 120, and a first gate dielectric layer 131 located between the first gate TG1 and the epitaxial region 120. The second gate structure 140 includes a second gate TG2 at least partially located in the epitaxial region 120, and a second gate dielectric layer 141 located between the second gate TG2 and the epitaxial region 120.
In the direction from the epitaxial region 120 to the substrate 110, the depth h1 of the first gate TG1 in the epitaxial region 120 is greater than the depth h2 of the second gate TG2 in the epitaxial region 120.
In some embodiments, the extending direction of the first gate TG1 and the second gate TG2 is the first direction Y. The dimension w1 of the first gate TG1 in the second direction X is greater than the dimension w2 of the second gate TG2 in the second direction. The second direction X is perpendicular to the first direction Y.
Some embodiments of forming the first gate structure 130 and the second gate structure 140 are described next in connection with fig. 13-16.
In some embodiments, as shown in fig. 13, a first trench T1 and a second trench T2 may be formed in the epitaxial region 120.
Here, the depth h3 of the first trench T1 in the epitaxial region 120 is greater than the depth h4 of the second trench T2 in the epitaxial region 120 in the direction from the epitaxial region 120 to the substrate 110, i.e., the bottom of the first trench 130 is closer to the substrate 110 than the bottom of the second trench 140.
For example, the first and second trenches T1 and T2 having different depths may be formed in the epitaxial region 120 by a dry etching process. In some embodiments, the first trench T1 and the second trench T2 may be formed simultaneously by the same etching process to reduce the manufacturing cost of the semiconductor device and improve the manufacturing efficiency.
In some embodiments, referring to fig. 13, the extension direction of the first and second trenches T1 and T2 is the first direction Y. The dimension w3 of the first trench T1 in the second direction X is larger than the dimension w4 of the second trench T2 in the second direction.
As some implementations, the first gate structure 130 may be formed in the first trench T1 and the second gate structure 140 may be formed in the second trench T2 according to the steps S1 to S3 as follows.
S1: as shown in fig. 14, a dielectric material layer D is formed on the bottom and side walls of the first trench T1, the bottom and side walls of the second trench T2, and the side of the epitaxial region 120 away from the substrate 110.
For example, the dielectric material layer D may be formed using a chemical vapor deposition process.
In some embodiments, the thickness of dielectric material layer D may be about 0.2 microns.
S2: as shown in fig. 15, after the dielectric material layer D is formed, a conductive material is filled in the first trench T1 and the second trench T2 to form a first gate TG1 and a second gate TG2.
For example, the first and second trenches T1 and T2 formed with the dielectric material layer D may be filled with a conductive material using a chemical vapor deposition process to form the first and second gates TG1 and TG2. For example, the conductive material may include doped polysilicon or metal.
S3: as shown in fig. 16, a portion of dielectric material layer D at a side of epitaxial region 120 remote from substrate 110 is removed.
Here, after the removal is performed, the portions of the dielectric material layer D at the bottom and the sidewalls of the first trench T1 serve as the first gate dielectric layer 131, and the portions of the dielectric material layer D at the bottom and the sidewalls of the second trench T2 serve as the second gate dielectric layer 141. The first gate TG1 is surrounded by the first gate dielectric layer 131, and the second gate TG2 is surrounded by the second gate dielectric layer 141.
For example, portions of the dielectric material layer D at a side of the epitaxial region 120 remote from the substrate 110 may be removed by a planarization process or an etch-back process, thereby forming the first gate structure 130 and the second gate structure 140. The planarization process is, for example, a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP).
In some embodiments, the thicknesses of the first gate dielectric layer 131 and the second gate dielectric layer 141 are formed to be substantially the same.
In step 104, a third gate structure PG' is formed on a side of the epitaxial region 120 remote from the substrate 110.
In some embodiments, as shown in fig. 17, after forming the first gate structure 130 and the second gate structure 140, a doping process may be performed to form a well region J in the epitaxial region 120, and after forming the well region J, the third gate structure PG' may be formed. For example, the well region J may have a first conductivity type (e.g., N-type).
As some implementations, as shown in fig. 18, a third gate dielectric layer GOX may be formed on a side of the epitaxial region 120 away from the substrate 110, and then a third gate PG may be formed on a side of the third gate dielectric layer GOX away from the substrate 110, thereby forming a third gate structure PG' including the third gate dielectric layer GOX and the third gate PG.
In some embodiments, as shown in fig. 18, the third gate structure PG' is formed to partially overlap not only the body region 150 but also the first gate dielectric layer 131. In some embodiments, a size of an overlapping portion of the third gate structure PG' and the first gate dielectric layer 131 in the second direction X is less than or equal to 0.1 micrometers.
As shown in fig. 19, after forming the third gate structure PG', a doping process is performed to form a body region 150 having the second conductivity type in the epitaxial region 120 between the first gate structure 130 and the second gate structure 140 in step 105. For example, with the third gate structure PG ' as a mask, for a right side region of the third gate structure PG ', a doping material is incident in different directions such as a positive X direction, a negative X direction, a positive Y direction, a negative Y direction, etc. at an incident angle oblique to the Z direction, and a doping process is performed to form a body region 150 having the second conductivity type in the epitaxial region 120 under the right end point of the third gate structure PG ' and between the second gate structures 140.
Here, the body region 150 partially overlaps the third gate structure PG', and the body region 150 is spaced apart from the first gate dielectric layer 131. The second conductivity type is different from the first conductivity type.
In some embodiments, the body region 150 is contiguous with the second gate dielectric layer 141.
As shown in fig. 20, in some embodiments, the doping process performed in step 105 may also form doped regions 180 in epitaxial region 120. Doped region 180 abuts first gate dielectric layer 131, doped region 180 being spaced apart from body region 150 by epitaxial region 120. For example, the third gate structure PG 'and the fourth gate structure PG1' may be used as masks at the same time, and the doping material is incident in different directions of the positive X direction, the negative X direction, the positive Y direction, the negative Y direction, and the like with respect to the region between the third gate structure PG 'and the fourth gate structure PG1' at an incident angle oblique to the Z direction, and the doping region 180 is formed in the epitaxial region 120 adjacent to the first gate dielectric layer 131, and the doping region 180 is spaced apart from the body region 150 by the epitaxial region 120.
In this case, even if the actual position of the third gate structure PG ' formed in step 104 is shifted from the intended position, by forming the doped region 180, the dimension of the epitaxial region 120 under the third gate structure PG ' in the second direction X can be kept substantially unchanged, and the adverse effect of the shift in position of the third gate structure PG ' is reduced.
In step 106, a first electrode region 160 having a first conductivity type is formed in the body region 150.
In some embodiments, as shown in fig. 21, after step 105, lightly doped drain LDD regions having the first conductivity type may be formed in the body regions 150. For example, the first conductivity type is N-type, the second conductivity type is P-type, the body region 150 is a P-type body region, and the lightly doped drain region LDD is an N-type lightly doped drain region (NLDD).
In some embodiments, as shown in fig. 22, after forming the lightly doped region drain LDD, a first spacer layer SP1 and a second spacer layer SP2 may be formed at both sides of the third gate structure PG'. The first spacer layer SP1 is located on the surface of the first gate dielectric layer 131 and the second spacer layer SP2 is located on the surface of the body region 150. For example, the first and second spacer layers SP1 and SP2 may be formed on opposite sidewalls of the third gate structure PG' by a chemical vapor deposition process and a dry etching process.
In some embodiments, the material of the first and second spacer layers SP1 and SP2 may include silicon nitride or silicon oxide.
In some embodiments, as shown in fig. 23, the first electrode region 160 having the first conductive type may be formed in the body region 150 after the first and second spacer layers SP1 and SP2 are formed. For example, the first electrode region 160 may be a source region.
In some embodiments, a doped region 161 having the second conductivity type may also be formed in the body region 150. The doped region 161 adjoins the second gate structure 140, and the first electrode region 160 is located between the first gate structure 130 and the doped region 161. For example, a photolithography process and an ion implantation process may be performed to form the first electrode region 160 and the doped region 161 in the body region 150.
In step 107, a second electrode 170 is formed under the substrate 110. For example, the second electrode 170 is formed on the second surface 112 of the substrate 110 facing away from the first surface 111. For example, the second electrode 170 is a drain electrode, and the first electrode region 160 is a source region.
In this way, the semiconductor device is manufactured to have the first gate TG1 and the second gate TG2 having different depths, and since the first gate TG1 and the second gate TG2 having different depths change the electric field structure in the epitaxial region 120, when avalanche breakdown occurs in the semiconductor device, the semiconductor device can be concentrated to the first electrode region 160 through the shortest path between the second electrode 170 and the first electrode region 160 (i.e., via the region closer to the second gate structure TG2 in the epitaxial region), so that the possibility of conduction of parasitic transistors inside the semiconductor device is reduced, thereby improving avalanche resistance of the semiconductor device and reducing the possibility of device damage.
In the related art, at least one of the first gate TG1 and the second gate TG2 is doped during the formation of the first electrode region 160 in the body region 150. In order to avoid the conductive material or the dopant doped in the first electrode region 160 from diffusing to a deeper portion of the body region 150 during the annealing process, the annealing time is limited (for example, limited to 10 to 20 seconds), which results in uneven diffusion of the doped dopant in the first gate TG1 and the second gate TG2, and the upper half of the first gate TG1 and the second gate TG2 has a higher dopant content than the lower half, so that the deeper portions of the first gate TG1 and the second gate TG2 have a higher resistance, thereby resulting in poor performance of the first gate TG1 and the second gate TG 2.
In view of this, the disclosed embodiments also provide the following solutions.
In some embodiments, at least one of the first gate TG1 and the second gate TG2 may be doped. For example, the first gate TG1 or the second gate TG2 may be doped. For another example, both the first gate TG1 and the second gate TG2 may be doped.
In some embodiments, as shown in fig. 18, in step 105, a body region 150 may be formed in the epitaxial region 120 by performing a doping process, and a first anneal may be performed after forming the body region 150. In these embodiments, at least one of the first gate TG1 and the second gate TG2 may be doped prior to forming the body region 150.
In the above embodiment, doping of at least one of the first gate TG1 and the second gate TG2 is performed before forming the body region 150. As such, since the first annealing is performed after the formation of the body region 150, the dopant doping at least one of the first and second gate TG1 and TG2 may be diffused deeper into the gate by the first annealing, thereby enabling more uniform diffusion of the dopant doping in at least one of the first and second gate TG1 and TG2 without affecting the subsequently formed first electrode region 160 in the body region 150, improving the performance of at least one of the first and second gate TG1 and TG2, and thus improving the performance of the fabricated semiconductor device.
In some embodiments, after forming the third gate dielectric layer GOX, a second anneal may be performed, after which the third gate PG is formed. In these embodiments, at least one of the first gate TG1 and the second gate TG2 may be doped before forming the third gate dielectric layer GOX.
In the above-described embodiment, the doping of at least one of the first gate TG1 and the second gate TG2 is performed before the formation of the third gate dielectric layer GOX. As such, since the body region 150 is formed after the third gate dielectric layer GOX is formed, and the second annealing is performed after the third gate dielectric layer GOX is formed, and the first annealing is performed after the body region 150 is formed, the conductive material or the dopant, etc. doped to at least one of the first gate TG1 and the second gate TG2 may be diffused deeper into the gate by the two anneals (i.e., the first annealing and the second annealing), thereby further improving the performance of at least one of the first gate TG1 and the second gate TG2 without affecting the first electrode region 160 formed in the body region 150 later, and further improving the performance of the manufactured semiconductor device.
In some embodiments, as shown in fig. 24, after forming the first spacer layer SP1 and the second spacer layer SP2, the first silicide layer SA1, the second silicide layer SA2, the third silicide layer SA3, and the fourth silicide layer SA4 may be formed. The first silicide layer SA1 is located on a side of the first gate TG1 away from the substrate 110, the second silicide layer SA2 is located on a side of the second gate TG2 away from the substrate 110, the third silicide layer SA3 is located on a side of the third gate structure PG' away from the substrate 110, and the fourth silicide layer SA4 is located on a side of the first electrode region 160 away from the substrate 110.
In some embodiments, the materials of the first, second, third, and fourth silicide layers SA1, SA2, SA3, and SA4 may include cobalt silicide, nickel silicide, tungsten silicide, titanium silicide, or the like.
In this way, after the first spacer layer SP1 and the second spacer layer SP2 are formed, the first silicide layer SA1, the second silicide layer SA2, the third silicide layer SA3 and the fourth silicide layer SA4 can be correspondingly formed on the surface of the first gate TG1 away from the substrate 110, the surface of the second gate TG2 away from the substrate 110, the surface of the third gate structure PG' away from the substrate 110, and the surface of the first electrode region 160 away from the substrate 110, without an additional photomask, thereby simplifying the manufacturing process of the semiconductor device and improving the manufacturing efficiency of the semiconductor device.
In some embodiments, as shown in fig. 25, an insulating layer 191 covering the first, second, third, and fourth silicide layers SA1, SA2, SA3, and SA4 may be formed on a side of the epitaxial region 120 away from the substrate 110.
In some embodiments, as shown in fig. 26, a metal layer 190 may be formed in the insulating layer 191. The metal layer 190 may be located on a side of the fourth silicide layer SA4 away from the substrate 110 and electrically coupled with the first electrode region 160 through the fourth silicide layer SA 4. The metal layer 190 and the third gate structure PG' are separated by an insulating layer 191. For example, the first electrode region 160 is a source region, and the metal layer 190 may serve as a source.
In some embodiments, as shown in fig. 27, step 107 may be performed after forming metal layer 190 to form second electrode 170 on second surface 112 of substrate 110. For example, the metal layer 190 is a source and the second electrode 170 is a drain.
Fig. 28 is a flow chart of a method of manufacturing a semiconductor device according to further embodiments of the present disclosure. As shown in fig. 28, the manufacturing method of the semiconductor device includes steps 201 to 208. It should be noted that, steps 201 to 208 may be sequentially performed in a sequence other than the sequence described later. For example, step 208 may be performed after step 201, i.e. step 208 may be performed before step 202. The method of manufacturing the semiconductor device shown in fig. 28 will be described with reference to fig. 12 to 27.
In step 201, a substrate 110 having a first conductivity type is provided.
As shown in fig. 12, the substrate 110 has opposing first and second surfaces 111, 112. In some embodiments, the material of the substrate 110 may be a semiconductor material such as silicon.
At step 202, an epitaxial region 120 having a first conductivity type is formed over a substrate 110, as shown in fig. 12. The first conductivity type may be one of N-type and P-type.
In step 203, as shown in fig. 13, a first trench T1 is formed in the epitaxial region 120.
For example, the first trench T1 may be formed in the epitaxial region 120 by a dry etching process. In some embodiments, a second trench T2 is also formed in the epitaxial region 120.
In step 204, the first gate structure 130 is formed in the first trench T1.
Here, the first gate structure 130 includes a first gate TG1 located in the first trench T1, and a first gate dielectric layer 131 located between the first gate TG1 and the epitaxial region 120.
The first gate dielectric layer 131 may include a first portion 1311 located at a first sidewall of the first trench T1, a second portion 1312 located at a second sidewall of the first trench T1, and a third portion 1313 located at a bottom of the first trench T1, wherein the third portion 1313 is connected between the first portion 1311 and the second portion 1312.
As some implementations, as shown in fig. 14 to 16, the first gate structure 130 may be formed in the first trench T1 in the manner shown in the foregoing steps S1 to S3, and the detailed description may refer to the related description in the foregoing steps S1 to S3, which is not repeated herein.
In step 205, a third gate structure PG' is formed on a side of epitaxial region 120 remote from substrate 110.
In some embodiments, as shown in fig. 17, after forming the first gate structure 130, a doping process may be performed to form a well region J in the epitaxial region 120, and after forming the well region J, a third gate structure PG' may be formed.
As some implementations, as shown in fig. 18, a third gate dielectric layer GOX may be formed on a side of the epitaxial region 120 away from the substrate 110, and then a third gate PG may be formed on a side of the third gate dielectric layer GOX away from the substrate 110, thereby forming a third gate structure PG' including the third gate dielectric layer GOX and the third gate PG.
Here, as shown in fig. 18, the third gate structure PG' is formed to partially overlap not only the body region 150 but also the first gate dielectric layer 131. In some embodiments, a size of an overlapping portion of the third gate structure PG' and the first gate dielectric layer 131 in the second direction X is less than or equal to 0.1 micrometers.
At step 206, after forming the third gate structure PG', a doping process is performed to form the body region 150 and the doped region 180 having the second conductivity type in the epitaxial region 120, as shown in fig. 19 and 20.
Here, the body region 150 partially overlaps the third gate structure PG' and is spaced apart from the first gate dielectric layer 130. Doped region 180 abuts first gate dielectric layer 131, doped region 180 being spaced apart from body region 150 by epitaxial region 120. The second conductivity type is different from the first conductivity type.
In step 207, a first electrode region 160 having a first conductivity type is formed in the body region 150.
In some embodiments, as shown in fig. 21, after step 105, lightly doped drain LDD regions having the first conductivity type may be formed in the body regions 150.
In some embodiments, as shown in fig. 22, after forming the lightly doped region drain LDD, a first spacer layer SP1 and a second spacer layer SP2 may be formed at both sides of the third gate structure PG'. The first spacer layer SP1 is located on the surface of the first gate dielectric layer 131 and the second spacer layer SP2 is located on the surface of the body region 150.
In some embodiments, as shown in fig. 23, the first electrode region 160 having the first conductive type may be formed in the body region 150 after the first and second spacer layers SP1 and SP2 are formed.
In some embodiments, a doped region 161 having the second conductivity type may also be formed in the body region 150. The doped region 161 adjoins the second gate structure 140, and the first electrode region 160 is located between the first gate structure 130 and the doped region 161.
At step 208, a second electrode 170 is formed under the substrate 110. For example, the second electrode 170 is a drain electrode, and the first electrode region 160 is a source region.
In this manner, the third gate structure PG 'of the fabricated semiconductor device partially overlaps the first gate dielectric layer 131, helping to reduce adverse effects on the semiconductor device in the event that the actual position of the third gate structure PG' is offset from the intended position.
In some embodiments, after forming the first spacer layer SP1 and the second spacer layer SP2, the first silicide layer SA1, the third silicide layer SA3, and the fourth silicide layer SA4 may be formed. The first silicide layer SA1 is located on a side of the first gate TG1 away from the substrate 110, the third silicide layer SA3 is located on a side of the third gate structure PG' away from the substrate 110, and the fourth silicide layer SA4 is located on a side of the first electrode region 160 away from the substrate 110.
In this way, after the first spacer layer SP1 and the second spacer layer SP2 are formed, the first silicide layer SA1, the third silicide layer SA3 and the fourth silicide layer SA4 can be correspondingly formed on the surface of the first gate TG1 away from the substrate 110, the surface of the third gate structure PG' away from the substrate 110 and the surface of the first electrode region 160 away from the substrate 110 without an additional photomask, thereby simplifying the manufacturing process of the semiconductor device and improving the manufacturing efficiency of the semiconductor device.
In some embodiments, after forming the third gate structure PG', performing a doping process may form two body regions 150 having the second conductivity type in the epitaxial region 120.
In some embodiments, a fourth gate structure PG1 may also be formed on a side of the epitaxial region 120 remote from the substrate 110. The fourth gate structure PG1 'includes a fourth gate PG1 and a fourth gate dielectric layer GOX' between the side of the epitaxial region 120 remote from the substrate 110 and the fourth gate PG1. In these embodiments, the third gate structure PG' partially overlaps the first portion 1311 of the first gate dielectric layer 131 and partially overlaps one body region 150 of the two body regions 150. The fourth gate structure PG1' partially overlaps the second portion 1312 of the first gate dielectric layer 131 and partially overlaps the other one 150 of the two body regions 150. It should be understood that the fourth gate structure PG1 'is formed in a similar manner to the third gate structure PG', and will not be described herein.
In some embodiments, two doped regions 180 may be formed in epitaxial region 120 by performing a doping process. One doped region 180 of the two doped regions 180 is spaced apart from one body region 150 of the two body regions 150 by the epitaxial region 120, and the one doped region 180 is contiguous with the first portion 1311 of the first gate structure 130; the other doped region 180 of the two doped regions 180 is spaced apart from the other body region 150 of the two body regions 150 by the epitaxial region 120, and the other doped region 180 is contiguous with the second portion 1312 of the first gate structure 130.
The method for manufacturing the semiconductor device shown in fig. 28 may further include other steps for forming other structures, and the detailed description will be given with reference to the foregoing description of the related embodiments in fig. 11 and fig. 12 to 27, which are not repeated herein.
The semiconductor device and the manufacturing method thereof provided by the embodiment of the disclosure can be used in combination. Thus, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concepts of the present disclosure, some details known in the art are not described. How to implement the solutions disclosed herein will be fully apparent to those skilled in the art from the above description.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that the foregoing embodiments may be modified and equivalents substituted for elements thereof without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (27)
1. A semiconductor device, comprising:
A substrate (110) having a first conductivity type;
an epitaxial region (120) of a first conductivity type over the substrate (110);
-a first trench (T1) and a second trench (T2) both located in the epitaxial region (120), wherein the depth of the first trench (T1) in the epitaxial region (120) is greater than the depth of the second trench (T2) in the epitaxial region (120) in a direction from the epitaxial region (120) to the substrate (110);
a first gate structure (130) comprising a first gate (TG 1) at least partially located in the first trench (T1), and a first gate dielectric layer (131) located between the first gate (TG 1) and the epitaxial region (120);
-a second gate structure (140) comprising a second gate (TG 2) at least partly located in the second trench (T2), and a second gate dielectric layer (141) located between the second gate (TG 2) and the epitaxial region (120);
-a body region (150) of a second conductivity type located in the epitaxial region (120) between the first gate structure (130) and the second gate structure (140), the body region (150) being spaced apart from the first gate dielectric layer (131) and contiguous with the second gate dielectric layer (141), the second conductivity type being different from the first conductivity type;
A first electrode region (160) of a first conductivity type located in the body region (150);
a third gate structure (PG') located on a side of the epitaxial region (120) remote from the substrate (110) and partially overlapping the body region (150);
a second electrode (170) located under the substrate (110);
wherein a region of the epitaxial region (120) through which a current path flows when the semiconductor device is normally turned on is closer to the first gate structure (130) than the second gate structure (140), and a region of the epitaxial region (120) through which a current path flows when the semiconductor device is avalanche broken down is closer to the second gate structure (140) than the first gate structure (130).
2. A semiconductor device, comprising:
a substrate (110) having a first conductivity type;
an epitaxial region (120) of a first conductivity type over the substrate (110);
a first trench (T1) and a second trench (T2) both located in the epitaxial region (120), wherein a bottom of the first trench (T1) is closer to the substrate (110) than a bottom of the second trench (T2);
a first gate structure (130) comprising a first gate (TG 1) at least partially located in the first trench (T1), and a first gate dielectric layer (131) located between the first gate (TG 1) and the epitaxial region (120);
-a second gate structure (140) comprising a second gate (TG 2) located at least partly in the second trench (T2), and a second gate dielectric layer (141) located between the second gate (TG 2) and the epitaxial region (120), the second gate dielectric layer (141) having the same thickness as the first gate dielectric layer (131);
-a body region (150) of a second conductivity type located in the epitaxial region (120) between the first gate structure (130) and the second gate structure (140), the body region (150) being spaced apart from the first gate dielectric layer (131) and contiguous with the second gate dielectric layer (141), the second conductivity type being different from the first conductivity type;
a first electrode region (160) of a first conductivity type located in the body region (150);
a third gate structure (PG') located on a side of the epitaxial region (120) remote from the substrate (110) and partially overlapping the body region (150);
a second electrode (170) located under the substrate (110);
wherein a region of the epitaxial region (120) through which a current path flows when the semiconductor device is normally turned on is closer to the first gate structure (130) than the second gate structure (140), and a region of the epitaxial region (120) through which a current path flows when the semiconductor device is avalanche broken down is closer to the second gate structure (140) than the first gate structure (130).
3. The device according to claim 1 or 2, wherein the extension direction of the first trench (T1) and the second trench (T2) is a first direction (Y), the dimension of the first trench (T1) in a second direction (X) being larger than the dimension of the second trench (T2) in the second direction, the second direction (X) being perpendicular to the first direction (Y).
4. A semiconductor device, comprising:
a substrate (110) having a first conductivity type;
an epitaxial region (120) of a first conductivity type over the substrate (110);
-a first gate structure (130) comprising a first gate (TG 1) at least partly located in the epitaxial region (120), and a first gate dielectric layer (131) located between the first gate (TG 1) and the epitaxial region (120);
a second gate structure (140) comprising a second gate (TG 2) located at least partially in the epitaxial region (120), and a second gate dielectric layer (141) located between the second gate (TG 2) and the epitaxial region (120), wherein a depth of the first gate (TG 1) in the epitaxial region (120) is greater than a depth of the second gate (TG 2) in the epitaxial region (120) in a direction from the epitaxial region (120) to the substrate (110);
-a body region (150) of a second conductivity type located in the epitaxial region (120) between the first gate structure (130) and the second gate structure (140), the body region (150) being spaced apart from the first gate dielectric layer (131) and contiguous with the second gate dielectric layer (141), the second conductivity type being different from the first conductivity type;
a first electrode region (160) of a first conductivity type located in the body region (150);
a third gate structure (PG') located on a side of the epitaxial region (120) remote from the substrate (110) and partially overlapping the body region (150);
a second electrode (170) located under the substrate (110);
wherein a region of the epitaxial region (120) through which a current path flows when the semiconductor device is normally turned on is closer to the first gate structure (130) than the second gate structure (140), and a region of the epitaxial region (120) through which a current path flows when the semiconductor device is avalanche broken down is closer to the second gate structure (140) than the first gate structure (130).
5. The device of claim 4, wherein the extension direction of the first gate (TG 1) and the second gate (TG 2) is a first direction (Y), the first gate (TG 1) having a larger dimension in a second direction (X) than the second gate (TG 2), the second direction (X) being perpendicular to the first direction (Y).
6. The device of any of claims 1-2, 4-5, wherein the third gate structure (PG') comprises:
a third gate (PG); and
a third gate dielectric layer (GOX) located between a side of the epitaxial region (120) remote from the substrate (110) and the third gate (PG);
wherein the third gate structure (PG') overlaps partially with the first gate dielectric layer (131).
7. The device of claim 6, wherein the third gate structure (PG') does not overlap the first gate (TG 1).
8. The device of claim 6, wherein the extension direction of the third gate structure (PG ') is a first direction (Y), and the overlapping portion of the third gate structure (PG') and the first gate dielectric layer (131) has a dimension in a second direction (X) that is perpendicular to the first direction (Y) of less than or equal to 0.1 micrometer.
9. The device of claim 6, further comprising:
a doped region (180) of a second conductivity type is located in the epitaxial region (120) and adjacent to the first gate dielectric layer (131), the doped region (180) being spaced apart from the body region (150) by the epitaxial region (120).
10. The device of claim 9, wherein the first gate dielectric layer (131) comprises a first portion (1311) located at a first sidewall of a first trench (T1) where the first gate (TG 1) is located, a second portion (1312) located at a second sidewall of the first trench (T1), and a third portion (1313) located at a bottom of the first trench (T1), the third portion (1313) being connected between the first portion (1311) and the second portion (1312);
the device comprises two body regions (150) located on both sides of the first gate structure (130), the third gate structure (PG') partially overlapping the first portion (1311) and partially overlapping one of the two body regions (150);
the device further comprises:
-a fourth gate structure (PG 1 ') comprising a fourth gate (PG 1) on a side of the epitaxial region (120) remote from the substrate (110), and a fourth gate dielectric layer (GOX ') between the side of the epitaxial region (120) remote from the substrate (110) and the fourth gate (PG 1), the fourth gate structure (PG 1 ') partially overlapping the second portion (1312) and partially overlapping the other of the two body regions (150).
11. The device of claim 10, wherein the device comprises two of the doped regions (180) located on both sides of the first gate structure (130);
one of the two doped regions (180) is spaced apart from one of the two body regions (150) by the epitaxial region (120) and adjoins the first portion (1311);
the other of the two doped regions (180) is spaced apart from the other of the two body regions (150) by the epitaxial region (120) and adjoins the second portion (1312).
12. The device of claim 6, further comprising:
-a first spacer layer (SP 1) and a second spacer layer (SP 2) on both sides of the third gate structure (PG'), the first spacer layer (SP 1) being located on a surface of the first gate dielectric layer (131), the second spacer layer (SP 2) being located on a surface of the body region (150).
13. The device of any one of claims 1, 2, 4, 5, wherein:
the first conductivity type is N type, and the second conductivity type is P type;
the first electrode region (160) is a source region and the second electrode (170) is a drain.
14. A method of manufacturing a semiconductor device, comprising:
providing a substrate (110) having a first conductivity type;
forming an epitaxial region (120) having a first conductivity type over the substrate (110);
forming a first trench (T1) and a second trench (T2) in the epitaxial region (120), wherein a depth of the first trench (T1) in the epitaxial region (120) is greater than a depth of the second trench (T2) in the epitaxial region (120) in a direction from the epitaxial region (120) to the substrate (110);
-forming a first gate structure (130) in the first trench (T1), and-forming a second gate structure (140) in the second trench (T2), the first gate structure (130) comprising a first gate (TG 1) at least partly located in the first trench (T1), and a first gate dielectric layer (131) located between the first gate (TG 1) and the epitaxial region (120), the second gate structure (140) comprising a second gate (TG 2) at least partly located in the second trench (T2), and a second gate dielectric layer (141) located between the second gate (TG 2) and the epitaxial region (120);
-forming a third gate structure (PG') on a side of the epitaxial region (120) remote from the substrate (110);
after forming the third gate structure (PG '), performing a doping process to form a body region (150) of a second conductivity type in the epitaxial region (120) between the first gate structure (130) and the second gate structure (140), the body region (150) partially overlapping the third gate structure (PG'), the body region (150) being spaced apart from the first gate dielectric layer (131) and adjoining the second gate dielectric layer (141), the second conductivity type being different from the first conductivity type;
-forming a first electrode region (160) of a first conductivity type in the body region (150);
forming a second electrode (170) under the substrate (110);
wherein a region of the epitaxial region (120) through which a current path flows when the semiconductor device is normally turned on is closer to the first gate structure (130) than the second gate structure (140), and a region of the epitaxial region (120) through which a current path flows when the semiconductor device is avalanche broken down is closer to the second gate structure (140) than the first gate structure (130).
15. A method of manufacturing a semiconductor device, comprising:
providing a substrate (110) having a first conductivity type;
forming an epitaxial region (120) having a first conductivity type over the substrate (110);
forming a first trench (T1) and a second trench (T2) in the epitaxial region (120), wherein a bottom of the first trench (T1) is closer to the substrate (110) than a bottom of the second trench (T2);
-forming a first gate structure (130) in the first trench (T1), and-forming a second gate structure (140) in the second trench (T2), the first gate structure (130) comprising a first gate (TG 1) at least partly located in the first trench (T1), and a first gate dielectric layer (131) located between the first gate (TG 1) and the epitaxial region (120), the second gate structure (140) comprising a second gate (TG 2) at least partly located in the second trench (T2), and a second gate dielectric layer (141) located between the second gate (TG 2) and the epitaxial region (120), the second gate dielectric layer (141) having the same thickness as the first gate dielectric layer (131);
-forming a third gate structure (PG') on a side of the epitaxial region (120) remote from the substrate (110);
after forming the third gate structure (PG '), performing a doping process to form a body region (150) of a second conductivity type in the epitaxial region (120) between the first gate structure (130) and the second gate structure (140), the body region (150) partially overlapping the third gate structure (PG'), the body region (150) being spaced apart from the first gate dielectric layer (131) and adjoining the second gate dielectric layer (141), the second conductivity type being different from the first conductivity type;
-forming a first electrode region (160) of a first conductivity type in the body region (150);
forming a second electrode (170) under the substrate (110);
wherein a region of the epitaxial region (120) through which a current path flows when the semiconductor device is normally turned on is closer to the first gate structure (130) than the second gate structure (140), and a region of the epitaxial region (120) through which a current path flows when the semiconductor device is avalanche broken down is closer to the second gate structure (140) than the first gate structure (130).
16. Method according to claim 14 or 15, wherein the extension direction of the first trench (T1) and the second trench (T2) is a first direction (Y), the dimension of the first trench (T1) in a second direction (X) being larger than the dimension of the second trench (T2) in the second direction, the second direction (X) being perpendicular to the first direction (Y).
17. The method of claim 14 or 15, wherein forming a first gate structure (130) in the first trench (T1) and forming a second gate structure (140) in the second trench (T2) comprises:
forming a dielectric material layer (D) on the bottom and side walls of the first trench (T1), the bottom and side walls of the second trench (T2), and a side of the epitaxial region (120) away from the substrate (110);
filling a conductive material in the first trench (T1) and the second trench (T2) after forming the dielectric material layer (D) to form the first gate (TG 1) and the second gate (TG 2);
-removing portions of the dielectric material layer (D) at a side of the epitaxial region (120) remote from the substrate (110), the portions of the dielectric material layer (D) at the bottom and sidewalls of the first trench (T1) being the first gate dielectric layer (131), and the portions of the dielectric material layer (D) at the bottom and sidewalls of the second trench (T2) being the second gate dielectric layer (141).
18. A method of manufacturing a semiconductor device, comprising:
providing a substrate (110) having a first conductivity type;
forming an epitaxial region (120) having a first conductivity type over the substrate (110);
-forming a first gate structure (130) and a second gate structure (140) in the epitaxial region (120), the first gate structure (130) comprising a first gate (TG 1) at least partly located in the epitaxial region (120) and a first gate dielectric layer (131) located between the first gate (TG 1) and the epitaxial region (120), the second gate structure (140) comprising a second gate (TG 2) at least partly located in the epitaxial region (120) and a second gate dielectric layer (141) located between the second gate (TG 2) and the epitaxial region (120), wherein the depth of the first gate (TG 1) in the epitaxial region (120) is greater than the depth of the second gate (TG 2) in the epitaxial region (120) in a direction from the epitaxial region (120) to the substrate (110);
-forming a third gate structure (PG') on a side of the epitaxial region (120) remote from the substrate (110);
After forming the third gate structure (PG '), performing a doping process to form a body region (150) of a second conductivity type in the epitaxial region (120) between the first gate structure (130) and the second gate structure (140), the body region (150) partially overlapping the third gate structure (PG'), the body region (150) being spaced apart from the first gate dielectric layer (131) and adjoining the second gate dielectric layer (141), the second conductivity type being different from the first conductivity type;
-forming a first electrode region (160) of a first conductivity type in the body region (150);
forming a second electrode (170) under the substrate (110);
wherein a region of the epitaxial region (120) through which a current path flows when the semiconductor device is normally turned on is closer to the first gate structure (130) than the second gate structure (140), and a region of the epitaxial region (120) through which a current path flows when the semiconductor device is avalanche broken down is closer to the second gate structure (140) than the first gate structure (130).
19. The method according to claim 18, wherein the extension direction of the first gate (TG 1) and the second gate (TG 2) is a first direction (Y), the first gate (TG 1) having a larger dimension in a second direction (X) than the second gate (TG 2), the second direction (X) being perpendicular to the first direction (Y).
20. The method of any of claims 14-15, 18-19, further comprising:
at least one of the first gate (TG 1) and the second gate (TG 2) is doped.
21. The method of claim 20, wherein at least one of the first gate (TG 1) and the second gate (TG 2) is doped prior to forming the body region (150);
the method further comprises the steps of:
after forming the body region (150), a first anneal is performed.
22. The method of claim 21, wherein the forming a third gate structure (PG') comprises:
forming a third gate dielectric layer (GOX) on a side of the epitaxial region (120) remote from the substrate (110);
performing a second anneal after forming the third gate dielectric layer (GOX);
forming a third gate (PG) on a side of the third gate dielectric layer (GOX) remote from the substrate (110);
wherein at least one of the first gate (TG 1) and the second gate (TG 2) is doped prior to forming the third gate dielectric layer (GOX).
23. The method of any of claims 14-15, 18-19, wherein the third gate structure (PG') comprises:
A third gate (PG); and
a third gate dielectric layer (GOX) located between a side of the epitaxial region (120) remote from the substrate (110) and the third gate (PG);
wherein the third gate structure (PG') overlaps partially with the first gate dielectric layer (131).
24. The method of claim 23, wherein the extension direction of the third gate structure (PG ') is a first direction (Y), and a size of an overlapping portion of the third gate structure (PG') with the first gate dielectric layer (131) in a second direction (X) is less than or equal to 0.1 micrometers, the second direction (X) being perpendicular to the first direction (Y).
25. The method according to claim 23, wherein:
the doping process also forms a doped region (180) in the epitaxial region (120), the doped region (180) being contiguous with the first gate dielectric layer (131), the doped region (180) being spaced apart from the body region (150) by the epitaxial region (120).
26. The method of claim 23, further comprising:
a first spacer layer (SP 1) and a second spacer layer (SP 2) are formed on both sides of the third gate structure (PG'), the first spacer layer (SP 1) being located on a surface of the first gate dielectric layer (131), and the second spacer layer (SP 2) being located on a surface of the body region (150).
27. The method of claim 26, further comprising:
after forming the first spacer layer (SP 1) and the second spacer layer (SP 2), forming a first silicide layer (SA 1), a second silicide layer (SA 2), a third silicide layer (SA 3), and a fourth silicide layer (SA 4);
the first silicide layer (SA 1) is located on one surface of the first grid electrode (TG 1) far away from the substrate (110), the second silicide layer (SA 2) is located on one surface of the second grid electrode (TG 2) far away from the substrate (110), the third silicide layer (SA 3) is located on one surface of the third grid electrode structure (PG') far away from the substrate (110), and the fourth silicide layer (SA 4) is located on one surface of the first electrode region (160) far away from the substrate (110).
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