CN109524472A - New power MOSFET element and preparation method thereof - Google Patents
New power MOSFET element and preparation method thereof Download PDFInfo
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- CN109524472A CN109524472A CN201811629070.8A CN201811629070A CN109524472A CN 109524472 A CN109524472 A CN 109524472A CN 201811629070 A CN201811629070 A CN 201811629070A CN 109524472 A CN109524472 A CN 109524472A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 119
- 239000002184 metal Substances 0.000 claims abstract description 119
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 368
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 19
- 239000012790 adhesive layer Substances 0.000 claims description 19
- 239000010936 titanium Substances 0.000 claims description 19
- 229910052719 titanium Inorganic materials 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 239000003292 glue Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000011982 device technology Methods 0.000 abstract description 2
- 230000001737 promoting effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 230000008901 benefit Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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Abstract
The invention belongs to semiconductor power device technology fields, specifically related to a kind of new power MOSFET element and preparation method thereof, device includes drain metal region layer, N+ monocrystalline substrate, N- epitaxial layer, P type trap zone layer, N+ source area, insulating medium layer, source level metal region layer, further includes groove；First gate oxide and the second gate oxide；First polysilicon layer and the second polysilicon layer and contact hole.The present invention also provides the preparation methods of the device, while possessing lower Qgd the invention enables device, also possess lower conducting resistance, and preparation method improves the market competitiveness, and have promotional value without increasing new cost.
Description
Technical field
The invention belongs to semiconductor power device technology fields, and in particular to a kind of new power MOSFET element and its
Preparation method.
Background technique
In power device, power MOSFET is had been widely used due to its superior function.Power MOSFET
Energy loss mainly includes switching loss and on-state loss, thus for the switching loss for how reducing power MOSFET device and
On-state loss generates many different device architectures and solution.Devclopment of Power MOSFET ' so far, at present for low pressure applications
Field mainly uses groove MOSFET device structure (being the mutation of groove structure comprising new structures such as split-gate), and right
In middle pressure application field be mainly then VDMOS, but the shortcomings that this two kinds of device architectures have inherently.
Though for groove MOSFET device structure, it has on state resistance more lower than VDMOS, due to groove type power MOS
There are biggish parasitic capacitances, i.e. gate-source capacitance Cgs and gate-drain capacitance Cgd between gate-drain between gate-source for device.
For power MOS pipe when on and off two states are converted, the voltage change of Cgd is much larger than the voltage change on Cgs, fill accordingly,
Discharge capacity Qgd is larger, so Qgd is affected to switching speed, also means that higher switching loss, and since it has
The influence of source region field distribution causes its breakdown voltage to be unable to satisfy higher requirement；Though and being directed to VDMOS has higher breakdown
Voltage and lower Qgd, but due to the influence of JEFET zone resistance, conduction loss is more than groove type power MOS device
It is high, it is therefore desirable to which that bigger device area meets lesser conduction loss.
In the today for advocating energy-saving and emission-reduction, low-carbon, the switching loss and conducting of power MOSFET device how are reduced simultaneously
Loss, so that there is device good high frequency characteristics and lower power loss to become the effort of those skilled in the art
Direction.
To solve the above-mentioned problems, the present invention provides a kind of new power MOSFET elements and preparation method thereof.
Summary of the invention
It is an object of the invention to solve at least one above problem or defect, and at least one is provided and will be described later
The advantages of.
It is a still further object of the present invention to provide a kind of new power MOSFET elements, device are possessed lower
While Qgd, also possess lower conducting resistance.
It is a still further object of the present invention to provide a kind of new power MOSFET elements, and which reduce MOSFET elements
Switching loss.
It is a still further object of the present invention to provide a kind of preparation method of new power MOSFET element, preparation processes
On the basis of structure novel, there can be lower power damage without increasing cost with existing MOSFET process compatible completely
Consumption, good electrical characteristics and reliability.
In order to realize these purposes and other advantages according to the present invention, the present invention provides a kind of new power MOSFET
Device including drain metal region layer, the N+ monocrystalline substrate above the drain metal region layer, is located at the N+ monocrystalline silicon
N- epitaxial layer above substrate, the P type trap zone layer above the N- epitaxial layer, the N+ above the P type trap zone layer
Source area, the insulating medium layer above the N+ source area and the source level metal area above the insulating medium layer
Layer, further includes:
Groove passes through the P type trap zone layer and the N+ source area, extends to the inside of the N- epitaxial layer；
Gate oxide comprising the first gate oxide and the second gate oxide, first gate oxide and the groove
Medial surface and bottom end contact, second gate oxide is located at the top of the N- epitaxial layer and the P type trap zone layer；
Polysilicon layer comprising the first polysilicon layer and the second polysilicon layer, first polysilicon layer are located at the ditch
It in slot, is contacted with first gate oxide, second polysilicon layer is located at the top of second gate oxide, and described
The contact of second gate oxide；
Contact hole passes through the insulating medium layer and N+ source area, extends to the P type trap zone layer, the contact hole
Inside be filled with metal.
Wherein, the source metal region layer is MOSFET element source metal electrode, and the drain metal region layer is
MOSFET element drain metal electrode.
Preferably, the metal is metal layer, and the metal layer sequentially consists of Titanium adhesive layer, titanium nitride
Barrier layer and tungsten metal layer；
Wherein, the metal layer and the P type trap zone layer and the N+ source region contact form ohmic contact layer, described
Metal layer is contacted with the source metal region layer.
Preferably, second gate oxide and second polysilicon layer form VDMOS gate structure, the groove
Positioned at the middle position of two VDMOS gate structures, the contact hole is located at the VDMOS gate structure and the groove
It is intermediate.
Preferably, the insulating medium layer is one of silicon dioxide layer and silicon nitride layer or two kinds.
Preferably, the N+ monocrystalline substrate is the N+ monocrystalline substrate of high-dopant concentration, and the N- epitaxial layer is low
The N- epitaxial layer of doping concentration.
The present invention also provides a kind of preparation methods of new power MOSFET element, comprising the following steps:
One layer of exposure mask oxide layer is grown on the surface for the N- epitaxial layer being located above N+ monocrystalline substrate, and is covered to described
Film oxide layer carries out photoetching, defines the trench area figure of metal-oxide-semiconductor unit cell array；
Dry etching is not photo-etched the exposure mask oxide layer of glue protection, exposes outside the corresponding N- of trench area figure
Prolong layer, after removing photoresist, the exposure mask oxide layer of reservation is as hard exposure mask；
Using the hard exposure mask as barrier layer, the surface in the N- epitaxial layer forms groove, in the groove and institute
The surface for stating N- epitaxial layer grows one layer of gate oxide；
The depositing polysilicon layer on the gate oxide, the area of grid of VDMOS structure is defined by photolithographicallpatterned, is done
Method etching removes the polysilicon layer and the gate oxide, is formed simultaneously VDMOS gate structure and groove MOSFET grid
Structure；
P type trap zone layer and N+ source electrode region layer are successively formed in the N- epitaxial layer；
Insulating medium layer is formed on the surface of the N+ source electrode region layer, and etches the insulating medium layer and forms contact hole,
Metal layer is filled in the contact hole；
In the metal that the upper surface of the insulating medium layer deposits, source metal region layer is formed, the contact hole is by connecing
Touching metal layer is connect with the source metal region layer, forms source metal electrode；
In the bottom surface deposition metal layer of the N+ monocrystalline substrate, drain electrode region layer is formed, which forms drain metal
Electrode.
It preferably, is the first gate oxide positioned at the gate oxide of the trench interiors, with first gate oxide
The polysilicon layer laterally contacted is the second polysilicon layer, the groove and first gate oxide and first polycrystalline
Silicon layer forms the groove MOSFET gate structure；
Gate oxide above the N- epitaxial layer and the P type trap zone layer is the second gate oxide, and described
The polysilicon layer that second gate oxide longitudinally contacts is the second polysilicon layer, second gate oxide and second polysilicon
Layer forms the VDMOS gate structure.
Preferably, the groove is located at the middle position of two VDMOS gate structures, and the contact hole is located at institute
It states among VDMOS gate structure and the groove.
Preferably, P type trap zone layer successively is formed in the N- epitaxial layer and N+ source electrode region layer specifically includes following step
It is rapid:
By being automatically aligned to mode, by p type impurity ion implanting to the N- epitaxial layer, then pass through at short annealing
Reason forms P type trap zone layer in the N- epitaxial layer；
N+ source electrode region layer is defined above the P type trap zone layer, and activation injection member is then handled by short annealing
Element.
Preferably, insulating medium layer is formed on the surface of the N+ source electrode region layer, and etches the insulating medium layer shape
At contact hole, filling metal layer in the contact hole specifically includes the following steps:
In one layer of insulating medium layer of surface deposition of the N+ source electrode region layer, which is silicon dioxide layer and silicon nitride
Layer one of or two kinds；
Dry etching is implemented to the insulating medium layer, penetrates the insulating medium layer and the P type trap zone layer, extends to
The N- epitaxial layer forms contact hole；
Metal filling is carried out to contact hole, first deposited metal titanium adhesive layer deposits titanium nitride resistance on Titanium adhesive layer
Barrier, redeposited tungsten metal layer are equipped with the contact zone P+ at the P type trap zone layer of the contact hole lateral ends, are located at institute
The Titanium adhesive layer and titanium nitride barrier layer and N+ source electrode region layer for stating contact hole lateral ends form N+ source electrode Ohmic contact, are located at
The Titanium adhesive layer and titanium nitride barrier layer and the contact zone P+ of the side wall of the contact hole form the ohmic contact layer of p-type trap,
Contact metal layer is formed in the ohmic contact layer and tungsten metal.
Beneficial effects of the present invention
1, VDMOS structure and groove are formed unit cell device, structure by new power MOSFET element provided by the invention
Novelty, properties of product are high；
2, new power MOSFET element provided by the invention, the existing lower conduction loss of power MOS (Metal Oxide Semiconductor) device with groove
Advantage, while having the advantages that VDMOS compared with low switching losses；
3, new power MOSFET element provided by the invention, while making device possess lower Qgd, also possess compared with
Low conducting resistance；
4, new power MOSFET element provided by the invention, the VDMOS gate structure and the groove structure are total
With the source metal region layer and drain metal region layer；
5, the preparation method of new power MOSFET element provided by the invention, increased VDMOS structure, without increasing
Additional preparation cost also optimizes the performance of device；
6, the preparation method of new power MOSFET element provided by the invention, preparation method being capable of complete and existing function
Rate MOSFET process compatible, at low cost, structure novel have lower power loss, good electrical characteristics and reliability, have
The market competitiveness and promotional value.
Detailed description of the invention
Fig. 1 is the schematic diagram of the section structure of new power MOSFET element of the present invention；
Fig. 2 is the structural schematic diagram that N+ monocrystalline substrate and N- epitaxial layer are formed in preparation method of the present invention；
Fig. 3 is the structural schematic diagram that groove is formed in preparation method of the present invention；
Fig. 4 is the structural schematic diagram that the gate oxide in preparation method of the present invention is formed；
Fig. 5 is the structural schematic diagram of polysilicon layer deposit in preparation method of the present invention；
Fig. 6 is the structural representation of VDSOS gate structure and groove MOSFET gate structure in preparation method of the present invention
Figure；
Fig. 7 is the structural schematic diagram of the P type trap zone layer and the formation of N+ source area in preparation method of the present invention；
Fig. 8 is the structural schematic diagram of the insulating medium layer in preparation method of the present invention；
Fig. 9 is the structural schematic diagram that the contact hole in preparation method of the present invention is formed；
Figure 10 is the structural schematic diagram of the metal layer filling in preparation method of the present invention；
Figure 11 is the structural representation of the source level metal region layer and the formation of drain metal region layer in preparation method of the present invention
Figure；
Figure 12 is the flow chart of preparation method of the present invention.
Wherein, 1-N+ monocrystalline substrate, 2-N- epitaxial layer, 3- groove, the first gate oxide of 4-, the second gate oxide of 5-,
The first polysilicon layer of 6-, the second polysilicon layer of 7-, 8- contact hole, 9- metal layer, 10-P type well region layer, 11-N+ source area, 12-
Insulating medium layer, 13- source level metal region layer, 14- drain metal region layer, 15- exposure mask oxide layer.
Specific embodiment
Present invention will be described in further detail below with reference to the accompanying drawings, to enable those skilled in the art referring to specification text
Word can be implemented accordingly.
It should be appreciated that in the present specification, when an element be mentioned as " be connected to or be coupled to " another element or
When " be arranged in another element ", can " direct " be connected to or be coupled to another element or " direct " setting in another member
In part.Or another element is connected to or be coupled in such a way that other elements are intervenient or is arranged in another element, unless
It is " be coupled directly to or be connected to " another element or " directly setting " in another element by volume.Furthermore, it is to be understood that working as
One element is mentioned as " on another element ", " above another element ", " under another element " or " under another element
When side ", it can contact with another element " direct " or be contacted in a manner of having intervened other elements therebetween with another element, unless
It is mentioned as directly contacting with another element.When the direction of reference element is inverted or changes, may be used as comprising root
According to the meaning of the concept in the direction of corresponding relativeness term.
As shown in Figure 1, the present invention provides a kind of new power MOSFET element, including drain metal region layer 14, it is located at
It is the N+ monocrystalline substrate 1 of high-dopant concentration above the drain metal region layer, low above the N+ monocrystalline substrate 1
The N- epitaxial layer 2 of doping concentration, is located on the P type trap zone layer 10 the P type trap zone layer 10 above the N- epitaxial layer 2
The N+ source area 11 of side, the insulating medium layer 12 positioned at the N+ source area 11 above and on the insulating medium layer 12
The source level metal region layer 13 of side, which is characterized in that further include:
Groove 3 passes through the P type trap zone layer 10 and the N+ source area 11, extends to the interior of the N- epitaxial layer 2
Portion；
Gate oxide comprising the first gate oxide 4 and the second gate oxide 5, first gate oxide 4 and the ditch
The medial surface of slot 3 and bottom end contact, second gate oxide 5 are located at the upper of the N- epitaxial layer 2 and the P type trap zone layer 10
Side；
Polysilicon layer comprising the first polysilicon layer 6 and the second polysilicon layer 7, first polysilicon layer 7 are located at described
In groove 3, being contacted with first gate oxide 4, second polysilicon layer 8 is located at the top of second gate oxide 5,
It is contacted with second gate oxide 5；
Wherein, second gate oxide 5 and second polysilicon layer 7 form VDMOS gate structure, the groove 3
Positioned at the middle position of two VDMOS gate structures.
Contact hole 8 passes through the insulating medium layer 12 and N+ source area 11, extends to the P type trap zone layer 10, described
Contact hole 8 is located among the VDMOS gate structure and the groove 3, and the inside of the contact hole 8 is filled with metal, tool
The metal of body be metal layer 9, the metal layer 9 sequentially consist of Titanium adhesive layer, titanium nitride barrier layer and
Tungsten metal layer；Wherein, the metal layer 9 is contacted with the P type trap zone layer 10 and the N+ source area 11, forms Ohmic contact
Layer, the metal layer 9 are contacted with the source metal region layer 13.
Wherein, the source metal region layer 13 is MOSFET element source metal electrode, and the drain metal region layer 14 is
MOSFET element drain metal electrode.
The insulating medium layer 12 is one of silicon dioxide layer and silicon nitride layer or two kinds.
The unit cell of each MOSFET element in the present invention is by a VDSOS structure and a trench MOSFET structure group
At, and the VDMOS structure and the trench MOSFET structure share the source metal region layer and drain metal region layer.
In top plan view, the center of the device is unit cell array region in parallel, the top surface deposition in unit cell array region
There is upper metal, forms source metal region layer, the bottom in unit cell array region is followed successively by from bottom to top positioned at the heavily doped of silicon chip back side
Miscellaneous drain metal region layer, the N+ monocrystalline substrate above the drain region, above the N+ monocrystalline substrate
N- epitaxial layer is lightly doped, in one layer of exposure mask oxide layer of N-type lightly doped epitaxial layer surface deposition, forms ditch eventually by photolithographicallpatterned
Slot is located at the N- epitaxial layer and is deep into the groove of the epitaxial layer, the trench interiors are equipped with the first gate oxide
With the first polysilicon layer, wherein meanwhile, there is the second gate oxide on the surface of the N- epitaxial layer, in second gate oxidation
The second polysilicon layer is deposited on layer, second gate oxide and second polysilicon layer define VDSOS gate structure, institute
The gate structure for stating VDSOS gate structure and the groove is formed simultaneously, and forms p-type by ion implanting in N- epi-layer surface
Well region layer, then activates doped chemical by annealing process；N+ source area is formed by ion implanting, then passes through annealing process
Doped chemical is activated, is insulating medium layer above N+ source electrode region layer, is performed etching on insulating medium layer, penetrate the insulation
Dielectric layer and the P type trap zone layer extend to the N- epitaxial layer, form contact hole, carry out metal filling to contact hole, first sink
Product Titanium adhesive layer, deposits titanium nitride barrier layer on Titanium adhesive layer, followed by depositing tungsten metal layer, connects close to described
At the P type trap zone layer of contact hole lateral ends be equipped with the contact zone P+, positioned at the contact hole lateral ends Titanium adhesive layer and
Titanium nitride barrier layer and N+ source electrode region layer form N+ source electrode Ohmic contact, positioned at the Titanium adhesive layer of the side wall of the contact hole
The ohmic contact layer that p-type trap is formed with titanium nitride barrier layer and the contact zone P+ connects in the ohmic contact layer and the formation of tungsten metal
Touch metal layer；The insulating medium layer upper surface formed source metal region layer, the contact hole by metal layer with it is described
The connection of source metal region layer, forms source metal electrode；
In the bottom surface deposition metal layer of N+ monocrystalline substrate, drain region is formed, which forms metal-oxide-semiconductor back side drain region gold
Belong to electrode layer, i.e. metal-oxide-semiconductor drain metal electrode.
Each MOSFET unit cell of the invention is made of a VDMOS structure and a trench MOSFET structure, is had
The MOSFET structure of this structure is novel, and properties of product are high, so that also possessing lower conducting while device possesses lower Qgd
Resistance.The switching loss and conduction loss of device can be effectively reduced in power application.Simultaneously because the VDMOS structure and
The area of grid of the trench MOSFET structure is formed simultaneously, thus its process can completely with existing power MOSFET work
Skill is compatible, without increasing additional preparation cost, can in high volume put into production, and reduces cost, increases the market competitiveness, so that this
Invention has substantive distinguishing features outstanding and significant progress.
On the basis of new power MOSFET element of the present invention, the present invention also provides the new power MOSFET devices
The preparation method of part, as shown in figure 12, comprising the following steps:
Step 101, it is covered as shown in Fig. 2, growing one layer on the surface for the N- epitaxial layer being located above N+ monocrystalline substrate
Film oxide layer, and photoetching is carried out to the exposure mask oxide layer, define the trench area figure of metal-oxide-semiconductor unit cell array；
Step 102, dry etching is not photo-etched the exposure mask oxide layer of glue protection, and it is corresponding to expose trench area figure
The N- epitaxial layer, after removing photoresist, the exposure mask oxide layer of reservation is as hard exposure mask；
Step 103, as shown in Figure 3 and Figure 4, the surface using the hard exposure mask as barrier layer, in the N- epitaxial layer
Groove is formed, grows one layer of gate oxide on the surface of the groove and the N- epitaxial layer；
Step 104, it as shown in figure 5, depositing conductive polycrystalline silicon floor on the gate oxide, is defined by photolithographicallpatterned
The area of grid of VDMOS structure, dry etching remove the polysilicon layer and the gate oxide, are formed simultaneously VDMOS grid
Pole structure and groove MOSFET gate structure；Specifically, as shown in fig. 6, the gate oxide for being located at the trench interiors is first
Gate oxide is the second polysilicon layer, the groove and institute with the polysilicon layer that first gate oxide laterally contacts
It states the first gate oxide and first polysilicon layer forms the groove MOSFET gate structure；Specifically, being located at the N-
Gate oxide above epitaxial layer and the P type trap zone layer is the second gate oxide, is longitudinally connect with second gate oxide
The polysilicon layer of touching is the second polysilicon layer, and second gate oxide and second polysilicon layer form the VDMOS grid
Pole structure；
Wherein, the groove is located at the middle position of two VDMOS gate structures, and the contact hole is located at described
Among VDMOS gate structure and the groove；
Step 105, as shown in fig. 7, successively forming P type trap zone layer and N+ source electrode region layer in the N- epitaxial layer；
Step 106, as shown in figure 8, forming insulating medium layer on the surface of the N+ source electrode region layer, and the insulation is etched
Dielectric layer forms contact hole, as shown in figure 9, filling metal layer in the contact hole, as shown in Figure 10；
Step 107, as shown in figure 11, the metal deposited in the upper surface of the insulating medium layer forms source metal area
Layer, the contact hole are connect by contact metal layer with the source metal region layer, and source metal electrode is formed；To metal region layer
Implement photoetching, with photoresist protect metal-oxide-semiconductor unit cell array area source metal electrode region and metal-oxide-semiconductor unit cell array area periphery
Gate metal electrode region defines source metal electrode region and gate metal electrode regional graphics；
Using dry etching method, selective removal is not photo-etched the metal region layer of glue protection, exposes and is situated between as insulation
The third dielectric layer of matter layer, after removing photoresist, the metal region layer positioned at unit cell array region left forms metal-oxide-semiconductor source electrode gold
Belong to electrode, while being also the anode metal electrodes of Schottky diode, the metal area positioned at unit cell array region periphery left
Layer forms metal-oxide-semiconductor gate metal electrode；
Step 108, drain electrode region layer is formed in the bottom surface deposition metal layer of the N+ monocrystalline substrate as shown in figure 11, it should
Metal layer forms drain metal electrode；
Wherein, in the step 101, the N+ monocrystalline substrate is the N+ monocrystalline substrate of high-dopant concentration, the N-
Epitaxial layer is the N- epitaxial layer of low doping concentration；
Wherein, in the step 103, the gate oxide is silicon dioxide layer；
In the present invention, the VDMOS gate structure is formed simultaneously with the groove MOSFET gate structure, is collectively constituted
Unit cell device, the class VDSOS structure that the VDMOS gate structure is constituted, and constituted with the groove MOSFET gate structure
Class MOSFET structure shares the source metal region layer and drain metal region layer, thus process of the invention can completely with
Existing power MOSFET processes are compatible, on the basis of being not necessarily to increase additional manufacturing cost, so that product structure is novel, and
While so that device possesses lower Qgd, also possess lower conducting resistance.
In addition, the groove is located at the middle position of two VDMOS gate structures, the contact hole is located at described
Among VDMOS gate structure and the groove, guarantee that VDMOS structure and trench MOS structure are alternately present, so that device possesses more
Low conduction loss and switching loss, while the Cell density of unit area and the switching frequency of device are promoted, it more adapts to present
It is thin, gently, small, the application demand of high frequency.
Specifically, successively form P type trap zone layer and N+ source electrode region layer in the N- epitaxial layer the following steps are included:
Step 201, by being automatically aligned to mode, by p type impurity ion implanting to the N- epitaxial layer, then pass through fast
Fast annealing activates doped chemical, and P type trap zone layer is formed in the N- epitaxial layer；
Step 202, N+ source electrode region layer is defined above the P type trap zone layer, is then handled and is swashed by short annealing
Injection element living.
Specifically, forming insulating medium layer on the surface of the N+ source electrode region layer, and etches the insulating medium layer and formed
Contact hole, filling metal layer in the contact hole specifically includes the following steps:
Step 301, in one layer of insulating medium layer of surface deposition of the N+ source electrode region layer, which is silica
The composite layer of layer perhaps silicon nitride layer or silicon dioxide layer and silicon nitride layer；
Step 302, dry etching is implemented to the insulating medium layer, penetrates the insulating medium layer and the P type trap zone
Layer extends to the N- epitaxial layer, forms contact hole；
Step 303, metal filling is carried out to contact hole, first deposited metal titanium adhesive layer deposits on Titanium adhesive layer
Titanium nitride barrier layer, redeposited tungsten metal layer are equipped with P+ at the P type trap zone layer of the contact hole lateral ends and contact
Area, Titanium adhesive layer and titanium nitride barrier layer and N+ source electrode region layer positioned at the contact hole lateral ends form N+ source electrode ohm
Contact forms the Europe of p-type trap positioned at the Titanium adhesive layer and titanium nitride barrier layer and the contact zone P+ of the side wall of the contact hole
Nurse contact layer forms contact metal layer in the ohmic contact layer and tungsten metal.
Each MOSFET unit cell of this method is made of a VDMOS structure and a trench MOSFET structure, is had
The MOSFET structure of this structure is novel, and properties of product are high, so that also possessing lower lead while device possesses lower Q gd
Be powered resistance.The switching loss and conduction loss of device can be effectively reduced in power application.Simultaneously because the VDMOS structure
Be formed simultaneously with the area of grid of the trench MOSFET structure, thus its process can completely with existing power MOSFET
Process compatible can in high volume put into production without increasing additional manufacturing cost, reduce cost, increase the market competitiveness, so that
The present invention has substantive distinguishing features outstanding and significant progress.
The present invention just no longer elaborates here there are also other selective embodiments.
Although the embodiments of the present invention have been disclosed as above, but its is not only in the description and the implementation listed
With it can be fully applied to various fields suitable for the present invention, for those skilled in the art, can be easily
Realize other modification, therefore without departing from the general concept defined in the claims and the equivalent scope, the present invention is simultaneously unlimited
In specific details and legend shown and described herein.
Claims (10)
1. a kind of new power MOSFET element, mono- including drain metal region layer, the N+ above the drain metal region layer
Crystalline silicon substrate, the N- epitaxial layer above the N+ monocrystalline substrate, the P type trap zone layer above the N- epitaxial layer,
N+ source area above the P type trap zone layer, the insulating medium layer above the N+ source area and be located at it is described absolutely
Source level metal region layer above edge dielectric layer, which is characterized in that further include:
Groove passes through the P type trap zone layer and the N+ source area, extends to the inside of the N- epitaxial layer；
Gate oxide comprising the first gate oxide and the second gate oxide, first gate oxide are interior with the groove
Side and bottom end contact, second gate oxide are located at the top of the N- epitaxial layer and the P type trap zone layer；
Polysilicon layer comprising the first polysilicon layer and the second polysilicon layer, first polysilicon layer are located in the groove,
It is contacted with first gate oxide, second polysilicon layer is located at the top of second gate oxide, with described second
Gate oxide contact；
Contact hole passes through the insulating medium layer and N+ source area, extends to the P type trap zone layer, the contact hole it is interior
Portion is filled with metal.
2. new power MOSFET element as described in claim 1, which is characterized in that the metal is metal layer, the gold
Belong to layer and sequentially consists of Titanium adhesive layer, titanium nitride barrier layer and tungsten metal layer；
Wherein, the metal layer and the P type trap zone layer and the N+ source region contact form ohmic contact layer, the metal
Layer is contacted with the source metal region layer.
3. new power MOSFET element as described in claim 1, which is characterized in that second gate oxide and described
Two polysilicon layers form VDMOS gate structure, and the groove is located at the middle position of two VDMOS gate structures, described
Contact hole is located among the VDMOS gate structure and the groove.
4. new power MOSFET element as described in claim 1, which is characterized in that the insulating medium layer is silica
Layer and one of silicon nitride layer or two kinds.
5. new power MOSFET element as described in claim 1, which is characterized in that the N+ monocrystalline substrate is highly doped
The N+ monocrystalline substrate of concentration, the N- epitaxial layer are the N- epitaxial layer of low doping concentration.
6. a kind of preparation method of new power MOSFET element, which comprises the following steps:
One layer of exposure mask oxide layer is grown on the surface for the N- epitaxial layer being located above N+ monocrystalline substrate, and to the exposure mask oxygen
Change layer and carry out photoetching, defines the trench area figure of metal-oxide-semiconductor unit cell array；
Dry etching is not photo-etched the exposure mask oxide layer of glue protection, exposes the corresponding N- extension of trench area figure
Layer, after removing photoresist, the exposure mask oxide layer of reservation is as hard exposure mask；
Using the hard exposure mask as barrier layer, the surface in the N- epitaxial layer forms groove, in the groove and the N-
The surface of epitaxial layer grows one layer of gate oxide；
The depositing polysilicon layer on the gate oxide, the area of grid of VDMOS structure is defined by photolithographicallpatterned, and dry method is carved
Etching off removes the polysilicon layer and the gate oxide, is formed simultaneously VDMOS gate structure and groove MOSFET gate structure；
P type trap zone layer and N+ source electrode region layer are successively formed in the N- epitaxial layer；
Insulating medium layer is formed on the surface of the N+ source electrode region layer, and etches the insulating medium layer and forms contact hole, it is described
Metal layer is filled in contact hole；
In the metal that the upper surface of the insulating medium layer deposits, source metal region layer is formed, the contact hole passes through contact gold
Belong to layer to connect with the source metal region layer, forms source metal electrode；
In the bottom surface deposition metal layer of the N+ monocrystalline substrate, drain electrode region layer is formed, which forms drain metal electrode.
7. the preparation method of new power MOSFET element as claimed in claim 6, which is characterized in that
Positioned at the trench interiors gate oxide be the first gate oxide, laterally contacted with first gate oxide described in
Polysilicon layer is that the second polysilicon layer, the groove and first gate oxide and first polysilicon layer form the ditch
Groove MOSFET gate structure；
Gate oxide above the N- epitaxial layer and the P type trap zone layer is the second gate oxide, with described second
The polysilicon layer that gate oxide longitudinally contacts is the second polysilicon layer, second gate oxide and the second polysilicon layer shape
At the VDMOS gate structure.
8. the preparation method of new power MOSFET element as claimed in claim 6, which is characterized in that the groove is located at two
The middle position of a VDMOS gate structure, the contact hole are located among the VDMOS gate structure and the groove.
9. the preparation method of new power MOSFET element as claimed in claim 6, which is characterized in that successively outside the N-
Prolong form P type trap zone layer and N+ source electrode region layer in layer specifically includes the following steps:
By being automatically aligned to mode, by p type impurity ion implanting to the N- epitaxial layer, then handled by short annealing,
P type trap zone layer is formed in the N- epitaxial layer；
N+ source electrode region layer is defined above the P type trap zone layer, and activation injection element is then handled by short annealing.
10. the preparation method of new power MOSFET element as claimed in claim 6, which is characterized in that in the N+ source electrode
The surface of region layer forms insulating medium layer, and etches the insulating medium layer and form contact hole, fills metal in the contact hole
Layer specifically includes the following steps:
In one layer of insulating medium layer of surface deposition of the N+ source electrode region layer, which is in silicon dioxide layer and silicon nitride layer
It is one or two kinds of；
Dry etching is implemented to the insulating medium layer, penetrates the insulating medium layer and the P type trap zone layer, is extended to described
N- epitaxial layer forms contact hole；
Metal filling is carried out to contact hole, first deposited metal titanium adhesive layer deposits titanium nitride barrier layer on Titanium adhesive layer,
Redeposited tungsten metal layer is equipped with the contact zone P+ at the P type trap zone layer of the contact hole lateral ends, is located at the contact
The Titanium adhesive layer and titanium nitride barrier layer and N+ source electrode region layer of hole lateral ends form N+ source electrode Ohmic contact, connect positioned at described
The Titanium adhesive layer and titanium nitride barrier layer and the contact zone P+ of the side wall of contact hole form the ohmic contact layer of p-type trap, described
Ohmic contact layer and tungsten metal form contact metal layer.
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| CN110400802A (en) * | 2019-08-22 | 2019-11-01 | 无锡沃达科半导体技术有限公司 | Novel common drain dual MOSFET structure and forming method thereof |
| CN112614891A (en) * | 2020-03-04 | 2021-04-06 | 许曙明 | Mosfet with enhanced high frequency performance |
| CN113363315A (en) * | 2021-04-25 | 2021-09-07 | 深圳深爱半导体股份有限公司 | Planar T-shaped gate transistor cell structure and manufacturing method |
| CN117038738A (en) * | 2023-10-10 | 2023-11-10 | 艾科微电子(深圳)有限公司 | Semiconductor device and method for manufacturing the same |
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| CN107863378A (en) * | 2017-09-14 | 2018-03-30 | 西安华羿微电子股份有限公司 | Superjunction MOS device and its manufacture method |
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| US20040026753A1 (en) * | 2002-05-16 | 2004-02-12 | Hirobumi Matsuki | Semiconductor device |
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| CN110400802A (en) * | 2019-08-22 | 2019-11-01 | 无锡沃达科半导体技术有限公司 | Novel common drain dual MOSFET structure and forming method thereof |
| CN112614891A (en) * | 2020-03-04 | 2021-04-06 | 许曙明 | Mosfet with enhanced high frequency performance |
| CN113363315A (en) * | 2021-04-25 | 2021-09-07 | 深圳深爱半导体股份有限公司 | Planar T-shaped gate transistor cell structure and manufacturing method |
| CN117038738A (en) * | 2023-10-10 | 2023-11-10 | 艾科微电子(深圳)有限公司 | Semiconductor device and method for manufacturing the same |
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