CN109524472B - Novel power MOSFET device and preparation method thereof - Google Patents
Novel power MOSFET device and preparation method thereof Download PDFInfo
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- CN109524472B CN109524472B CN201811629070.8A CN201811629070A CN109524472B CN 109524472 B CN109524472 B CN 109524472B CN 201811629070 A CN201811629070 A CN 201811629070A CN 109524472 B CN109524472 B CN 109524472B
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- 238000002360 preparation method Methods 0.000 title abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 151
- 239000002184 metal Substances 0.000 claims abstract description 151
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 47
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 21
- 239000010936 titanium Substances 0.000 claims description 19
- 229910052719 titanium Inorganic materials 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 9
- 230000000903 blocking effect Effects 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000003213 activating effect Effects 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 230000008901 benefit Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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Abstract
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a novel power MOSFET device and a preparation method thereof, wherein the device comprises a drain electrode metal region layer, an N+ monocrystalline silicon substrate, an N-epitaxial layer, a P-type well region layer, an N+ source region, an insulating medium layer, a source metal region layer and a groove; a first gate oxide layer and a second gate oxide layer; the first polysilicon layer and the second polysilicon layer and the contact hole. The invention also provides a preparation method of the device, which ensures that the device has lower Qgd and lower on-resistance at the same time, and the preparation method does not need to increase new cost, thereby improving market competitiveness and having popularization value.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a novel power MOSFET device and a preparation method thereof.
Background
Among power devices, power MOSFETs have found very wide application due to their superior performance. Power MOSFET energy losses include mainly switching losses and on-state losses, and therefore many different device structures and solutions are created for how to reduce switching losses and on-state losses of power MOSFET devices. To date, the development of power MOSFETs has mainly used trench MOSFET device structures (including split-gate, etc. novel structures are variations of trench structures) for low voltage applications, and VDMOS for medium voltage applications, but both of these device structures have inherent drawbacks.
Although the on-state resistance of the trench MOSFET device structure is lower than that of the VDMOS, the trench power MOS device has larger parasitic capacitance between the gate and the source and between the gate and the drain, namely the gate-source capacitance Cgs and the gate-drain capacitance Cgd. When the power MOS tube is switched between an on state and an off state, the voltage change of Cgd is far greater than the voltage change on Cgs, and the corresponding charge and discharge quantity Qgd is larger, so that the Qgd has larger influence on the switching speed, which means higher switching loss, and the breakdown voltage cannot meet higher requirements due to the influence of the electric field distribution of an active region; while VDMOS has higher breakdown voltage and lower Qgd, JEFET region resistance affects higher on-loss than trench power MOS devices, and therefore a larger device area is required to meet smaller on-loss.
At present, energy conservation and emission reduction and low carbon are advocated, and how to simultaneously reduce the switching loss and the conduction loss of a power MOSFET device, so that the device has good high-frequency characteristics and lower power loss is an effort direction of a person in the technical field.
In order to solve the problems, the invention provides a novel power MOSFET device and a preparation method thereof.
Disclosure of Invention
It is an object of the present invention to address at least one of the above problems or disadvantages and to provide at least one advantage as will be described below.
It is a further object of the present invention to provide a novel power MOSFET device that allows for a device having a lower Qgd while also having a lower on-resistance.
It is a further object of the present invention to provide a novel power MOSFET device that reduces the switching losses of the MOSFET device.
The invention also aims to provide a preparation method of the novel power MOSFET device, the preparation process of the novel power MOSFET device can be completely compatible with the existing MOSFET process, the cost is not increased, and the novel power MOSFET device has low power loss and good electrical characteristics and reliability on the basis of novel structure.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a novel power MOSFET device is provided, comprising a drain metal region layer, an n+ monocrystalline silicon substrate over the drain metal region layer, an N-epitaxial layer over the n+ monocrystalline silicon substrate, a P-type well region layer over the N-epitaxial layer, an n+ source region over the P-type well region layer, an insulating dielectric layer over the n+ source region, and a source metal region layer over the insulating dielectric layer, further comprising:
a trench extending through the P-type well region layer and the n+ source region to an inside of the N-epitaxial layer;
The gate oxide layer comprises a first gate oxide layer and a second gate oxide layer, the first gate oxide layer is in contact with the inner side surface and the bottom end of the groove, and the second gate oxide layer is positioned above the N-epitaxial layer and the P-type well region layer;
The polysilicon layer comprises a first polysilicon layer and a second polysilicon layer, the first polysilicon layer is positioned in the groove and is contacted with the first gate oxide layer, and the second polysilicon layer is positioned above the second gate oxide layer and is contacted with the second gate oxide layer;
and the contact hole penetrates through the insulating dielectric layer and the N+ source region and extends to the P-type well region layer, and the metal is filled in the contact hole.
The source metal region layer is a source metal electrode of the MOSFET device, and the drain metal region layer is a drain metal electrode of the MOSFET device.
Preferably, the metal is a metal layer, and the metal layer is a metal titanium bonding layer, a titanium nitride barrier layer and a tungsten metal layer in sequence from bottom to top;
The metal layer is in contact with the P-type well region layer and the N+ source region to form an ohmic contact layer, and the metal layer is in contact with the source metal region layer.
Preferably, the second gate oxide layer and the second polysilicon layer form a VDMOS gate structure, the trench is located in a middle position of the two VDMOS gate structures, and the contact hole is located in a middle position of the VDMOS gate structure and the trench.
Preferably, the insulating dielectric layer is one or two of a silicon dioxide layer and a silicon nitride layer.
Preferably, the n+ monocrystalline silicon substrate is an n+ monocrystalline silicon substrate with high doping concentration, and the N-epitaxial layer is an N-epitaxial layer with low doping concentration.
The invention also provides a preparation method of the novel power MOSFET device, which comprises the following steps:
growing a mask oxide layer on the surface of the N-epitaxial layer above the N+ monocrystalline silicon substrate, and photoetching the mask oxide layer to define a groove region pattern of the MOS transistor unit cell array;
the mask oxide layer which is not protected by the photoresist is etched by a dry method, the N-epitaxial layer corresponding to the pattern of the groove area is exposed, and after the photoresist is removed, the remained mask oxide layer is used as a hard mask;
Forming a groove on the surface of the N-epitaxial layer by taking the hard mask as a blocking layer, and growing a gate oxide layer on the surfaces of the groove and the N-epitaxial layer;
Depositing a polysilicon layer on the gate oxide layer, defining a gate region of a VDMOS structure in a photoetching mode, removing the polysilicon layer and the gate oxide layer by dry etching, and simultaneously forming a VDMOS gate structure and a trench MOSFET gate structure;
Forming a P-type well region layer and an N+ source region layer in the N-epitaxial layer in sequence;
Forming an insulating medium layer on the surface of the N+ source electrode region layer, etching the insulating medium layer to form a contact hole, and filling a metal layer in the contact hole;
Forming a source metal region layer by depositing metal on the upper surface of the insulating medium layer, wherein the contact hole is connected with the source metal region layer through the contact metal layer to form a source metal electrode;
And depositing a metal layer on the bottom surface of the N+ monocrystalline silicon substrate to form a drain electrode region layer, wherein the metal layer forms a drain electrode metal electrode.
Preferably, the gate oxide layer inside the trench is a first gate oxide layer, the polysilicon layer laterally contacting the first gate oxide layer is a second polysilicon layer, and the trench, the first gate oxide layer and the first polysilicon layer form the trench MOSFET gate structure;
The gate oxide layer positioned above the N-epitaxial layer and the P-type well region layer is a second gate oxide layer, the polysilicon layer longitudinally contacted with the second gate oxide layer is a second polysilicon layer, and the second gate oxide layer and the second polysilicon layer form the VDMOS gate structure.
Preferably, the trench is located in the middle of two of the VDMOS gate structures, and the contact hole is located in the middle of the VDMOS gate structures and the trench.
Preferably, forming the P-type well region layer and the n+ source region layer in the N-epitaxial layer in sequence specifically includes the following steps:
Implanting P-type impurity ions into the N-epitaxial layer in an automatic alignment mode, and forming a P-type well region layer in the N-epitaxial layer through rapid annealing treatment;
and defining an N+ source region layer above the P-type well region layer, and activating an implanted element through rapid annealing treatment.
Preferably, an insulating dielectric layer is formed on the surface of the n+ source region layer, and a contact hole is formed by etching the insulating dielectric layer, wherein a metal layer is filled in the contact hole, and the method specifically comprises the following steps:
Depositing an insulating dielectric layer on the surface of the N+ source electrode region layer, wherein the dielectric layer is one or two of a silicon dioxide layer and a silicon nitride layer;
Dry etching is carried out on the insulating dielectric layer, the insulating dielectric layer and the P-type well region layer are penetrated, and the insulating dielectric layer and the P-type well region layer extend to the N-epitaxial layer to form a contact hole;
And filling metal into the contact hole, depositing a metal titanium bonding layer, depositing a titanium nitride blocking layer on the metal titanium bonding layer, depositing a tungsten metal layer, arranging a P+ contact region at the P-type well region layer close to the side face end of the contact hole, forming N+ source ohmic contact with the N+ source region layer by the metal titanium bonding layer and the titanium nitride blocking layer which are positioned at the side face end of the contact hole, forming an ohmic contact layer of a P-type well by the metal titanium bonding layer and the titanium nitride blocking layer which are positioned on the side wall of the contact hole and the P+ contact region, and forming a contact metal layer between the ohmic contact layer and tungsten metal.
The beneficial effects of the invention are that
1. The novel power MOSFET device provided by the invention has the advantages that the VDMOS structure and the groove form a single-cell device, the structure is novel, and the product performance is high;
2. The novel power MOSFET device provided by the invention has the advantages of lower conduction loss of the trench power MOS device and also has the advantage of lower switching loss of the VDMOS;
3. The novel power MOSFET device provided by the invention has lower Qgd and lower on-resistance at the same time;
4. the VDMOS gate structure and the trench structure of the novel power MOSFET device share the source metal region layer and the drain metal region layer;
5. The preparation method of the novel power MOSFET device provided by the invention has the advantages that the added VDMOS structure is unnecessary to increase extra preparation cost, and the performance of the device is optimized;
6. the preparation method of the novel power MOSFET device provided by the invention can be completely compatible with the existing power MOSFET technology, is low in cost and novel in structure, has lower power loss, good electrical characteristics and reliability, and has market competitiveness and popularization value.
Drawings
Fig. 1 is a schematic cross-sectional structure of a novel power MOSFET device according to the present invention;
FIG. 2 is a schematic diagram of the structure of an N+ monocrystalline silicon substrate and an N-epitaxial layer in the preparation method of the present invention;
FIG. 3 is a schematic diagram of a trench formed in a method of making the present invention;
FIG. 4 is a schematic diagram of the structure of the gate oxide layer formed in the preparation method according to the present invention;
FIG. 5 is a schematic diagram of a polysilicon layer deposition structure in the fabrication method of the present invention;
FIG. 6 is a schematic diagram of a VDSOS gate structure and a trench MOSFET gate structure in a method of making the present invention;
FIG. 7 is a schematic diagram of a structure of a P-type well region layer and an N+ source region in the fabrication method of the present invention;
FIG. 8 is a schematic diagram of an insulating dielectric layer in the preparation method of the present invention;
FIG. 9 is a schematic diagram of a contact hole formation structure in the manufacturing method according to the present invention;
FIG. 10 is a schematic diagram of a metal layer filling structure in the manufacturing method according to the present invention;
FIG. 11 is a schematic view of a structure formed by a source metal region layer and a drain metal region layer in the manufacturing method of the present invention;
FIG. 12 is a flow chart of the preparation method of the present invention.
The semiconductor device comprises a 1-N+ monocrystalline silicon substrate, a 2-N-epitaxial layer, a 3-trench, a 4-first gate oxide layer, a 5-second gate oxide layer, a 6-first polysilicon layer, a 7-second polysilicon layer, an 8-contact hole, a 9-metal layer, a 10-P type well region layer, an 11-N+ source region, a 12-insulating dielectric layer, a 13-source metal region layer, a 14-drain metal region layer and a 15-mask oxide layer.
Detailed Description
The present invention is described in further detail below with reference to the drawings to enable those skilled in the art to practice the invention by referring to the description.
It will be understood that in the present specification, when an element is referred to as being "connected to or coupled to" another element or being "disposed in" another element, it can be "directly" connected to or coupled to the other element or be "directly" disposed in the other element. Or connected or coupled to or disposed in another element with other elements interposed therebetween, unless it is physically "directly coupled or connected to" or "directly disposed in" the other element. In addition, it will be understood that when an element is referred to as being "on," "over," "under" or "under" another element, it can be "directly contacted with" the other element or intervening elements may be present therebetween, unless it is referred to as being directly contacted with the other element. When the orientation of a reference element is reversed or changed, it may be used as a meaning of a concept comprising orientation according to the corresponding relative term.
As shown in fig. 1, the present invention provides a novel power MOSFET device, which includes a drain metal region layer 14, an n+ monocrystalline silicon substrate 1 with high doping concentration located above the drain metal region layer, an N-epitaxial layer 2 with low doping concentration located above the n+ monocrystalline silicon substrate 1, a P-type well region layer 10 located above the N-epitaxial layer 2, an n+ source region 11 located above the P-type well region layer 10, an insulating dielectric layer 12 located above the n+ source region 11, and a source metal region layer 13 located above the insulating dielectric layer 12, and is characterized in that the novel power MOSFET device further includes:
A trench 3 extending through the P-type well region layer 10 and the n+ source region 11 to the inside of the N-epitaxial layer 2;
the gate oxide layer comprises a first gate oxide layer 4 and a second gate oxide layer 5, the first gate oxide layer 4 is in contact with the inner side surface and the bottom end of the groove 3, and the second gate oxide layer 5 is positioned above the N-epitaxial layer 2 and the P-type well region layer 10;
The polysilicon layer comprises a first polysilicon layer 6 and a second polysilicon layer 7, the first polysilicon layer 7 is positioned in the groove 3 and is contacted with the first gate oxide layer 4, and the second polysilicon layer 8 is positioned above the second gate oxide layer 5 and is contacted with the second gate oxide layer 5;
wherein the second gate oxide layer 5 and the second polysilicon layer 7 form a VDMOS gate structure, and the trench 3 is located in a middle position of the two VDMOS gate structures.
The contact hole 8 passes through the insulating dielectric layer 12 and the n+ source region 11 and extends to the P-type well region layer 10, the contact hole 8 is positioned between the VDMOS gate structure and the trench 3, the metal is filled in the contact hole 8, the metal is specifically a metal layer 9, and the metal layer 9 is sequentially a metal titanium bonding layer, a titanium nitride barrier layer and a tungsten metal layer from bottom to top; the metal layer 9 contacts the P-type well region layer 10 and the n+ source region 11 to form an ohmic contact layer, and the metal layer 9 contacts the source metal region layer 13.
The source metal region layer 13 is a source metal electrode of the MOSFET device, and the drain metal region layer 14 is a drain metal electrode of the MOSFET device.
The insulating dielectric layer 12 is one or both of a silicon dioxide layer and a silicon nitride layer.
The unit cell of each MOSFET device in the invention is composed of one VDSOS structure and one groove MOSFET structure, and the VDMOS structure and the groove MOSFET structure share the source metal area layer and the drain metal area layer.
On a top plane, the center of the device is a parallel unit cell array area, the top surface of the unit cell array area is deposited with upper metal to form a source metal area layer, the bottom of the unit cell array area is sequentially provided with a heavily doped drain metal area layer positioned on the back surface of a silicon wafer from bottom to top, an N+ monocrystalline silicon substrate positioned above the drain area, a lightly doped N-epitaxial layer positioned above the N+ monocrystalline silicon substrate, a mask oxide layer deposited on the surface of the N-type lightly doped epitaxial layer, a groove formed in a photoetching mode, namely a groove positioned in the N-epitaxial layer and penetrating into the epitaxial layer, a first gate oxide layer and a first polycrystalline silicon layer are arranged in the groove, meanwhile, a second gate oxide layer is arranged on the surface of the N-epitaxial layer, a second polycrystalline silicon layer is deposited on the second gate oxide layer, a VDSOS gate structure is defined by the second gate oxide layer and the second polycrystalline silicon layer, a VDSOS gate structure and a gate structure of the groove are simultaneously formed, an ion implantation is performed on the surface of the N-epitaxial layer to form a P-type doped element epitaxial layer, and then an annealing process is performed; forming an N+ source region through ion implantation, activating a doping element through an annealing process, forming an insulating medium layer above the N+ source region layer, etching on the insulating medium layer, penetrating through the insulating medium layer and the P-type well region layer, extending to the N-epitaxial layer to form a contact hole, filling metal into the contact hole, depositing a metal titanium bonding layer, depositing a titanium nitride barrier layer on the metal titanium bonding layer, then depositing a tungsten metal layer, arranging a P+ contact region at the P-type well region layer close to the side face end of the contact hole, forming N+ source ohmic contact with the N+ source region layer by the metal titanium bonding layer and the titanium nitride barrier layer positioned at the side face end of the contact hole, forming an ohmic contact layer of a P-type well by the metal titanium bonding layer and the titanium nitride barrier layer positioned on the side wall of the contact hole and the P+ contact region, and forming a contact metal layer between the ohmic contact layer and tungsten metal; forming a source metal region layer on the upper surface of the insulating medium layer, wherein the contact hole is connected with the source metal region layer through the metal layer to form a source metal electrode;
And depositing a metal layer on the bottom surface of the N+ monocrystalline silicon substrate to form a drain region, wherein the metal layer forms a metal electrode layer of a drain region on the back surface of the MOS tube, namely a metal electrode of the drain electrode of the MOS tube.
Each MOSFET unit of the invention is composed of one VDMOS structure and one trench MOSFET structure, and the MOSFET with the structure has novel structure and high product performance, so that the device has lower Qgd and lower on-resistance. Switching losses and conduction losses of the device can be effectively reduced in power applications. Meanwhile, because the VDMOS structure and the grid electrode region of the trench MOSFET structure are formed at the same time, the process method of the VDMOS structure is completely compatible with the existing power MOSFET process, does not need to increase extra preparation cost, can be put into production in batches, reduces cost and increases market competitiveness, so that the VDMOS structure has outstanding substantive characteristics and remarkable progress.
On the basis of the novel power MOSFET device, the invention also provides a preparation method of the novel power MOSFET device, as shown in fig. 12, comprising the following steps:
Step 101, as shown in fig. 2, a mask oxide layer is grown on the surface of an N-epitaxial layer above an n+ monocrystalline silicon substrate, and the mask oxide layer is subjected to photoetching to define a trench region pattern of a MOS transistor unit cell array;
Step 102, dry etching the mask oxide layer which is not protected by the photoresist to expose the N-epitaxial layer corresponding to the pattern of the trench region, and taking the remained mask oxide layer as a hard mask after the photoresist is removed;
Step 103, as shown in fig. 3 and fig. 4, using the hard mask as a blocking layer, forming a trench on the surface of the N-epitaxial layer, and growing a gate oxide layer on the surfaces of the trench and the N-epitaxial layer;
Step 104, as shown in fig. 5, a conductive polysilicon layer is deposited on the gate oxide layer, a gate region of a VDMOS structure is defined by a photoetching mode, the polysilicon layer and the gate oxide layer are removed by dry etching, and a VDMOS gate structure and a trench MOSFET gate structure are formed at the same time; specifically, as shown in fig. 6, the gate oxide layer inside the trench is a first gate oxide layer, the polysilicon layer laterally contacting the first gate oxide layer is a second polysilicon layer, and the trench, the first gate oxide layer and the first polysilicon layer form the trench MOSFET gate structure; specifically, the gate oxide layer above the N-epitaxial layer and the P-type well region layer is a second gate oxide layer, the polysilicon layer longitudinally contacted with the second gate oxide layer is a second polysilicon layer, and the second gate oxide layer and the second polysilicon layer form the VDMOS gate structure;
the groove is positioned at the middle position of the two VDMOS gate structures, and the contact hole is positioned between the VDMOS gate structures and the groove;
step 105, as shown in fig. 7, forming a P-type well region layer and an n+ source region layer in the N-epitaxial layer in sequence;
Step 106, as shown in fig. 8, an insulating dielectric layer is formed on the surface of the n+ source region layer, and the insulating dielectric layer is etched to form a contact hole, as shown in fig. 9, and a metal layer is filled in the contact hole, as shown in fig. 10;
Step 107, as shown in fig. 11, a source metal region layer is formed by depositing metal on the upper surface of the insulating dielectric layer, and the contact hole is connected with the source metal region layer through a contact metal layer to form a source metal electrode; photoetching is carried out on the metal area layer, and a source metal electrode area of the MOS tube unit cell array area and a grid metal electrode area at the periphery of the MOS tube unit cell array area are protected by photoresist, namely a source metal electrode area and a grid metal electrode area pattern are defined;
A dry etching method is adopted to selectively remove the metal area layer which is not protected by the photoresist, the third dielectric layer which is used as an insulating dielectric layer is exposed, after the photoresist is removed, the metal area layer which is left and positioned in the unit cell array area forms a metal electrode of a source electrode of the MOS tube, and meanwhile, the metal area layer which is left and positioned at the periphery of the unit cell array area forms a metal electrode of a grid electrode of the MOS tube;
Step 108, depositing a metal layer on the bottom surface of the N+ monocrystalline silicon substrate to form a drain region layer, wherein the metal layer forms a drain metal electrode as shown in fig. 11;
In the step 101, the n+ monocrystalline silicon substrate is an n+ monocrystalline silicon substrate with high doping concentration, and the N-epitaxial layer is an N-epitaxial layer with low doping concentration;
wherein, in the step 103, the gate oxide layer is a silicon dioxide layer;
In the invention, the VDMOS gate structure and the trench MOSFET gate structure are formed simultaneously to form a single cell device together, the similar VDSOS structure formed by the VDMOS gate structure and the similar MOSFET structure formed by the trench MOSFET gate structure share the source metal region layer and the drain metal region layer, so that the process method of the invention can be completely compatible with the existing power MOSFET process, and the product structure is novel without increasing additional manufacturing cost, and the device has lower Qgd and lower on-resistance.
In addition, the groove is positioned at the middle position of the two VDMOS gate structures, the contact hole is positioned between the VDMOS gate structures and the groove, and the alternate occurrence of the VDMOS structures and the groove MOS structures is ensured, so that the device has lower conduction loss and switching loss, and meanwhile, the unit cell density of unit area and the switching frequency of the device are improved, and the device is more suitable for the application requirements of thinness, lightness, smallness and high frequency at present.
Specifically, forming a P-type well region layer and an n+ source region layer in the N-epitaxial layer in sequence includes the following steps:
step 201, implanting P-type impurity ions into the N-epitaxial layer in an automatic alignment manner, and then activating doping elements through rapid annealing to form a P-type well region layer in the N-epitaxial layer;
And 202, defining an N+ source region layer above the P-type well region layer, and activating an implanted element through rapid annealing treatment.
Specifically, an insulating dielectric layer is formed on the surface of the n+ source electrode region layer, a contact hole is formed by etching the insulating dielectric layer, and a metal layer is filled in the contact hole, specifically comprising the following steps:
Step 301, depositing an insulating dielectric layer on the surface of the n+ source region layer, where the dielectric layer is a silicon dioxide layer, or a silicon nitride layer, or a composite layer of the silicon dioxide layer and the silicon nitride layer;
Step 302, dry etching is performed on the insulating dielectric layer, the insulating dielectric layer and the P-type well region layer are penetrated, and the insulating dielectric layer and the P-type well region layer extend to the N-epitaxial layer to form a contact hole;
and 303, filling metal into the contact hole, depositing a metal titanium bonding layer, depositing a titanium nitride barrier layer on the metal titanium bonding layer, depositing a tungsten metal layer, arranging a P+ contact region at the P-type well region layer close to the side surface end of the contact hole, forming N+ source ohmic contact with the N+ source region layer by the metal titanium bonding layer and the titanium nitride barrier layer positioned at the side surface end of the contact hole, forming an ohmic contact layer of a P-type well by the metal titanium bonding layer and the titanium nitride barrier layer positioned on the side wall of the contact hole and the P+ contact region, and forming a contact metal layer between the ohmic contact layer and tungsten metal.
Each MOSFET unit of the method consists of one VDMOS structure and one trench MOSFET structure, and the MOSFET with the structure has novel structure and high product performance, so that the device has lower Q gd and lower on-resistance. Switching losses and conduction losses of the device can be effectively reduced in power applications. Meanwhile, because the VDMOS structure and the grid electrode region of the trench MOSFET structure are formed at the same time, the process method of the VDMOS structure and the trench MOSFET structure can be completely compatible with the existing power MOSFET process, does not need to increase extra manufacturing cost, can be put into production in batches, reduces cost and increases market competitiveness, so that the VDMOS structure has outstanding substantive characteristics and remarkable progress.
The invention has other alternative embodiments, which will not be described in detail here.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (7)
1. A power MOSFET device comprising a drain metal region layer, an n+ monocrystalline silicon substrate over the drain metal region layer, an N-epitaxial layer over the n+ monocrystalline silicon substrate, a P-type well region layer over the N-epitaxial layer, an n+ source region over the P-type well region layer, an insulating dielectric layer over the n+ source region, and a source metal region layer over the insulating dielectric layer, further comprising:
a trench extending through the P-type well region layer and the n+ source region to an inside of the N-epitaxial layer;
The gate oxide layer comprises a first gate oxide layer and a second gate oxide layer, the first gate oxide layer is in contact with the inner side surface and the bottom end of the groove, and the second gate oxide layer is positioned above the N-epitaxial layer and the P-type well region layer;
The polysilicon layer comprises a first polysilicon layer and a second polysilicon layer, the first polysilicon layer is positioned in the groove and is contacted with the first gate oxide layer, and the second polysilicon layer is positioned above the second gate oxide layer and is contacted with the second gate oxide layer;
the contact hole penetrates through the insulating dielectric layer and the N+ source region and extends to the P-type well region layer, and metal is filled in the contact hole;
The second gate oxide layer and the second polysilicon layer form a VDMOS gate structure, the trench is positioned in the middle of the two VDMOS gate structures, and the contact hole is positioned between the VDMOS gate structure and the trench;
the metal is a metal layer, the metal layer is in contact with the P-type well region layer and the N+ source region to form an ohmic contact layer, and the metal layer is in contact with the source metal region layer;
the unit cell of the MOSFET device is composed of a VDMOS structure and a trench MOSFET structure, and the VDMOS structure and the trench MOSFET structure share the source metal region layer and the drain metal region layer.
2. The power MOSFET device of claim 1, wherein said metal layer is a metallic titanium bonding layer, a titanium nitride barrier layer, and a tungsten metal layer in that order from bottom to top.
3. The power MOSFET device of claim 1, wherein said insulating dielectric layer is one or both of a silicon dioxide layer and a silicon nitride layer.
4. The power MOSFET device of claim 1, wherein said n+ monocrystalline silicon substrate is a high dopant concentration n+ monocrystalline silicon substrate and said N-epitaxial layer is a low dopant concentration N-epitaxial layer.
5. A method of fabricating a power MOSFET device comprising the steps of:
Growing a mask oxide layer on the surface of the N-epitaxial layer above the N+ monocrystalline silicon substrate, and photoetching the mask oxide layer to define a groove region pattern of the MOS transistor unit cell array;
The mask oxide layer which is not protected by the photoresist is etched by a dry method, the N-epitaxial layer corresponding to the pattern of the groove area is exposed, and after the photoresist is removed, the remained mask oxide layer is used as a hard mask;
Forming a groove on the surface of the N-epitaxial layer by taking the hard mask as a blocking layer, and growing a gate oxide layer on the surfaces of the groove and the N-epitaxial layer;
Depositing a polysilicon layer on the gate oxide layer, defining a gate region of a VDMOS structure in a photoetching mode, removing the polysilicon layer and the gate oxide layer by dry etching, and simultaneously forming a VDMOS gate structure and a trench MOSFET gate structure;
Forming a P-type well region layer and an N+ source region layer in the N-epitaxial layer in sequence;
forming an insulating medium layer on the surface of the N+ source electrode region layer, etching the insulating medium layer to form a contact hole, and filling metal into the contact hole;
Depositing metal on the upper surface of the insulating medium layer to form a source metal region layer, wherein the contact hole is connected with the source metal region layer through the contact metal layer to form a source metal electrode;
depositing a metal layer on the bottom surface of the N+ monocrystalline silicon substrate to form a drain metal region layer, wherein the metal layer of the drain metal region layer forms a drain metal electrode;
the gate oxide layer positioned in the groove is a first gate oxide layer, the polysilicon layer transversely contacted with the first gate oxide layer is a first polysilicon layer, and the groove, the first gate oxide layer and the first polysilicon layer form the groove MOSFET gate structure;
the gate oxide layer positioned above the N-epitaxial layer and the P-type well region layer is a second gate oxide layer, the polysilicon layer longitudinally contacted with the second gate oxide layer is a second polysilicon layer, and the second gate oxide layer and the second polysilicon layer form the VDMOS gate structure;
the groove is positioned at the middle position of the two VDMOS gate structures, and the contact hole is positioned between the VDMOS gate structures and the groove;
the metal in the contact hole is a metal layer, the metal layer in the contact hole is in contact with the P-type well region layer and the N+ source region layer to form an ohmic contact layer, and the metal layer is in contact with the source metal region layer;
the unit cell of the MOSFET device is composed of a VDMOS structure and a trench MOSFET structure, and the VDMOS structure and the trench MOSFET structure share the source metal region layer and the drain metal region layer.
6. The method for manufacturing a power MOSFET device according to claim 5, wherein forming a P-type well region layer and an n+ source region layer in the N-epitaxial layer in sequence comprises the steps of:
Implanting P-type impurity ions into the N-epitaxial layer in an automatic alignment mode, and forming a P-type well region layer in the N-epitaxial layer through rapid annealing treatment;
And defining an N+ source region layer above the P-type well region layer, and activating an implanted element through rapid annealing treatment.
7. The method for manufacturing a power MOSFET device according to claim 5, wherein an insulating dielectric layer is formed on the surface of the N+ source region layer, a contact hole is formed by etching the insulating dielectric layer, and a metal layer is filled in the contact hole, comprising the following steps:
Depositing an insulating dielectric layer on the surface of the N+ source electrode region layer, wherein the dielectric layer is one or two of a silicon dioxide layer and a silicon nitride layer;
dry etching is carried out on the insulating dielectric layer, the insulating dielectric layer and the N+ source region layer are penetrated, and the insulating dielectric layer and the N+ source region layer extend to the P-type well region layer to form a contact hole;
And filling metal into the contact hole, depositing a metal titanium bonding layer, depositing a titanium nitride blocking layer on the metal titanium bonding layer, depositing a tungsten metal layer, wherein a P+ contact region is arranged at the P-type well region layer close to the side face end of the contact hole, the metal titanium bonding layer and the titanium nitride blocking layer which are positioned at the side face end of the contact hole form N+ source ohmic contact with the N+ source region layer, the metal titanium bonding layer and the titanium nitride blocking layer which are positioned on the side wall of the contact hole form an ohmic contact layer of the P-type well region layer with the P+ contact region, and the ohmic contact layer and the tungsten metal layer form a contact metal layer.
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