CN113410299B - High-voltage-resistance n-channel LDMOS device and preparation method thereof - Google Patents
High-voltage-resistance n-channel LDMOS device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 17
- 230000008569 process Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 21
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000004047 hole gas Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention relates to a high-voltage-resistant n-channel LDMOS device, and belongs to the technical field of semiconductors. The invention provides a surface super junction structure for an n-channel LDMOS device, which can realize large-range depletion of a drift region channel under a turn-off condition by preparing a comb-finger-shaped p-type semiconductor strip on the surface of the drift region of the device and electrically connecting the p-type semiconductor strip with a source electrode, and the depletion region can bear higher voltage, so that the breakdown characteristic of the device is enhanced. On the other hand, compared with the traditional super junction, the comb-finger-shaped p-type surface voltage-resistant structure is prepared on the surface of the drift region and is not embedded in the drift region of the device, so that the requirement on the process is reduced. Meanwhile, because the comb-finger-shaped p-type surface voltage-resistant structure connected with the source electrode only covers a small part of the area of the drift region, when the device is switched on, the parasitic resistance and the parasitic capacitance which are associated with the device are relatively small, so that the device has relatively good direct current conduction characteristics and high-frequency characteristics.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a high-voltage-resistance n-channel LDMOS device and a preparation method thereof.
Background
In the field of radio frequency and power integrated circuits, the frequency, voltage resistance, on-resistance and other characteristics of devices are important performance indexes for determining circuit characteristics. With the increasing integration level of power integrated circuits, the requirements for various characteristics of the circuits and devices are also increasing. In a radio frequency power device, an LDMOS (laterally diffused metal oxide semiconductor field effect transistor) device exhibits excellent electrical characteristics such as high reliability and high linearity compared with other power devices, and the advantage of compatibility with a conventional CMOS process becomes a research focus in the field of radio frequency power devices, so that how to improve electrical characteristics such as frequency, on-resistance, and withstand voltage of the LDMOS device becomes a focus of attention in the industry.
The rapid development of radio frequency and power integrated circuits also increasingly requires power devices capable of meeting higher frequency and larger voltage withstanding characteristics, and along with the continuous reduction of the device size, the integratability of the devices becomes an important consideration for chip manufacturing while meeting the above characteristics. As shown in fig. 1, the conventional super-junction LDMOS device eliminates the contradiction between the high breakdown voltage and the low on-resistance, and realizes the revolutionary transition from the resistive voltage-withstanding layer to the junction voltage-withstanding layer. However, in the process of super junction, the doping concentration and thickness of the P region and the N region are strictly controlled, which makes the process conditions severe. On the other hand, the PN junction area of the super junction structure is limited by the contact area of the P region and the N region, so the parasitic capacitance increased by the introduction of the super junction structure greatly limits the ac characteristics of the LDMOS. Aiming at the problem, the invention provides the high-voltage-resistant n-channel LDMOS device, which can simplify the process of the super-junction LDMOS, control the junction area of the super-junction and inhibit parasitic capacitance.
Disclosure of Invention
The invention aims to solve the technical problem in the prior art and provides a high-voltage-resistance n-channel LDMOS device and a preparation method thereof.
In order to solve the technical problem, an embodiment of the present invention provides a high voltage-resistant n-channel LDMOS device, which includes a semiconductor substrate, an n-type lightly doped drift region, a p-type well region, a gate structure, an n-type heavily doped source, and an n-type heavily doped drain;
the p-type well region is positioned on one side of the top layer of the semiconductor substrate, and the n-type lightly doped drift region is positioned on the other side of the top layer of the semiconductor substrate; the n-type heavily doped drain electrode is positioned on one side, away from the p-type well region, of the top layer of the n-type lightly doped drift region, and the n-type heavily doped source electrode is positioned on one side, away from the n-type lightly doped drift region, of the top layer of the p-type well region; the grid structure is positioned on the p-type well region and positioned between the n-type heavily doped source electrode and the n-type lightly doped drift region;
the p-type semiconductor blocks are positioned on the n-type lightly doped drift region and positioned between the gate structure and the n-type heavily doped drain, and the p-type semiconductor blocks, the gate structure and the n-type heavily doped drain are arranged at intervals; and a plurality of electrodes are positioned on one side of the plurality of p-type semiconductor blocks close to the grid structure, and the plurality of p-type semiconductor blocks and the source are electrically connected through the plurality of electrodes so as to be mutually communicated.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, an insulating medium is provided between the plurality of p-type semiconductor blocks.
Further, the insulating medium extends towards the drain electrode and fills a gap between the p-type semiconductor block and the n-type heavily doped drain electrode.
Further, the grid structure comprises a grid oxide layer and a grid which are arranged from bottom to top in sequence.
Further, the conductivity type of the semiconductor substrate is n-type or p-type.
In order to solve the above technical problem, an embodiment of the present invention provides a method for manufacturing a high-withstand-voltage n-channel LDMOS device, including the following steps:
injecting phosphorus impurities into the other side of the p-type well region, and forming an n-type heavily doped source electrode after transverse diffusion;
and 6, etching the electrode and the p-type Si layer to the surface of the n-type lightly doped drift region in a graphical mode, forming a plurality of comb-finger-shaped p-type Si blocks and electrodes which are uniformly distributed and extend along the gate leakage direction above the n-type lightly doped drift region, and electrically connecting the plurality of p-type Si blocks and the source electrode through the plurality of electrodes to enable the plurality of p-type Si blocks and the source electrode to be communicated with each other.
The working principle of the invention is as follows:
the invention adopts a comb-finger-shaped p-type surface voltage-resistant structure connected with the source electrode to control the electric field and potential distribution in the drift region of the LDMOS device, thereby effectively improving the breakdown voltage of the device. Compared with the traditional super junction, the comb-finger-shaped p-type surface voltage-resistant structure is prepared on the surface of the drift region, and is not embedded in the drift region of the device, so that the requirement on the process is reduced. Meanwhile, the p-type surface voltage-resistant structure forms a pn junction on the surface of the drift region, so that the depletion region of the drift region is induced to expand downwards to the normal direction of the junction surface when the p-type surface voltage-resistant structure works, and the depletion region of the drift region is forced to expand towards two sides simultaneously, thereby greatly promoting the generation of the depletion layer of the drift region. The structure has relatively higher efficiency because the depletion region in the traditional super junction can only expand along the normal direction of the junction surface. It is particularly noted that when the device is operating in the forward direction, the junction area is small and thus the parasitic capacitance it introduces is relatively small, since no significant expansion of the depletion region of the pn junction occurs. This is a big difference from the case of a conventional superjunction. The junction surface area of the traditional super junction is kept constant when the device is in forward operation and reverse cut-off, so that the parasitic capacitance introduced by the traditional super junction in the forward operation of the device is also very obvious. In summary, compared with the conventional super junction, the p-type surface voltage-resistant structure has the advantages of lower process requirements and smaller parasitic capacitance.
The working principle of the comb finger p-type surface voltage-resistant structure can be described as follows: when the device is turned off, the p-type semiconductor blocks in contact with the source are gradually depleted as the negative voltage on the drain increases, and the fixed positive charge in this depletion region depletes the charge in the drift region. In this process, the drift region under the p-type semiconductor blocks will be depleted first. As the drain negative voltage is further increased, the drift region under the comb finger gap region of the comb finger p-type surface voltage-resistant structure connected to the source is gradually depleted. If the doping concentration of the comb finger-shaped p-type surface voltage-resistant structure connected with the source is proper, the comb finger-shaped p-type semiconductor block connected with the source and a drift region below the comb finger gap region can be simultaneously depleted. Thus, the plurality of p-type semiconductor blocks between the source and the drain of the LDMOS device and the extension region below the p-type semiconductor blocks form a larger depletion region which can bear higher voltage, and the voltage resistance of the device is improved as a direct result.
When the device is conducted, the drift region below the comb finger gap region of the comb finger-shaped p-type surface voltage-resistant structure connected with the source is not influenced by the p-type semiconductor blocks, has higher electron concentration and is a good conduction path, and the on-resistance of the device is ensured not to be remarkably degraded by adopting the voltage-resistant structure. On the other hand, because the comb finger-shaped p-type surface voltage-resistant structure connected with the source only covers a small part of the area of the drift region, the parasitic capacitance introduced by the comb finger-shaped p-type surface voltage-resistant structure is relatively small. The device adopting the voltage-resistant structure has smaller on-resistance and additional capacitance, so that the device has better high-frequency characteristics.
The invention has the beneficial effects that: the LDMOS device provided by the invention can effectively improve the breakdown voltage of the n-channel LDMOS device, and realizes smaller on-resistance and parasitic capacitance of a voltage-withstanding structure while ensuring high breakdown voltage.
Drawings
FIG. 1 is a schematic structural diagram of a conventional n-channel LDMOS device;
fig. 2 is a schematic structural diagram of a high-withstand-voltage n-channel LDMOS device in embodiment 1 of the present invention;
fig. 3 is a schematic structural diagram of a high-withstand-voltage n-channel LDMOS device according to embodiment 2 of the present invention;
fig. 4 is a schematic structural diagram of a high-withstand-voltage n-channel LDMOS device according to embodiment 3 of the present invention;
fig. 5 is a schematic structural diagram of an n-channel LDMOS device with high withstand voltage according to embodiment 4 of the present invention;
fig. 6 is a schematic structural diagram of a depletion region formed in a drift region under a plurality of p-type semiconductor blocks 8 in the high-withstand-voltage n-channel LDMOS device in embodiment 1 of the present invention;
fig. 7 is a schematic structural view of a drift region under a plurality of p-type semiconductor blocks 8 and under a gap region between the plurality of p-type semiconductor blocks 8 while forming a depletion region in the high-withstand-voltage n-channel LDMOS device according to embodiment 1 of the present invention;
fig. 8 to fig. 13 are schematic structural diagrams of a manufacturing method of a high-withstand-voltage n-channel LDMOS device according to embodiment 5 of the present invention.
In the drawings, the reference numbers indicate the following list of parts:
1. the semiconductor device comprises a semiconductor substrate, 2, an n-type lightly doped drift region, 3, a p-type well region, 4, a gate oxide layer, 5, a gate, 6, an n-type heavily doped source electrode, 7, an n-type heavily doped drain electrode, 8, a p-type semiconductor block, 9, an insulating medium, 10 and electrodes.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 2, an n-channel LDMOS device with high withstand voltage provided in embodiment 1 of the present invention includes a semiconductor substrate 1, an n-type lightly doped drift region 2, a p-type well region 3, a gate structure, an n-type heavily doped source 6, and an n-type heavily doped drain 7;
the p-type well region 3 is positioned on one side of the top layer of the semiconductor substrate 1, and the n-type lightly doped drift region 2 is positioned on the other side of the top layer of the semiconductor substrate 1; the n-type heavily doped drain 7 is positioned on one side, away from the p-type well region 3, of the top layer of the n-type lightly doped drift region 2, and the n-type heavily doped source 6 is positioned on one side, away from the n-type lightly doped drift region 2, of the top layer of the p-type well region 3; the grid structure is positioned on the p-type well region 3 and is positioned between the n-type heavily doped source electrode 6 and the n-type lightly doped drift region 2;
the p-type semiconductor blocks 8 are positioned on the n-type lightly doped drift region 2 and positioned between the gate structure and the n-type heavily doped drain 7, and the p-type semiconductor blocks 8 are arranged at intervals with the gate structure and the n-type heavily doped drain 7; a plurality of electrodes 10 are positioned on the plurality of p-type semiconductor blocks 8 on a side closer to the gate structure, and the plurality of p-type semiconductor blocks 8 and the source 6 are electrically connected by the plurality of electrodes 10 so that the plurality of p-type semiconductor blocks 8 and the source 6 communicate with each other.
As shown in fig. 3, in the n-channel LDMOS device with high withstand voltage provided in embodiment 2 of the present invention, an insulating dielectric 9 is provided between the plurality of p-type semiconductor blocks 8 on the basis of embodiment 1.
As shown in fig. 4, in the n-channel LDMOS device with high withstand voltage provided in embodiment 3 of the present invention, on the basis of embodiment 2, the insulating medium 9 is extended toward the drain 7 and fills a portion of the gap between the p-type semiconductor block 8 and the heavily doped n-type drain 7.
As shown in fig. 5, in the n-channel LDMOS device with high withstand voltage provided in embodiment 4 of the present invention, on the basis of embodiment 2, the insulating medium 9 is extended toward the drain 7 and fills the entire gap between the p-type semiconductor block 8 and the heavily doped n-type drain 7.
Optionally, the gate structure comprises a gate oxide layer 4 and a gate 5 arranged in sequence from bottom to top.
Optionally, the conductivity type of the semiconductor substrate 1 is n-type or p-type.
The working process of the invention is explained in detail below with reference to fig. 6 and 7:
for a conventional n-channel LDMOS device, when a large negative voltage is applied to the drain, the drift region between the gate and the drain is difficult to fully deplete, causing the voltage to drop mainly near the edge of the gate, which results in a large electric field peak, causing the device to break down.
The invention provides an n-channel LDMOS device with a comb-finger-shaped p-type surface voltage-resistant structure connected with a source, and a plurality of p-type semiconductor blocks 8 are arranged between a grid electrode 5 and a drain electrode 7 of the device. As the negative voltage on the drain increases, the drift region under the p-type semiconductor blocks 8 depletes first, as shown in fig. 6. When the negative drain voltage is large enough, the depletion regions below the p-type semiconductor blocks expand to the periphery, so that the two-dimensional hole gas in the whole comb finger-shaped surface voltage-resistant structure and the region below the gaps of the comb finger-shaped surface voltage-resistant structure is also depleted, and the depletion regions gradually expand until the two-dimensional hole gas is connected to form a large depletion region which is approximately rectangular, as shown in fig. 7. The newly formed depletion region can play a role in resisting voltage, and the comb finger-shaped p-type surface voltage-resisting structure is electrically connected with the source electrode, so that a voltage distribution region which is concentrated and falls on the edge of the grid electrode originally is greatly expanded, the electric field peak of a drift region between the grid electrode and the drain electrode is effectively inhibited, the breakdown voltage of the device is improved, and the voltage-resisting capacity of the device is greatly improved.
As shown in fig. 8 to 13, a method for manufacturing a high-withstand-voltage n-channel LDMOS device provided in embodiment 5 of the present invention includes the following steps:
and 6, etching the electrode and the p-type Si layer to the surface of the n-type lightly doped drift region 2 in a patterning mode, forming a plurality of comb-finger-shaped p-type Si blocks and electrodes 10 which are uniformly distributed and extend along the gate-drain direction above the n-type lightly doped drift region 2, and electrically connecting the plurality of p-type Si blocks and the source electrode 6 through the plurality of electrodes 10 to enable the plurality of p-type Si blocks and the source electrode 6 to be communicated with each other, as shown in FIG. 13.
In the above embodiment, the semiconductor substrate 1 is an N-type substrate having a (001) crystal orientation.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. An n-channel LDMOS device with high voltage resistance comprises a semiconductor substrate (1), an n-type lightly doped drift region (2), a p-type well region (3), a grid structure, an n-type heavily doped source electrode (6) and an n-type heavily doped drain electrode (7);
the p-type well region (3) is positioned on one side of the top layer of the semiconductor substrate (1), and the n-type lightly doped drift region (2) is positioned on the other side of the top layer of the semiconductor substrate (1); the n-type heavily doped drain (7) is positioned on one side, away from the p-type well region (3), of the top layer of the n-type lightly doped drift region (2), and the n-type heavily doped source (6) is positioned on one side, away from the n-type lightly doped drift region (2), of the top layer of the p-type well region (3); the grid structure is positioned on the p-type well region (3) and is positioned between the n-type heavily doped source electrode (6) and the n-type lightly doped drift region (2);
the semiconductor device is characterized by further comprising a plurality of comb-finger-shaped p-type semiconductor blocks (8) extending along the gate-drain direction and a plurality of electrodes (10), wherein the p-type semiconductor blocks (8) are located on the n-type lightly doped drift region (2) and located between the gate structure and the n-type heavily doped drain (7), and the p-type semiconductor blocks (8) are arranged at intervals with the gate structure and the n-type heavily doped drain (7); the electrodes (10) are positioned on one side, close to the grid structure, of the p-type semiconductor blocks (8), the p-type semiconductor blocks (8) are electrically connected with the n-type heavily doped source electrode (6) through the electrodes (10), and the p-type semiconductor blocks (8) are communicated with the n-type heavily doped source electrode (6).
2. A high withstand voltage n-channel LDMOS device as set forth in claim 1, wherein an insulating dielectric (9) is provided between said plurality of p-type semiconductor blocks (8).
3. A high voltage tolerant n-channel LDMOS device as claimed in claim 2, wherein said insulating dielectric (9) extends towards said heavily doped n-type drain (7) and fills the gap between said p-type semiconductor body (8) and said heavily doped n-type drain (7).
4. A high withstand voltage n-channel LDMOS device as set forth in claim 1, wherein said gate structure comprises a gate oxide layer (4) and a gate electrode (5) arranged in this order from below.
5. A high withstand voltage n-channel LDMOS device as set forth in claim 1, wherein said semiconductor substrate (1) is of n-type or p-type conductivity type.
6. A preparation method of a high-voltage-resistance n-channel LDMOS device is characterized by comprising the following steps:
step 1, forming a p-type well region (3) on one side of the top layer of a semiconductor substrate (1) by adopting a photoetching process and an ion implantation process, and forming an n-type lightly doped drift region (2) on the other side of the top layer of the semiconductor substrate (1);
step 2, sequentially forming a gate oxide layer and polycrystalline silicon by adopting oxidation and deposition processes, then carrying out phosphorus diffusion doping, and forming a gate oxide layer (4) and a gate (5) on one side of the p-type well region (3) close to the n-type lightly doped drift region (2) after etching;
step 3, injecting phosphorus impurities into the other side of the p-type well region (3), and forming an n-type heavily doped source electrode (6) after transverse diffusion;
step 4, injecting phosphorus impurities into one side of the n-type lightly doped drift region (2) far away from the p-type well region (3) to form an n-type heavily doped drain (7);
step 5, forming a p-type Si layer above the n-type lightly doped drift region (2) and between the grid (5) and the n-type heavily doped drain (7), and depositing an electrode on one side of the p-type Si layer close to the grid (5);
and 6, etching the electrode and the p-type Si layer to the surface of the n-type lightly doped drift region (2) in a graphical mode, forming a plurality of comb-finger-shaped p-type Si blocks and electrodes (10) which are uniformly distributed and extend along the gate-drain direction above the n-type lightly doped drift region (2), and electrically connecting the p-type Si blocks with the n-type heavily doped source electrode (6) through the electrodes (10) to enable the p-type Si blocks and the n-type heavily doped source electrode (6) to be communicated with each other.
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| CN101916780A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | LDMOS device with multilayer super-junction structure |
| CN103165678B (en) * | 2013-03-12 | 2015-04-15 | 电子科技大学 | Super junction lateral double-diffused metal-oxide semiconductor (LDMOS) device |
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