CN101777584B - P-channel laterally double diffused metal oxide semiconductor device - Google Patents
P-channel laterally double diffused metal oxide semiconductor device Download PDFInfo
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- CN101777584B CN101777584B CN2010103009599A CN201010300959A CN101777584B CN 101777584 B CN101777584 B CN 101777584B CN 2010103009599 A CN2010103009599 A CN 2010103009599A CN 201010300959 A CN201010300959 A CN 201010300959A CN 101777584 B CN101777584 B CN 101777584B
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Abstract
The invention relates to an LDMOS (Laterally Double-diffused Metal Oxide Semiconductor) device on an SOI (Silicon On Insulator) substrate, and discloses a p-channel laterally double diffused metal oxide semiconductor device of the SOI substrate aiming at the problem of immaturely puncturing a device in the prior art and the contradiction between the doping concentration of a drain extension area and the voltage resistance of a device. The p-channel laterally double diffused metal oxide semiconductor device comprises a substrate, an oxygen buried layer and an n-type doping layer along a Y direction from bottom to top, wherein a source n-well is formed at one end of the X direction of the n-type doping layer, while a drain p-well is formed at the other end; the drain extension area is arranged between the source n-well and the drain p-well and consists of an n-type impurity strip and a p-type impurity strip which are staggered in juxtaposition along a Z direction, and two ends of the X direction of the n-type impurity strip and the p-type impurity strip are respectively connected with the source n-well and the drain p-well. The invention improves the voltage resistance of the device and reduces the on-resistance of the device at the same time, thereby being very suitable for manufacturing a PDP (Plasma Display Panel) addressing integrated circuit.
Description
Technical field
The present invention relates to LDMOS (lateral double diffusion metal oxide semiconductor) device on SOI (silicon on the dielectric substrate) base, the super knot of particularly a kind of high pressure (Super Junction) p raceway groove LDMOS device.
Background technology
The SOI technology is subjected to people's favor in the semiconductor integrated circuit technical field with its ideal medium isolation performance, simple relatively dielectric isolation technology.The SOI device has that ghost effect is little, speed is fast, low in energy consumption, advantage such as integrated level is high, anti-irradiation ability is strong.But integrating with LDMOS device based on the SOI technology, owing to adopt dielectric isolation completely between active device and material substrate and other high-low voltage devices, help avoiding LDMOS device generation latch-up, and device is integrated in the high-voltage power integrated circuit with other high-low voltage device monolithics as high-end or low-end switch easily.
Fig. 1 shows conventional thin layer SOI base p raceway groove LDMOS device architecture schematic diagram.Wherein 1 is substrate (being generally p type substrate), 2 is oxygen buried layer, 3 is source electrode n trap, herein as the channel region of p raceway groove LDMOS device, 4 are source electrode n+ back of the body gate contact zone, 51,52 is ohm hole, and the active area current potential is picked out, and 61 and 62 are respectively source metal field plate and drain metal field plate, 7 is source electrode p+ contact zone, 8 is source electrode p type expansion area, and for p raceway groove LDMOS device provides continuous raceway groove, 9 is polygate electrodes, 10 is field oxide, 11 is medium (PMD) before the metal, and 12 are drain electrode p+ contact zone, and 13 is p type drift region.Above-mentioned its withstand voltage generally≤300V of thin layer SOI base p raceway groove LDMOS device, during device work, source electrode is a high potential, its depletion layer begins to exhaust from source electrode n trap 3 and p type drift region 13PN junction boundary, because depletion layer is from high potential PN junction border, make that source electrode n trap 3 and 13PN knot place, p type drift region electric field curvature are big, finally make device breakdown.Equipotentiality line chart when Fig. 2 is the above-mentioned device breakdown of utilizing that the MEDICI of two Dimension Numerical Value simulation software draws, when source electrode was high level, depletion layer began to exhaust to the right from left side A point, finally made the excessive device breakdown that causes of A point curvature.
Patent Lateral Thin-Film Silicon-On-Insulator (SOI) PMOS Device Having a Drain Extension Region, U.S.Pat.NO.6,127,703.NXP propose a kind of novel thin layer SOI base p raceway groove LDMOS device, its thought of dealing with problems is for passing through to introduce drain extensions, make depletion layer begin to exhaust, avoided high potential source end to occur the possibility that curvature punctures too early from drain electrode.Fig. 3 has provided this device architecture schematic diagram, wherein 1 is p type substrate, 2 is oxygen buried layer, 3 is source electrode n trap, as the channel region of p raceway groove LDMOS device, 4 are source electrode n+ back of the body gate contact zone herein, and 51,52 is ohm hole, the active area current potential is picked out, 6 is source electrode p+ contact zone, and 7 is polygate electrodes, and 8 is gate oxide, 91 and 92 are respectively source metal field plate and drain metal field plate, 10 are n type doped layer (or being called the drift region), and 11 is medium before the metal, and 12 is p type drain extensions, 13 are drain electrode p+ contact zone, and 14 are drain electrode p trap.Device is in OFF state, and when source electrode applied high level, drain electrode p trap 14 began to exhaust with the PN junction that n type drift region 10 constitutes, up to being depleted to the high level source electrode.Thereby avoided source electrode curvature excessive, the device premature breakdown.During P raceway groove LDMOS break-over of device, source electrode p+ contact zone 6 is by the inversion layer of source electrode n trap raceway groove 3, again by drain extensions 12 conduction currents.For the drift region is exhausted entirely, drain extensions 12 needs to satisfy the requirement of reduction surface field (RESURF) technology dopant dose, makes its dopant dose can not surpass 1E12/cm
3, the reduction of conducting resistance is restricted.
Summary of the invention
(for the convenience on describing, the present invention also abbreviates " the silica-based p channel laterally double diffused metal oxide semiconductor device on the dielectric substrate " as sometimes: SOI base p channel laterally double diffused metal oxide semiconductor device, p channel laterally double diffused metal oxide semiconductor device, SOI base p raceway groove LDMOS device or directly be called device.)
The technical problem to be solved in the present invention, begin to exhaust at the base of the SOI on prior art p raceway groove LDMOS device source end PN junction exactly, the problem that makes device prematurity puncture, and the contradiction of drain extensions doping content and device withstand voltage, the silica-based p channel laterally double diffused metal oxide semiconductor device on a kind of dielectric substrate is provided.
The present invention solve the technical problem, and the technical scheme of employing is that the p channel laterally double diffused metal oxide semiconductor device comprises from bottom to top substrate, oxygen buried layer, n type doped layer; Described n type doped layer one end forms source electrode n trap, and the other end forms drain electrode p trap, is drain extensions between source electrode n trap and the drain electrode p trap; It is characterized in that, described drain extensions is made of staggered n type impurity bar and p type impurity bar side by side, the two ends of described n type impurity bar and p type impurity bar join with source electrode n trap and drain electrode p trap respectively, and described p type impurity bar doping content equals or is slightly larger than n type impurity bar doping content.
Further, the degree of depth of described drain extensions is less than the thickness of n type doped layer.
Further, when described device was in OFF state, described n type impurity bar and p type impurity bar were depleted.
Concrete, described source electrode n trap, drain electrode p trap and n type impurity bar and p type impurity bar all are arranged in above the n type doped layer and forgive at n type doped layer.
Concrete, the width of described drain electrode p trap and source electrode n trap is not less than the width sum of n type impurity bar and p type impurity bar.
Concrete, the width of described p type impurity bar and the degree of depth equal or are slightly larger than the width and the degree of depth of n type impurity bar.
Further, the impurity implantation dosage of described n type impurity bar and p type impurity bar becomes tangible inverse relation with its width.
Further, described device is used for the active element of integrated circuit.
Further, described integrated circuit is a PDP addressing integrated circuit.
The invention has the beneficial effects as follows, when improving p raceway groove LDMOS device withstand voltage, reduced break-over of device resistance, can reach the requirement of withstand voltage of 200～700V, be suitable for very much making PDP (plasma display panel (PDP)) addressing integrated circuit.
Description of drawings
Fig. 1 is a prior art thin layer SOI base p raceway groove LDMOS device architecture schematic diagram.
Wherein Reference numeral is as follows: 1 is p type substrate, and 2 is oxygen buried layer, and 3 is source electrode n trap, 4 are source electrode n+ back of the body gate contact zone, 51,52 is ohm hole, and 61,62 are respectively source metal field plate and drain metal field plate, and 7 is source electrode p+ contact zone, 8 is source electrode p type expansion area, 9 is polygate electrodes, and 10 is field oxide, and 11 is medium before the metal, 12 are drain electrode p+ contact zone, and 13 is p type drift region.
Potential profile when Fig. 2 is a device breakdown shown in Figure 1.
Fig. 3 is U.S.Pat.NO.6,127,703 disclosed thin layer SOI base p raceway groove LDMOS device architecture schematic diagrames.
Wherein Reference numeral is as follows: 1 is p type substrate, and 2 is oxygen buried layer, and 3 is source electrode n trap, 4 are source electrode n+ back of the body gate contact zone, and 51,52 is ohm hole, and 6 is source electrode p+ contact zone, 7 is polygate electrodes, 8 is gate oxide, and 91,92 is source metal field plate and drain metal field plate, and 10 is n type drift region, 11 is medium before the metal, 12 is p type drain extensions, and 13 are drain electrode p+ contact zone, and 14 are drain electrode p trap.
Fig. 4 is the SOI base p raceway groove LDMOS device architecture schematic diagram of the embodiment of the invention.
Reference numeral is as follows: 1 is p type substrate, and 2 is oxygen buried layer, and 10 is n type doped layer (drift region), and 3 is that source electrode n trap, 12 is drain electrode p trap, and 5 is the p+ contact zone, and 4 are back of the body grid n+ contact zone.11 are drain electrode p+ contact zone.81 ... 8i is a n type impurity bar, 91 ... 9i is a p type impurity bar, and 7 is polygate electrodes, 6 gate oxides.
Equipotential lines distribution map when Fig. 5 is Fig. 4 device OFF state.
Fig. 6 laterally reduces surface field (RESURF) device surface field distribution schematic diagram.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that the specific embodiment that describes below only in order to explanation the present invention, and be not used in qualification the present invention.
SOI base p channel laterally double diffused metal oxide semiconductor device of the present invention, at top layer n type doped layer (drift region) staggered p type impurity bar and n type impurity bar side by side is set, when device is in closed condition, reach charge balance, distribute for the drift region internal electric field and can not cause too big influence.Device of the present invention is provided with the p trap at drain terminal, and when source electrode was high potential, drain terminal PN junction (interface of drain electrode p trap and top layer n type doped layer) was born withstand voltage.By exhausting moving of direction, avoided source end PN junction curvature excessive and puncture voltage that cause descends.P type impurity bar is subjected to adjacent n type impurity bar and n type doped layer exhausts jointly in the drift region, and p type impurity bar can carry out than heavy doping, realizes low on-resistance.P raceway groove LDMOS device of the present invention can be realized the requirement of 200～700V device withstand voltage, can be used in the high voltage level displacement unit, in PDP addressing integrated circuit.
Embodiment
Fig. 4 is the p channel laterally double diffused metal oxide semiconductor device cutaway view of present embodiment.This routine SOI base p raceway groove LDMOS device by p type impurity bar and n type impurity bar are set at top layer n type doped layer, is provided with the p trap at drain terminal, has successfully realized exhausting direction and has shifted, and reaches high withstand voltage purpose.Be p type substrate 1, oxygen buried layer 2 from bottom to top, on oxygen buried layer 2, form n type doped layer 10 along the Y direction among Fig. 4.In the n type doped layer 10, form source electrode n trap 3 by diffusion along directions X one end, as the channel region of p raceway groove LDMOS device, the other end forms drain electrode p trap 12.Zone between source electrode n trap 3 and the drain electrode p trap 12 is a drain extensions.Form source electrode p+ contact zone 5 and n+ back of the body gate contact zone 4 in the source electrode n trap 3, the source electrode (S) that its common extraction electrode is this routine device.Form drain electrode p+ contact zone 11 in the drain electrode p trap 12, its extraction electrode is the drain electrode (D) of this routine device.This routine drain extensions diffuses to form by the n type impurity bar 81 that interlocks along the Z direction side by side by doping ... 8i and p type impurity bar 91 ... 9i.The two ends of these impurity bar directions Xs join with source electrode n trap 3 and drain electrode p trap 12 respectively, and all impurity bars (drain extensions that this is routine) should be less than the thickness of n type doped layer 10 in the degree of depth of Y direction, and promptly drain extensions does not contact with oxygen buried layer 2.Said n type impurity bar 81 ... 8i, p type impurity bar 91 ... 9i, source electrode n trap 3 and drain electrode p trap 12 all are arranged in above the n type doped layer 10 and forgive at n type doped layer 10, and wherein source electrode n trap 3 and/or drain electrode p trap 12 can penetrate n type doped layer 10 and join with oxygen buried layer.This routine gate electrode 7 is positioned at gate oxide 6 tops, and its extraction electrode is the grid (G) of this routine device.Gate electrode 7 should stride across source electrode n trap 3 with gate oxide 6 at the width of directions X, and left end extends to source electrode p+ contact zone 5, and right-hand member extends to drain extensions and (covers n type impurity bar 81 ... 8i and p type impurity bar 91 ... the end of 9i), referring to Fig. 4.This routine device is when OFF state, exhaust left with the PN junction that n type doped layer 10 forms by the right drain electrode p trap 12, electric current is by hole inversion layer, drift region p type impurity bar 91 on source electrode p+ contact zone 5, the source electrode n trap 3 during conducting ... 9i, drain electrode p trap 12 are collected by drain electrode p+ contact zone 11, form current path.The p type impurity bar is exhausted by side by side n type impurity bar when OFF state, is current path during ON state.Broken the drawback that conventional SOI base p raceway groove LDMOS device source end begins to exhaust, made SOI base p channel laterally double diffused metal oxide semiconductor device drift region can bear high pressure, realized the demand of high voltage level shift circuit for thick grid oxygen p raceway groove LDMOS.
When this routine device was in OFF state, n type doped layer 10 top n type impurity bars and p type impurity bar were owing to the charge balance effect, and it exhausts mutually, is equivalent to light doping section, can not cause big influence to the drift region Electric Field Distribution at high withstand voltage zone.By drain electrode p trap 12 is set at n type doped layer 10, shift conventional SOI base p raceway groove LDMOS source electrode PN junction, the direction that exhausts of device is shifted, thereby realize that device drift region exhausts to the high level direction from the low level direction, reach the high withstand voltage demand of device.Because p type impurity bar exhausts jointly with side by side n type impurity bar and n type doped layer 10 simultaneously, p type impurity bar doping content can equal or be slightly larger than n type impurity bar doping content, realizes satisfying the demand of the low conduction loss of p raceway groove LDMOS than heavy doping.Same reason, p type impurity bar can equal or be slightly larger than n type impurity bar in the width of Z direction and the degree of depth of Y direction at the width of Z direction and the degree of depth of Y direction.Guaranteeing under the condition that the unnecessary electric charge of p type impurity bar can further be exhausted by n type doped layer 10 that the doping content of p type impurity bar and energising cross section (size of Z and Y direction) can be slightly larger than n type impurity bar, thereby further reduce conducting resistance and loss.All can effectively participate in conduction in order to satisfy all impurity bars (comprising p type impurity bar and n type impurity bar), drain electrode p trap 12 and source electrode n trap 3 should be more than or equal to n type impurity bar and the p type impurity bar width sums in the Z direction at the width of Z direction.
Equipotential lines distribution map when Fig. 5 is a silica-based p channel laterally double diffused metal oxide semiconductor device OFF state on the dielectric substrate of the present invention, source voltage is 470V, adjacent equipotential lines electrical potential difference is 15V, surveys and draws concrete parameter to be: oxygen buried layer 2 thickness (Y direction size) 2～5 μ m; N type doped layer 10 thickness (Y direction size) 2～20 μ m, length (directions X size) 30～70 μ m, its impurity satisfies the requirement of RESURF implantation dosage; Source electrode n trap 3 length (directions X size) 2～6 μ m, implantation dosage is 8E12～1.6E13/cm
2, junction depth (Y direction size) 1.5～4 μ m, drain electrode p trap 12 implantation dosages are 1E13～5E13/cm
2P type impurity bar and n type impurity bar junction depth be (Y direction size) 1～3 μ m approximately, bar wide (Z direction size) 1～3 μ m, and implantation dosage is 1.2E12～4E12/cm
2And become obvious inverse relation with bar is wide.Fig. 5 has confirmed that by simulation software it exhausts direction and changes device when the OFF state, and high pressure (being 470V herein) down device drift region take place to exhaust entirely.
Fig. 6 has provided horizontal reduction surface field RESURF device surface field distribution schematic diagram, and its surface field of device architecture shown in Figure 1 is single RESURF device surface Electric Field Distribution; Its surface field of device architecture shown in Figure 3 is two RESURF device surface Electric Field Distribution; And the present invention dielectric substrate on silica-based p channel laterally double diffused metal oxide semiconductor device, its surface field is a 3D RESURF device surface Electric Field Distribution.As seen in Figure 6, under the identical condition of drift region length, device of the present invention has uniform electric field distribution, thereby can stand bigger puncture voltage.
Silica-based p channel laterally double diffused metal oxide semiconductor device on the dielectric substrate of the present invention, by being set, p type impurity bar and n type impurity bar constitute the expansion area, building in the drift region, at drain electrode the p trap is set and has realized the high withstand voltage and ON state low resistance of OFF state, can reach the requirement of 200V-700V device withstand voltage, can be used in the high voltage level displacement unit, its level shift unit is applicable as among the PDP addressing IC.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, any modification of being done within every the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1.p channel laterally double diffused metal oxide semiconductor device comprises from bottom to top substrate, oxygen buried layer, n type doped layer; Described n type doped layer one end forms source electrode n trap, and the other end forms drain electrode p trap, is drain extensions between source electrode n trap and the drain electrode p trap; It is characterized in that, described drain extensions is made of staggered n type impurity bar and p type impurity bar side by side, the two ends of described n type impurity bar and p type impurity bar join with source electrode n trap and drain electrode p trap respectively, and described p type impurity bar doping content equals or is slightly larger than n type impurity bar doping content.
2. p channel laterally double diffused metal oxide semiconductor device according to claim 1 is characterized in that the degree of depth of described drain extensions is less than the thickness of n type doped layer.
3. p channel laterally double diffused metal oxide semiconductor device according to claim 1 is characterized in that, when described device was in OFF state, described n type impurity bar and p type impurity bar were depleted.
4. p channel laterally double diffused metal oxide semiconductor device according to claim 1 is characterized in that, described source electrode n trap, drain electrode p trap and n type impurity bar and p type impurity bar all are arranged in above the n type doped layer and forgive at n type doped layer.
5. p channel laterally double diffused metal oxide semiconductor device according to claim 1 is characterized in that, the width of described drain electrode p trap and source electrode n trap is not less than the width sum of n type impurity bar and p type impurity bar.
6. p channel laterally double diffused metal oxide semiconductor device according to claim 1 is characterized in that, the width of described p type impurity bar and the degree of depth equal or be slightly larger than the width and the degree of depth of n type impurity bar.
7. p channel laterally double diffused metal oxide semiconductor device according to claim 1 is characterized in that, the impurity implantation dosage of described n type impurity bar and p type impurity bar becomes tangible inverse relation with its width.
8. p channel laterally double diffused metal oxide semiconductor device according to claim 1 is characterized in that described device is used for the active element of integrated circuit.
9. p channel laterally double diffused metal oxide semiconductor device according to claim 8 is characterized in that, described integrated circuit is a PDP addressing integrated circuit.
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| CN102339853B (en) * | 2010-01-29 | 2013-08-07 | 四川长虹电器股份有限公司 | P-channel lateral double-diffusion metal oxide semiconductor device |
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| CN102569359B (en) * | 2010-12-08 | 2015-07-29 | 四川长虹电器股份有限公司 | The horizontal double-diffused device of partial SOI |
| CN102231389A (en) * | 2011-05-27 | 2011-11-02 | 四川长虹电器股份有限公司 | P type metal oxide semiconductor transistor for plasma display panel (PDP) driving chip |
| CN113410299B (en) * | 2020-03-16 | 2023-01-31 | 电子科技大学 | High-voltage-resistance n-channel LDMOS device and preparation method thereof |
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| CN1926690A (en) * | 2004-01-16 | 2007-03-07 | 崇贸科技股份有限公司 | Isolated high-voltage LDMOS transistor having a split well structure |
| CN100438032C (en) * | 2006-02-22 | 2008-11-26 | 崇贸科技股份有限公司 | High-voltage low-on resistance transmistor with irradiation structure and isolation effect |
| CN101771082A (en) * | 2009-12-30 | 2010-07-07 | 四川长虹电器股份有限公司 | Silicon-based lateral double-diffused metal-oxide semiconductor device on insulating substrate |
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| CN1926690A (en) * | 2004-01-16 | 2007-03-07 | 崇贸科技股份有限公司 | Isolated high-voltage LDMOS transistor having a split well structure |
| CN100438032C (en) * | 2006-02-22 | 2008-11-26 | 崇贸科技股份有限公司 | High-voltage low-on resistance transmistor with irradiation structure and isolation effect |
| CN101771082A (en) * | 2009-12-30 | 2010-07-07 | 四川长虹电器股份有限公司 | Silicon-based lateral double-diffused metal-oxide semiconductor device on insulating substrate |
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| CN102339853B (en) * | 2010-01-29 | 2013-08-07 | 四川长虹电器股份有限公司 | P-channel lateral double-diffusion metal oxide semiconductor device |
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