CN107871782B - Double-diffusion metal oxide semiconductor element and manufacturing method thereof - Google Patents
Double-diffusion metal oxide semiconductor element and manufacturing method thereof Download PDFInfo
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- CN107871782B CN107871782B CN201710062427.8A CN201710062427A CN107871782B CN 107871782 B CN107871782 B CN 107871782B CN 201710062427 A CN201710062427 A CN 201710062427A CN 107871782 B CN107871782 B CN 107871782B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 26
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000009792 diffusion process Methods 0.000 title abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 210000000746 body region Anatomy 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims description 36
- 239000012535 impurity Substances 0.000 claims description 32
- 238000005468 ion implantation Methods 0.000 description 14
- 230000015556 catabolic process Effects 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000002513 implantation Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention provides a double-diffusion metal oxide semiconductor element and a manufacturing method thereof. The double-diffused metal oxide semiconductor element comprises: the semiconductor device comprises a substrate, an epitaxial layer, a high-voltage well, a body region, a grid electrode, a source electrode, a drain electrode, a drift buried region and a buried region. A first PN junction is arranged between the high-voltage trap and the upper surface of the substrate. The drift buried region has a second conductivity type and the buried region has a first conductivity type. In the channel direction, the length of the buried region is greater than or equal to the length of the drift buried region. Viewed from the cross-sectional view, a second PN junction is formed between the drift buried region and the buried region or between the high-voltage well and the buried region in the channel direction. The second PN junction has a depth, as viewed in cross-section, calculated vertically downward from the surface of the epitaxial layer that is shallower than the depth, as calculated vertically downward from the surface of the epitaxial layer, of the first PN junction.
Description
Technical Field
The present invention relates to a Double Diffused Metal Oxide Semiconductor device and a method for manufacturing the same, and more particularly, to a Double Diffused Metal Oxide Semiconductor device and a method for manufacturing the same, which can improve a breakdown protection voltage of the Double Diffused Metal Oxide Semiconductor (DMOS) device during a non-turn-on operation and can reduce an on-resistance during a turn-on operation.
Background
Referring to fig. 1, a cross-sectional view of a prior art nmos device is shown. As shown in fig. 1, a prior art nmos device 100 includes: substrate 17, insulating structure 13, high voltage well 15, body region 16, source 18, drain 19, and gate 11. The substrate 17 has a P-type conductivity, the high voltage well 15 has an N-type conductivity and is formed on the substrate 17, and the insulating structure 13 is a local oxidation of silicon (LOCOS) structure to define an operation region 13a, which is a main active region of the prior art nmos device 100 during operation. The extent of the operating field 13a is indicated in fig. 1 by two arrows pointing in opposite directions.
This prior art nmos device 100 has a drawback: in the prior art nmos device 100, the substrate 17 is electrically connected to a ground potential (not shown) under the conducting and non-conducting operating conditions, and the potential of the high-voltage well 15 is relatively high, which causes the high-voltage well 15 to be completely depleted in the operating region 13a during the conducting operation, so that the on-resistance is relatively high, thereby limiting the operating speed and the device performance.
To improve the above drawback, another prior art proposes to form a reduced surface field (RESURF) effect in the DMOS device, so as to suppress the high electric field of the DMOS device during the off-state operation, thereby increasing the breakdown voltage of the device. However, this prior art approach still has disadvantages: although the device breakdown protection voltage is increased, the on-resistance is relatively increased, which limits the operation speed and the device performance.
Accordingly, the present invention provides a double-diffused metal oxide semiconductor device and a method for manufacturing the same, wherein the device breakdown protection voltage is increased during the off operation of the double-diffused metal oxide semiconductor device, and the on resistance is reduced during the on operation of the double-diffused metal oxide semiconductor device.
Disclosure of Invention
The present invention is directed to overcoming the drawbacks and drawbacks of the prior art, and providing a method for manufacturing a double diffused metal oxide semiconductor device, which can increase the breakdown voltage of the double diffused metal oxide semiconductor device during the off operation and reduce the on resistance of the double diffused metal oxide semiconductor device during the on operation.
To achieve the above object, in one aspect, the present invention provides a double Diffused Metal Oxide Semiconductor (DMOS) device including: the substrate is provided with a first conductive type, and an upper surface and a lower surface which are opposite to each other in a vertical direction; an epitaxial layer formed on the substrate, having an epitaxial layer surface opposite to the upper surface, and stacked and connected on the upper surface in the vertical direction; a high voltage well formed in the epitaxial layer, having a second conductivity type, stacked and connected on the upper surface of the substrate in the vertical direction, wherein a first PN junction is formed between the high voltage well and the upper surface of the substrate; a body region formed in the epitaxial layer, having a first conductivity type, stacked and connected below the surface of the epitaxial layer in the vertical direction, and having a channel-direction junction with the high-voltage well in the channel direction as viewed in the cross-sectional view; a gate formed on the epitaxial layer, the gate being stacked and connected to the surface of the epitaxial layer in the vertical direction, and the gate covering at least a portion of the channel-direction junction as viewed in cross-section; a source electrode formed in the epitaxial layer, having a second conductivity type, stacked and connected below the surface of the epitaxial layer in the vertical direction, and located in the body region as viewed in the cross-sectional view; a drain formed in the epitaxial layer, having a second conductivity type, stacked and connected below the surface of the epitaxial layer in the vertical direction, wherein the source and the drain are located at different sides of the junction in the channel direction, and the drain and the gate are separated by the high voltage well as viewed in a cross-sectional view; a drift buried region formed in the epitaxial layer and having a second conductivity type, wherein, viewed from a cross-sectional view, in the channel direction, a part of the drift buried region is located right below the drain, and the length of the drift buried region is greater than or equal to the length of the drain; and a buried region formed in the substrate and the epitaxial layer, having a first conductivity type, and in the vertical direction, a part of the buried region is located in the substrate, and another part of the buried region is located in the epitaxial layer, wherein, viewed from a cross-sectional view, in the channel direction, at least a part of the buried region is located right below the drift buried region, and the length of the buried region is greater than or equal to the length of the drain, wherein the length of the buried region is greater than or equal to the length of the drift buried region; wherein, viewed from a cross-sectional view, a second PN junction is formed between the drift buried region and the buried region or between the high voltage well and the buried region in the channel direction, and, viewed from a cross-sectional view, the second PN junction has a depth, which is calculated from the surface of the epitaxial layer downward along the vertical direction, shallower than the depth, which is calculated from the surface of the epitaxial layer downward along the vertical direction, of the first PN junction; the drift buried region is provided with a first boundary close to the grid and a second boundary far away from the grid in the channel direction, and the buried region is provided with a third boundary close to the grid and a fourth boundary far away from the grid in the channel direction; wherein the first boundary and the third boundary are between the drain and the channel-direction junction in the channel direction; the second boundary and the fourth boundary at least exceed a fifth boundary in the channel direction, wherein the fifth boundary is located between the drain and an insulating structure near the drain, wherein the insulating structure is used for defining an element region of the DMOS element.
In a preferred embodiment, the dmos device further includes a field oxide region formed in the operating region on the epitaxial layer, the field oxide region being stacked and connected to the high voltage well in the vertical direction, and the field oxide region being between the channel direction junction and the drain in the channel direction.
In a preferred embodiment, the DMOS device further comprises a contact region formed in the epitaxial layer, having the first conductivity type, stacked and connected below the surface of the epitaxial layer in the vertical direction, and located in the body region as viewed in cross-section.
In order to achieve the above object, in another aspect, the present invention provides a method for manufacturing a double diffused metal oxide semiconductor device, comprising: providing a substrate, wherein the substrate has a first conductive type and has an upper surface and a lower surface which are opposite to each other in a vertical direction; forming an epitaxial layer on the substrate, wherein the epitaxial layer has an epitaxial layer surface opposite to the upper surface, and is stacked and connected on the upper surface in the vertical direction; forming a high voltage well in the epitaxial layer, wherein the high voltage well has a second conductivity type, is stacked and connected on the upper surface of the substrate in the vertical direction, and has a first PN junction with the upper surface of the substrate; forming a body region in the epitaxial layer, the body region having a first conductivity type, being stacked and connected below the surface of the epitaxial layer in the vertical direction, and having a channel-direction junction between the body region and the high-voltage well in the channel direction as viewed in a cross-sectional view; forming a gate on the epitaxial layer, the gate being stacked and connected to the surface of the epitaxial layer in the vertical direction, and the gate covering at least a portion of the channel-direction junction as viewed in cross-section; forming a source in the epitaxial layer, the source having a second conductivity type and being stacked and connected below the surface of the epitaxial layer in the vertical direction and being located in the body region as viewed in the cross-sectional view; forming a drain electrode in the epitaxial layer, the drain electrode having a second conductivity type and being stacked and connected below the surface of the epitaxial layer in the vertical direction, the source electrode and the drain electrode being located at different sides of the junction in the channel direction, and the drain electrode and the gate electrode being separated by the high voltage well as viewed in a cross-sectional view; forming a drift buried region in the epitaxial layer, wherein the drift buried region has a second conductivity type, and a part of the drift buried region is located right below the drain in the channel direction, and the length of the drift buried region is greater than or equal to that of the drain; and forming a buried region in the substrate and the epitaxial layer, the buried region having a first conductivity type, and in the vertical direction, a part of the buried region is located in the substrate, and another part of the buried region is located in the epitaxial layer, wherein, viewed from a cross-sectional view, in the channel direction, at least a part of the buried region is located right below the drift buried region, and the length of the buried region is greater than or equal to the length of the drain, wherein the length of the buried region is greater than or equal to the length of the drift buried region; wherein, viewed from a cross-sectional view, a second PN junction is formed between the drift buried region and the buried region or between the high voltage well and the buried region in the channel direction, and, viewed from a cross-sectional view, the second PN junction has a depth, which is calculated from the surface of the epitaxial layer downward along the vertical direction, shallower than the depth, which is calculated from the surface of the epitaxial layer downward along the vertical direction, of the first PN junction; the drift buried region is provided with a first boundary close to the grid and a second boundary far away from the grid in the channel direction, and the buried region is provided with a third boundary close to the grid and a fourth boundary far away from the grid in the channel direction; wherein the first boundary and the third boundary are between the drain and the channel-direction junction in the channel direction; the second boundary and the fourth boundary at least exceed a fifth boundary in the channel direction, wherein the fifth boundary is located between the drain and an insulating structure near the drain, wherein the insulating structure is used for defining an element region of the DMOS element.
In a preferred embodiment, the method for fabricating a double diffused metal oxide semiconductor device further comprises: forming a field oxide region in the operation region on the epitaxial layer, wherein the field oxide region is stacked and connected to the high voltage well in the vertical direction, and the field oxide region is between the junction in the channel direction and the drain in the channel direction.
In a preferred embodiment, the method for fabricating a double diffused metal oxide semiconductor device further comprises: a contact region of a first conductivity type is formed in the epitaxial layer, stacked and connected below a surface of the epitaxial layer in the vertical direction, and in the body region as viewed in cross-section.
In a preferred embodiment, the second conductive type impurity concentration in the drift buried region is greater than the second conductive type impurity concentration in the high voltage well, and the first conductive type impurity concentration in the buried region is greater than the first conductive type impurity concentration in the substrate.
In a preferred embodiment, the first boundary and the third boundary are located between regions directly below the field oxide region in the channel direction.
The purpose, technical content, features and effects of the present invention will be more readily understood through the following detailed description of specific embodiments.
Drawings
FIG. 1 shows a cross-sectional view of a prior art NMOS device;
FIG. 2 is a cross-sectional view of an embodiment of a DMOS device of the present invention;
FIGS. 3A-3G illustrate one embodiment of a method of fabricating a DMOS device according to the present invention;
fig. 4-6 are electrical schematic diagrams of the dmos device of the present invention corresponding to fig. 2.
Description of the symbols in the drawings
100 conventional double diffused metal oxide semiconductor element
200 double-diffused metal oxide semiconductor element
11. 21 grid electrode
13. 23f, 23r insulation structure
13a, 23a element region
14. 24 field oxide region
15. 25 high-voltage trap
16. 26 body region
16a, 26a contact area
18. 28 source electrode
19. 29 drain electrode
17. 27 base plate
21a upper surface
21b lower surface
22 epitaxial layer
22a epitaxial layer surface
26b, 28a photoresist layer
41 buried region
42 drift buried region
B1, B2 boundary
Boundary of C1 and C2
JN channel directional junction
M1, M2 boundary
N1, N2, N3 boundaries
Depth H1, H2
Region L1
Region L2
P region
PN0 PN junction
PN1 PN junction
PN2 PN junction
W29 length
W41 length
W42 length
Detailed Description
The foregoing and other aspects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment, as illustrated in the accompanying drawings. The drawings are schematic and are intended to show the process steps and the sequence of layers, and the shapes, thicknesses and widths are not to scale.
Referring to fig. 2, an embodiment of the invention is shown. This embodiment is described by taking a double Diffused Metal Oxide Semiconductor (DMOS) device as an example.
As shown in fig. 2, the dmos device 200 includes: substrate 27, epitaxial layer 22, insulating structure 23f, insulating structure 23r, high voltage well 25, body region 26, field oxide region 24, contact region 26a, buried region 41, drift buried region 42, source 28, drain 29, and gate 21. Among them, it is noted that the present invention has the following differences from the prior art: since the present invention includes the buried drift region 41 and the buried drift region 42, a shallow PN junction (PN junction) PN2 is formed between the buried drift region 42 and the buried drift region 41 or between the high voltage well 25 and the buried drift region 41. However, the shallow PN junction PN2 is not available in the prior art (the features and details of the buried region 41 and the floating buried region 42 and the shallow PN junction PN2 will be described later).
The substrate 27 has a first conductivity type, such as but not limited to P-type, and has an upper surface 21a and a lower surface 21b opposite to each other in a vertical direction (as indicated by the thick dashed arrow in the figure). The epitaxial layer 22 is formed on the substrate 27 in an epitaxial process step, has an epitaxial layer surface 22a opposite to the upper surface 21a, and is stacked and connected on the upper surface 21a in a vertical direction. The insulating structures 23f and 23r are, for example, but not limited to, local oxidation on silicon (LOCOS) structures to define the operation region 23a as the main active region of the dmos 200 during operation. And the body region 26, the source electrode 28, and the drain electrode 29, all located in the operation region 23a as seen in the cross-sectional view of fig. 2. The high voltage well 25 is formed in the epitaxial layer 22, has a second conductivity type, such as but not limited to N type, and is stacked and connected on the upper surface 21a of the substrate 27 in a vertical direction. In the present embodiment, since the substrate 27 has a first conductivity type, such as but not limited to P-type, and the high voltage well 25 has a second conductivity type, such as but not limited to N-type, a PN junction PN1 is formed between the high voltage well 25 and the upper surface 21a of the substrate 27.
The body region 26 is formed in the epitaxial layer 22, has a first conductivity type, such as, but not limited to, P-type, and is stacked and connected below the epitaxial layer surface 202a in a vertical direction, and in a channel direction (as indicated by the thick solid line arrow in the figure), the body region 26 and the high voltage well 25 have a channel direction junction JN, as indicated by the thick solid line in fig. 2. The gate 21 is formed on the epitaxial layer 22, and in the vertical direction, the gate 21 is stacked and connected on the epitaxial layer surface 22a, and as seen from the cross-sectional view of fig. 2, the gate 21 covers at least a portion of the channel junction JN. In this embodiment, for example, but not limited to, all of the channel direction junctions JN are covered. A source 28 is formed in the epitaxial layer 22, having a second conductivity type, such as but not limited to N-type, and is stacked and connected below the epitaxial layer surface 22a in a vertical direction, and the source 28 is located in the body region 26 as viewed in the cross-sectional view of fig. 2. The drain 29 is formed in the epitaxial layer 22, has a second conductivity type, such as but not limited to N-type, and is stacked and connected below the epitaxial layer surface 22a in the vertical direction, and the source 28 and the drain 29 are located on different sides of the channel junction JN in the channel direction, and the drain 29 and the gate 21 are separated by the high voltage well 25 as seen from the cross-sectional view of fig. 2.
The field oxide region 24 is formed in the operation region 23a on the epitaxial layer 22, and the field oxide region 24 is stacked and connected to the high voltage well 25 in the vertical direction, and the field oxide region 24 is between the channel direction junction JN and the drain 29 in the channel direction.
Contact regions 26a are formed in the epitaxial layer 22, have a first conductivity type, such as but not limited to P-type, and are stacked and connected in a vertical direction below the epitaxial layer surface 22a, and as seen in the cross-sectional view of fig. 2, the contact regions 26a are located in the body regions 26 for electrical contact with the body regions 26.
Drift buried region 42 is formed in epitaxial layer 22 and has a second conductivity type, such as but not limited to N-type. In one embodiment, the concentration of the second conductivity type (for example, but not limited to, N type) impurity in the drift buried region 42 is greater than the concentration of the second conductivity type (for example, but not limited to, N type) impurity in the high voltage well 25. Wherein, as seen from the cross-sectional view of fig. 2, a part of the drift buried region 42 is located right under the drain 29 in the channel direction. It should be noted that, in one embodiment, the length W42 of the drift buried region 42 is greater than the length W29 of the drain 29. However, in another embodiment, the length W42 of the drift buried region 42 may be equal to the length W29 of the drain 29.
Also, it is noted that in one embodiment, the length W41 of the buried region 41 is greater than the length W42 of the drift buried region 42. However, in another embodiment, the length W41 of the buried region 41 may be equal to the length W42 of the drift buried region 42. That is, in the present embodiment, the length W41 ≧ the length W42. In this embodiment, the drift buried region 42 is separated from the buried region 41 by the high voltage well 25; in one embodiment, the floating buried region 42 and the buried region 41 may be directly adjacent to each other, and therefore, the PN junction PN2 may be formed by the buried region 41 and the high voltage well 25 or the buried region 41 and the floating buried region 42 in different embodiments. Note that, in the present embodiment, the drift buried region 42 is separated from the drain 29 by the high voltage well 25; in one embodiment, the drift buried region 42 and the drain 29 may also be directly adjacent.
In the channel direction, the buried region 41 has a boundary B1 close to the gate 21 and a boundary B2 away from the gate 21, and the floating buried region 42 has a boundary C1 close to the gate 21 and a boundary C2 away from the gate 21. As seen from the cross-sectional view of fig. 2, the boundary B1 of the buried region 41 and the boundary C1 of the floating buried region 42 are between the drain 29 and the channel junction JN in the channel direction. The boundary B2 of the buried region 41 and the boundary C2 of the floating buried region 42 at least exceed the boundary M1 in the channel direction. As shown in fig. 2, a boundary M1 is located between drain 29 and insulating structure 23r near drain 29.
It is noted that, in one embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the floating buried region 42 are between the drain 29 and the channel junction JN in the channel direction. That is, in one embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 may be located between the drain 29 and the region L1 between the channel-direction junction JN. However, in another embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 may be located between the region L2 directly below the field oxide region 24 in the channel direction.
It should be noted that, in one embodiment, the boundary B2 of the buried region 41 and the boundary C2 of the floating buried region 42 may be located in the channel direction in a region P between the boundary M1 and the boundary M2 shown in fig. 2. It is to be noted that, in an embodiment, the native substrate may also be divided into two regions, i.e., the substrate 27 and the epitaxial layer 22, by a first-conductivity-type or second-conductivity-type doped region, which is well known in the art and will not be described herein again.
It is noted that the present invention has the following differences from the prior art: since the present invention includes the buried region 41 and the floating buried region 42, and in the present embodiment, the buried region 41 has a first conductivity type, such as but not limited to P type, the floating buried region 42 has a second conductivity type, such as but not limited to N type, and the high voltage well 25 has a second conductivity type, such as but not limited to N type, in the present embodiment, a PN junction PN2 is formed between the floating buried region 42 and the buried region 41. Alternatively, high voltage well 25 and buried region 41 have a PN junction PN 2. The PN junction PN2 has a depth H2, measured vertically downward from the epitaxial layer surface 22a, that is shallower than the PN junction PN1 (formed between the high voltage well 25 and the upper surface 21a of the substrate 27) has a depth H1, measured vertically downward from the epitaxial layer surface 22a, as viewed in cross-section. I.e., depth H2 < depth H1.
In the present invention, the drift buried region 42 has a higher concentration of N-type impurity than the high voltage well 25 and the buried region 41 has a higher concentration of P-type impurity than the substrate 27 during the non-conduction operation of the dmos 200 because the PN junction PN2 has a shallower depth H2 near the drain 29; a depletion region may be formed near PN junction PN2 near drain 29 to form a wide depletion region in combination with the lateral depletion region of the dmos 200 itself during operation to suppress high electric fields of the dmos 200 during non-conducting operation. Thus, the breakdown protection voltage of the PN junction PN2 can be increased, and the on-resistance can be reduced.
However, the prior art does not have such a shallow PN junction PN 2. Compared to the present invention having two PN junctions (i.e., PN junction PN1 and PN junction PN2, and the depth H2 of PN junction PN2 near the drain 29 is shallower than the depth H1 of PN junction PN 1), the prior art has only one PN junction PN 0. Also, in the prior art, the depth of the PN junction PN0 near the drain 19 (not shown) is the same as the depth of the PN junction PN0 near the source 18 (not shown), and there is no difference in depth.
Referring to fig. 3A to 3G, an embodiment of a method for fabricating a dmos device is shown.
First, as shown in fig. 3A, a P-type substrate 27 is provided, wherein the substrate 27 is, for example, but not limited to, a P-type silicon substrate, and may be other P-type semiconductor substrates. The P-type substrate 27 has an upper surface 21a and a lower surface 21b opposite to each other in a vertical direction (a direction indicated by a thick dotted arrow in fig. 3A). Next, as shown in fig. 3A, an epitaxial layer 22 is formed on the P-type substrate 27, and has an epitaxial layer surface 22a opposite to the upper surface 21a in the vertical direction, and the epitaxial layer 22 is stacked and connected on the upper surface 21 a. Next, for example, by an ion implantation process, impurities of the second conductivity type are implanted in the form of accelerated ions, as indicated by the thin dashed arrows in fig. 3A, to form a high voltage well 25 in the epitaxial layer 22 in a region defined by the implantation, having the second conductivity type, for example, but not limited to, N-type, and stacked and connected on the upper surface 21a of the substrate 27 in the vertical direction. The high voltage well 25 has a PN junction PN1 with the upper surface 21a of the substrate 27. It should be noted that the buried region 41 is formed in the substrate 27 and the epitaxial layer 22, and has a first conductivity type, such as but not limited to P type, and in the vertical direction, a part of the buried region 41 (in the present embodiment, for example, the lower half) is located in the substrate 27, and another part (in the present embodiment, for example, the upper half) of the buried region 41 is located in the epitaxial layer 22. In one embodiment, the first conductivity type (e.g., but not limited to, P-type) impurity concentration in buried region 41 is greater than the first conductivity type (e.g., but not limited to, P-type) impurity concentration in substrate 27. The buried region 41 is formed by, for example, but not limited to, using a photolithography process to form a photoresist layer (not shown) as a mask to define an ion implantation range, and implanting P-type impurities in the form of accelerated ions into the defined implantation range by an ion implantation process to form a buried ion implantation region in the substrate 27, and then removing the photoresist layer; then, after the epitaxial layer 22 is formed, an annealing (anneal) process step is performed to thermally diffuse the P-type impurity within the partial implantation range into the epitaxial layer 22 to form a buried region 41; this is well known to those skilled in the art and will not be described in detail herein.
Next, as shown in fig. 3B, a drift buried region 42 is formed in the epitaxial layer 22, having a second conductivity type, such as but not limited to N type. In one embodiment, the concentration of the second conductive type impurity (such as but not limited to N type) in the drift buried region 42 is greater than the concentration of the second conductive type impurity (such as but not limited to N type) in the high voltage well 25. The drift buried region 42 is formed by, for example but not limited to, using a photolithography process to form a photoresist layer (not shown) as a mask to define an ion implantation range, implanting N-type impurities in the form of accelerated ions into the defined implantation range by an ion implantation process to form a drift buried region ion implantation region in the substrate 27, and then removing the photoresist layer; then, after the epitaxial layer 22 is formed, an annealing (anneal) process step is performed to thermally diffuse the N-type impurity within the partial implantation range into the epitaxial layer 22 to form a drift buried region 42; this is well known to those skilled in the art and will not be described in detail herein. As seen from the cross-sectional view of fig. 3B, in the channel direction, a part of the buried region 41 is located right below the drift buried region 42.
It is noted that, as shown in fig. 3B, in an embodiment, the length W41 of the buried region 41 is greater than the length W42 of the floating buried region 42. However, in another embodiment, the length W41 of the buried region 41 may be equal to the length W42 of the drift buried region 42. That is, in the present embodiment, the length W41 ≧ the length W42.
It should be noted that the sequence of the above-mentioned process steps for forming the buried region 41 and the drift buried region 42 may be interchanged, and the present invention is not limited to forming the buried region 41 first and then forming the drift buried region 42. It is also possible to form the drift buried region 42 first and then form the buried region 41.
Next, as shown in fig. 3C, an insulating structure 23f and an insulating structure 23r are formed on the epitaxial layer 22 to define an operation region 23 a; at the same time or subsequently, a field oxide region 24 is formed in the operation region 23a on the epitaxial layer 22, and in the vertical direction, the field oxide region 24 is stacked and connected to the high voltage well 25. The insulating structure 23f, the insulating structure 23r and the field oxide region 24 are local oxidation of silicon (LOCOS) structures or Shallow Trench Isolation (STI) structures as shown in the figure.
Next, as shown in fig. 3D, a body region 26 of a first conductivity type, such as but not limited to P-type, is formed in the epitaxial layer 22, stacked and connected below the epitaxial layer surface 22a in the vertical direction, and a channel-direction junction JN is formed between the body region 26 and the high-voltage well 25 in the channel direction, as indicated by the thick solid line in fig. 3D. The body region 26 is masked by, for example, but not limited to, a photolithography process to form a photoresist layer 26b, and an ion implantation process to implant P-type impurities in the form of accelerated ions into the defined implantation range to form a body region ion implantation region in the substrate 27, and then the photoresist layer is removed.
Next, as shown in the cross-sectional view of fig. 3E, the gate 21 is formed on the epitaxial layer 22, and the gate 21 is stacked and connected on the epitaxial layer surface 22a in the vertical direction, and as shown in the cross-sectional view of fig. 3E, the gate 21 covers at least a portion of the channel-direction junction JN, for example, but not limited to, the entire channel-direction junction JN in the present embodiment.
Next, as shown in the cross-sectional diagram of fig. 3F, a source 28 and a drain 29 are formed in the epitaxial layer 22, having a second conductivity type, such as but not limited to N-type, and stacked and connected below the epitaxial layer surface 22a in the vertical direction, and the source 28 is located in the body region 26 as shown in the cross-sectional diagram of fig. 3F. The drain 29 is formed in the epitaxial layer 22, has a second conductivity type, such as but not limited to N-type, and is stacked and connected below the epitaxial layer surface 22a in the vertical direction, and the source 28 and the drain 29 are located on different sides of the channel junction JN in the channel direction, and the drain 29 and the gate 21 are separated by the high voltage well 25 as shown in the cross-sectional diagram of fig. 3F.
For example, in the nmos device 200, during the turn-on operation, the turn-on current flows from the N-type drain 29 through the high voltage well 25 and the body region 26 to the source 28, and the channel path is a channel formed at the junction of the P-type body region 26 and the gate 21 by applying a positive voltage to the gate 21, so that during the turn-on operation, the turn-on current flows from the drain 29 to the source 28, which is well known in the art and will not be described herein.
The source 28 and the drain 29 are formed by, for example, but not limited to, the same photolithography process and the same ion implantation process. As shown in fig. 3F, for example, but not limited to, a photoresist layer 28a and a gate electrode 21 are formed by photolithography process as a mask to define an N-type source 28 and an N-type drain 29, and an ion implantation process is performed to implant N-type impurities in the form of accelerated ions into the defined region as indicated by the dotted arrow in fig. 3F, thereby forming the N-type source 28 and the N-type drain 29 under the surface 22a of the epitaxial layer.
It is noted that, in one embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the floating buried region 42 are between the drain 29 and the channel junction JN in the channel direction. That is, in one embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 may be located between the drain 29 and the region L1 between the channel-direction junction JN. However, in another embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 may be located between the region L2 directly below the field oxide region 24 in the channel direction.
It should be noted that, in one embodiment, the boundary B2 of the buried region 41 and the boundary C2 of the floating buried region 42 may be located in the channel direction in a region P between the boundary M1 and the boundary M2 shown in fig. 2.
As shown in fig. 3F, in the present embodiment, a PN junction PN2 is formed between the floating buried region 42 and the buried region 41. Alternatively, high voltage well 25 and buried region 41 have a PN junction PN 2. The PN junction PN2 has a depth H2, measured vertically downward from the epitaxial layer surface 22a, that is shallower than the PN junction PN1 (formed between the high voltage well 25 and the upper surface 21a of the substrate 27) has a depth H1, measured vertically downward from the epitaxial layer surface 22a, as viewed in cross-section. I.e., depth H2 < depth H1.
Next, as shown in fig. 3G, a contact region 26a is formed in the epitaxial layer 22, having a first conductivity type, such as but not limited to P-type, and stacked and connected below the surface 22a of the epitaxial layer in the vertical direction. The contact region 26a is formed by, for example, but not limited to, forming a photoresist layer 26b as a mask by a photolithography process to define an ion implantation range, implanting P-type impurities in the form of accelerated ions into the defined implantation range by an ion implantation process to form a contact region ion implantation region in the epitaxial layer 22, and then removing the photoresist layer; then, an annealing (anneal) process step is performed to anneal the P-type impurity within the implantation range to form the contact region 26 a; this is well known to those skilled in the art and the details of the process steps are not described herein.
It is noted that in fig. 2 and fig. 3A to 3G, the body region 26 can be replaced by a P-well (the same concept can be applied to N-type devices, as long as the doped region is changed accordingly). The body region described in the present invention utilizes a self-aligned implant process to determine the length of the channel. That is, the channel is formed by a self-aligned implantation process of the body region. However, the P-well in the present invention determines the length of the channel by overlapping the P-well and a polysilicon layer (poly). That is, the channel is formed by shielding of the P-well.
Although the above fig. 2 and fig. 3A to 3G illustrate N-type devices, the same concept can be applied to P-type devices, and the type and concentration of the doped impurities can be changed accordingly.
In addition, please refer to FIGS. 4-6. Fig. 4-6 are electrical schematic diagrams of the dmos device of the present invention corresponding to fig. 2.
Referring to fig. 4, under the same breakdown voltage condition, the on-resistance of the dmos device 200 of the present invention is significantly reduced compared to the prior art. In contrast, the double diffused metal oxide semiconductor device 200 of the present invention has a significantly improved breakdown voltage compared to the prior art under the same on-resistance condition. Therefore, it can be seen that the double diffused metal oxide semiconductor device 200 of the present invention can increase the device breakdown voltage and reduce the on-resistance during the turn-on operation when the device is in the turn-off operation.
FIG. 5 is a schematic diagram of breakdown protection voltages according to the prior art and the present invention. Referring to fig. 5, the breakdown voltage of the dmos device 200 of the present invention is significantly improved compared to the prior art. Also, fig. 6 is a schematic diagram illustrating a turn-on operation according to the prior art and the present invention. Referring to fig. 6, the dmos device 200 of the present invention has a higher drain current at turn-on operation than the prior art. That is, the double diffused metal oxide semiconductor device 200 of the present invention can increase the device breakdown protection voltage and reduce the on-resistance.
The present invention has been described in terms of the preferred embodiments, and the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. Those skilled in the art will recognize a variety of equivalent variations that are within the spirit of the invention. For example, other process steps or structures, such as deep wells, etc., may be added without affecting the primary characteristics of the device; for example, the lithography technique is not limited to the mask technique, but may include the electron beam lithography technique. All of which can be analogized to the teachings of the present invention. In addition, the embodiments described are not limited to single applications, but may also be combined, for example, but not limited to, a combination of two embodiments. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above. Furthermore, it is not necessary for any embodiment of the invention to achieve all of the objects or advantages, and thus, it is not intended that any one of the claims be limited thereto.
Claims (10)
1. A double diffused metal oxide semiconductor DMOS cell, comprising:
the substrate is provided with a first conductive type, and an upper surface and a lower surface which are opposite to each other in a vertical direction;
an epitaxial layer formed on the substrate, having an epitaxial layer surface opposite to the upper surface, and stacked and connected on the upper surface in the vertical direction;
a high voltage well formed in the epitaxial layer, having a second conductivity type, stacked and connected on the upper surface of the substrate in the vertical direction, wherein a first PN junction is formed between the high voltage well and the upper surface of the substrate;
a body region formed in the epitaxial layer, having a first conductivity type, stacked and connected below the surface of the epitaxial layer in the vertical direction, and having a channel-direction junction with the high-voltage well in a channel direction as viewed in a cross-sectional view;
a gate formed on the epitaxial layer, the gate being stacked and connected to the surface of the epitaxial layer in the vertical direction, and the gate covering at least a portion of the channel-direction junction as viewed in cross-section;
a source electrode formed in the epitaxial layer, having a second conductivity type, stacked and connected below the surface of the epitaxial layer in the vertical direction, and located in the body region as viewed in the cross-sectional view;
a drain formed in the epitaxial layer, having a second conductivity type, stacked and connected below the surface of the epitaxial layer in the vertical direction, wherein the source and the drain are located at different sides of the junction in the channel direction, and the drain and the gate are separated by the high voltage well as viewed in a cross-sectional view;
a drift buried region formed in the epitaxial layer and having a second conductivity type, wherein, viewed from a cross-sectional view, in the channel direction, a part of the drift buried region is located right below the drain, and the length of the drift buried region is greater than or equal to the length of the drain; and
a buried region of the first conductivity type formed in the substrate and the epitaxial layer, wherein a portion of the buried region is located in the substrate and another portion of the buried region is located in the epitaxial layer in the vertical direction, wherein at least a portion of the buried region is located directly below the drift buried region in the channel direction, and the length of the buried region is greater than or equal to the length of the drain, and wherein the length of the buried region is greater than or equal to the length of the drift buried region;
wherein, viewed from a cross-sectional view, a second PN junction is formed between the drift buried region and the buried region or between the high voltage well and the buried region in the channel direction, and, viewed from a cross-sectional view, the second PN junction has a depth, which is calculated from the surface of the epitaxial layer downward along the vertical direction, shallower than the depth, which is calculated from the surface of the epitaxial layer downward along the vertical direction, of the first PN junction;
the drift buried region is provided with a first boundary close to the grid and a second boundary far away from the grid in the channel direction, and the buried region is provided with a third boundary close to the grid and a fourth boundary far away from the grid in the channel direction;
wherein the first boundary and the third boundary are between the drain and the channel-direction junction in the channel direction; the second boundary and the fourth boundary at least exceed a fifth boundary in the channel direction, wherein the fifth boundary is located between the drain and an insulating structure near the drain, wherein the insulating structure is used for defining an element region of the DMOS element.
2. The DMOS device of claim 1, wherein a concentration of the second conductive type impurity in the drift buried region is greater than a concentration of the second conductive type impurity in the high voltage well, and a concentration of the first conductive type impurity in the buried region is greater than a concentration of the first conductive type impurity in the substrate.
3. The DMOS device of claim 1, further comprising a field oxide region formed in an active region on the epitaxial layer, wherein the field oxide region is stacked and connected to the high voltage well in the vertical direction, and wherein the field oxide region is between the channel junction and the drain in the channel direction.
4. The DMOS device of claim 3, wherein the first boundary and the third boundary are between regions directly below the field oxide region in the channel direction.
5. The DMOS device of claim 1, further comprising a contact region formed in the epitaxial layer, having the first conductivity type, stacked and connected below a surface of the epitaxial layer in the vertical direction, the contact region being located in the body region as viewed in cross-section.
6. A method for fabricating a DMOS device, comprising:
providing a substrate, wherein the substrate has a first conductive type and has an upper surface and a lower surface which are opposite to each other in a vertical direction;
forming an epitaxial layer on the substrate, wherein the epitaxial layer has an epitaxial layer surface opposite to the upper surface, and is stacked and connected on the upper surface in the vertical direction;
forming a high voltage well in the epitaxial layer, wherein the high voltage well has a second conductivity type, is stacked and connected on the upper surface of the substrate in the vertical direction, and has a first PN junction with the upper surface of the substrate;
forming a body region in the epitaxial layer, the body region having a first conductivity type, being stacked and connected below the surface of the epitaxial layer in the vertical direction, and having a channel-direction junction between the body region and the high-voltage well in a channel direction as viewed in a cross-sectional view;
forming a gate on the epitaxial layer, the gate being stacked and connected to the surface of the epitaxial layer in the vertical direction, and the gate covering at least a portion of the channel-direction junction as viewed in cross-section;
forming a source in the epitaxial layer, the source having a second conductivity type and being stacked and connected below the surface of the epitaxial layer in the vertical direction and being located in the body region as viewed in the cross-sectional view;
forming a drain electrode in the epitaxial layer, the drain electrode having a second conductivity type and being stacked and connected below the surface of the epitaxial layer in the vertical direction, the source electrode and the drain electrode being located at different sides of the junction in the channel direction, and the drain electrode and the gate electrode being separated by the high voltage well as viewed in a cross-sectional view;
forming a drift buried region in the epitaxial layer, wherein the drift buried region has a second conductivity type, and a part of the drift buried region is located right below the drain in the channel direction, and the length of the drift buried region is greater than or equal to that of the drain; and
forming a buried region in the substrate and the epitaxial layer, the buried region having a first conductivity type, and in the vertical direction, a part of the buried region is located in the substrate, and another part of the buried region is located in the epitaxial layer, wherein, viewed from a cross-sectional view, in the channel direction, at least a part of the buried region is located right below the drift buried region, and the length of the buried region is greater than or equal to the length of the drain, wherein the length of the buried region is greater than or equal to the length of the drift buried region;
wherein, viewed from a cross-sectional view, a second PN junction is formed between the drift buried region and the buried region or between the high voltage well and the buried region in the channel direction, and, viewed from a cross-sectional view, the second PN junction has a depth, which is calculated from the surface of the epitaxial layer downward along the vertical direction, shallower than the depth, which is calculated from the surface of the epitaxial layer downward along the vertical direction, of the first PN junction;
the drift buried region is provided with a first boundary close to the grid and a second boundary far away from the grid in the channel direction, and the buried region is provided with a third boundary close to the grid and a fourth boundary far away from the grid in the channel direction;
wherein the first boundary and the third boundary are between the drain and the channel-direction junction in the channel direction; the second boundary and the fourth boundary at least exceed a fifth boundary in the channel direction, wherein the fifth boundary is located between the drain and an insulating structure near the drain, wherein the insulating structure is used for defining an element region of the DMOS element.
7. The DMOS device of claim 6, wherein a concentration of the second conductive type impurity in the drift buried region is greater than a concentration of the second conductive type impurity in the high voltage well, and a concentration of the first conductive type impurity in the buried region is greater than a concentration of the first conductive type impurity in the substrate.
8. The method of manufacturing a double diffused metal oxide semiconductor device as claimed in claim 6 further comprising:
forming a field oxide region in an operation region on the epitaxial layer, wherein the field oxide region is stacked and connected to the high voltage well in the vertical direction, and the field oxide region is between the junction in the channel direction and the drain in the channel direction.
9. The method of claim 8, wherein the first boundary and the third boundary are located between regions directly below the field oxide region in the channel direction.
10. The method of manufacturing a double diffused metal oxide semiconductor device as claimed in claim 6 further comprising:
a contact region of a first conductivity type is formed in the epitaxial layer, stacked and connected below a surface of the epitaxial layer in the vertical direction, and in the body region as viewed in cross-section.
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