CN104659090B - LDMOS device and manufacture method - Google Patents

LDMOS device and manufacture method Download PDF

Info

Publication number
CN104659090B
CN104659090B CN201310574832.XA CN201310574832A CN104659090B CN 104659090 B CN104659090 B CN 104659090B CN 201310574832 A CN201310574832 A CN 201310574832A CN 104659090 B CN104659090 B CN 104659090B
Authority
CN
China
Prior art keywords
type
layer
well
buried regions
shallow trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310574832.XA
Other languages
Chinese (zh)
Other versions
CN104659090A (en
Inventor
钱文生
石晶
慈朋亮
刘冬华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201310574832.XA priority Critical patent/CN104659090B/en
Publication of CN104659090A publication Critical patent/CN104659090A/en
Application granted granted Critical
Publication of CN104659090B publication Critical patent/CN104659090B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

The invention discloses a kind of LDMOS device, the N-type impurity that high dose is added in the drift region being made up of N-type epitaxy layer injects the N-type implanted layer formed, the p-type assisted depletion layer to be formed is injected in the p type impurity of the high dose formed below of the close source side of N-type implanted layer, the p type diffused layer diffuseed to form using the impurity of P+ buried regions in N-type epitaxy layer is formed with the close source side of N-type implanted layer.The invention also discloses a kind of manufacture method of LDMOS device.The present invention can reduce the conducting resistance of device, increase the conducting electric current of device, while can reduce the surface field intensity of drift region, increase the breakdown voltage of device, can be integrated in BCD techniques, need not increase additional technology cost.

Description

LDMOS device and manufacture method
Technical field
Field, more particularly to a kind of lateral double diffusion metal oxide half are manufactured the present invention relates to semiconductor integrated circuit Conductor FET(Lateral double-dif fused MOSFET, LDMOS)Device, the invention further relates to the LDMOS devices Part manufacture method.
Background technology
Double-diffusion metal-oxide-semiconductor field effect transistor(DMOS)Due to high pressure resistant, high current drive capability and pole The features such as low-power consumption, it is widely adopted at present in electric power management circuit.In LDMOS device, conducting resistance is one important Index.In BCD (Bipolar-CMOS-DMOS, bipolar-complementary metal oxide semiconductor-dual diffused metal oxide Semiconductor) in technique, although DMOS and CMOS is integrated in same chip, due to high withstand voltage and low on-resistance will Ask, DMOS is on the premise of the condition of background region and drift region is shared with the existing process conditions of CMOS, and its conducting resistance is higher, The requirement of switching tube application can not often be met.Therefore, in order to make high performance LDMOS, it is necessary to using various methods optimize The conducting resistance of device.It is generally necessary to increase by one of extra N-type injection in the drift region of device, device is set to have relatively low conducting Resistance, and the breakdown voltage of device can be reduced in this way.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of LDMOS device, can reduce the conducting resistance of device, increase Plus the conducting electric current of device, while the surface field intensity of drift region can be reduced, increase the breakdown voltage of device, it can be integrated in In BCD techniques, additional technology cost need not be increased.Therefore, present invention also offers the manufacture method of LDMOS device.
In order to solve the above technical problems, the LDMOS device that the present invention is provided includes:
N+ buried regions, is formed in P-type silicon substrate.
Above P+ buried regions, the subregion for being formed at the N+ buried regions, the bottom of the P+ buried regions and the N+ buried regions connect Touch.
N-type epitaxy layer, is formed at the surface of silicon, the bottom of the N-type epitaxy layer respectively after the N+ buried regions and The P+ buried regions contact.
P type diffused layer, is formed in the N-type epitaxy layer at the top of the P+ buried regions, the p-type of the p type diffused layer is miscellaneous Matter is diffuseed to form from the P+ buried regions into the N-type epitaxy layer.
Shallow trench oxygen layer(STI), it is formed in the N-type epitaxy layer and for the isolation of active area.
P-well, is formed in the N-type epitaxy layer, and the p-well and the p type diffused layer are at a distance.
N traps, are formed in the p type diffused layer;Isolation has a shallow trench between the N traps and the p-well Oxygen layer, it is the first shallow trench oxygen layer to make the shallow trench oxygen layer, and the N traps and first shallow trench oxygen layer are from right It is accurate.
N-type implanted layer, is formed in the N-type epitaxy layer, and the side of the side of N-type implanted layer first and the p-well connects Touch, the second side of the N-type implanted layer extends in the p type diffused layer and will first shallow trench field oxygen layer and the N Trap is surrounded.
P-type assisted depletion layer, is formed at below the N-type implanted layer, the first side of the p-type assisted depletion layer and described The contacts side surfaces of p-well, the second side of the p-type assisted depletion layer and the contacts side surfaces of the p type diffused layer, the p-well auxiliary The top of depletion layer and N-type implanted layer contact.
Grid structure, is formed from the gate dielectric layer and polysilicon gate composition on the N-type epitaxy layer surface, the grid knot P-well surface described in structure covering part simultaneously extends transverse to the N-type injection layer surface and first shallow trench oxygen layer table On face, the p-well surface covered by the grid structure is used to form raceway groove.
Source region, is formed from N+ district's groups in the p-well into, the first side of the source region and the grid structure from right It is accurate.
Drain region, is formed from N+ district's groups in the N traps into, the drain region and first shallow trench oxygen layer from right It is accurate.
P type substrate draw-out area, is formed from the P+ district's groups in the p-well into for drawing the p-well.
Expanded by the N-type implanted layer between the N traps and the p-well, p-type assisted depletion layer, the p-type Dissipate layer and the N-type epitaxy layer constitutes the drift region of LDMOS device;The doping concentration of the N-type implanted layer is higher, described The conducting resistance of LDMOS device is lower;The p-type assisted depletion layer and the p type diffused layer are used to note the N-type from bottom Enter layer to be exhausted, the doping concentration of the p-type assisted depletion layer causes the N more than the doping concentration of the p type diffused layer It is flat that type implanted layer exhausts rear surface field.
Further improve is that the implanted dopant of the ion implanting of the N-type implanted layer is phosphorus or arsenic, and Implantation Energy is 50KeV~600KeV, implantation dosage scope is 1e11cm-2~1e13cm-2
Further improve is that the implanted dopant of the ion implanting of the p-type assisted depletion layer is boron, and Implantation Energy is 800KeV~1500KeV, implantation dosage scope is 1e11cm-2~1e13cm-2
In order to solve the above technical problems, the manufacture method for the LDMOS device that the present invention is provided comprises the following steps:
Step 1: forming N+ buried regions in P-type silicon substrate using ion implantation technology.
Step 2: forming P+ buried regions above the subregion of the N+ buried regions using ion implantation technology, the P+ is buried The ion implanted regions of layer are defined by photoetching process.
Step 3: being formed with the surface of silicon formation N-type epitaxy layer of the N+ buried regions and the P+ buried regions, institute State the N+ buried regions and P+ buried regions contact after the bottom difference of N-type epitaxy layer.
Step 4: carry out pick into technique by the p type impurity of the P+ buried regions to outside the N-type at the top of the P+ buried regions Prolong and p type diffused layer is spread and formed in layer.
Step 5: forming shallow trench oxygen layer in the N-type epitaxy layer, the shallow trench oxygen layer is used to isolate Source region.
Step 6: photoetching opens p-well injection zone and carries out p-type ion implanting in the N-type epitaxy layer in the region P-well is formed, the p-well and the p type diffused layer are at a distance;Photoetching opens N traps injection zone and carries out N in the region Type ion implanting forms N traps in the p type diffused layer, and isolation has a shallow trench between the N traps and the p-well Oxygen layer, it is the first shallow trench oxygen layer to make the shallow trench oxygen layer, and the N traps and first shallow trench oxygen layer are from right It is accurate.
Step 7: photoetching opens N-type implanted layer region and carries out N-type ion implanting in the N-type epitaxy layer in the region The contacts side surfaces of middle formation N-type implanted layer, the side of N-type implanted layer first and the p-well, the second side of the N-type implanted layer Extend in the p type diffused layer and surround first shallow trench oxygen layer and the N traps.
Step 8: photoetching opens p-type assisted depletion layer region and carries out p-type ion implanting outside the N-type in the region Prolong and p-type assisted depletion layer is formed in layer, the p-type assisted depletion layer is located at below the N-type implanted layer, the p-type auxiliary consumption First side of most layer and the contacts side surfaces of the p-well, the second side of the p-type assisted depletion layer and the side of the p type diffused layer Face is contacted, the top of the p-well assisted depletion layer and N-type implanted layer contact.
Step 9: deposit gate dielectric layer and polysilicon gate successively on the N-type epitaxy layer surface, to the polysilicon gate and The gate dielectric layer carries out chemical wet etching formation grid structure, and p-well surface described in the grid structure covering part is simultaneously laterally prolonged Reach on the N-type injection layer surface and first shallow trench oxygen layer surface, the institute covered by the grid structure Stating p-well surface is used to form raceway groove.
Step 10: carrying out N+ source and drain ion implanting formation source region and drain region, the source region is located in the p-well, the source Area and the first side autoregistration of the grid structure;The drain region is located in the N traps, the drain region and first shallow trench Field oxygen layer autoregistration;P+ ion implantings formation P type substrate draw-out area is carried out, the P type substrate draw-out area is located in the p-well, For drawing the p-well.
Expanded by the N-type implanted layer between the N traps and the p-well, p-type assisted depletion layer, the p-type Dissipate layer and the N-type epitaxy layer constitutes the drift region of LDMOS device;The doping concentration of the N-type implanted layer is higher, described The conducting resistance of LDMOS device is lower;The p-type assisted depletion layer and the p type diffused layer are used to note the N-type from bottom Enter layer to be exhausted, the doping concentration of the p-type assisted depletion layer causes the N more than the doping concentration of the p type diffused layer It is flat that type implanted layer exhausts rear surface field.
Further improve is that the implanted dopant of the ion implanting of N-type implanted layer described in step 7 is phosphorus or arsenic, injection Energy is 50KeV~600KeV, and implantation dosage scope is 1e11cm-2~1e13cm-2
Further improve is that the implanted dopant of the ion implanting of the layer of p-type assisted depletion described in step 8 is boron, injection Energy is 800KeV~1500KeV, and implantation dosage scope is 1e11cm-2~1e13cm-2
Further improve is that the resistivity of the P-type silicon substrate is 0.007 ohmcm~0.013 ohm li Rice.
Further improve is that the manufacturing process of the LDMOS device is integrated in BCD techniques, the LDMOS device The p-well in manufacturing process is identical with the p-well technique of the cmos device in the BCD techniques and is synchronously formed, the LDMOS The N traps in the manufacturing process of device are identical with the N-well process of the cmos device in the BCD techniques and synchronously formed, institute State the N+ source and drain ion implanting in the manufacturing process of LDMOS device and the N+ source and drain of the cmos device in the BCD techniques Ion implanting is identical and is synchronously formed, the P+ sources of the P type substrate draw-out area in the manufacturing process of the LDMOS device Leakage ion implanting is identical with the P+ source and drain ion implantings of the cmos device in the BCD techniques and is synchronously formed;The LDMOS devices The shape of the grid structure of the formation process of the grid structure in the manufacturing process of part and the cmos device in the BCD techniques It is identical and synchronous formed into technique.
The present invention has the advantages that:
1st, LDMOS device of the present invention is injected by the doping of adjusting device, increases the N-type impurity note of high dose in drift region The conducting resistance of device can effectively be reduced by entering to be formed N-type implanted layer.
2nd, the present invention injects shape by increasing the p type impurity of high dose in the lower section of the close source side of N-type implanted layer The p type diffused layer formed below in the close drain region for being diffused in N-type implanted layer into p-type assisted depletion layer and using p type buried layer, It can realize and N-type implanted layer is exhausted from bottom using p-type assisted depletion layer and p type diffused layer, so as to increase device Breakdown voltage;The present invention can also cause the doping concentration that the doping concentration of p-type assisted depletion layer is more than the p type diffused layer N-type implanted layer exhausts that rear surface field is flat, so as to the further breakdown voltage for improving device.
3rd, the present invention can be integrated in BCD techniques, it is not necessary to increase additional technology cost.Such as the P+ buried regions works of the present invention Common process in skill originally BCD techniques, it is only necessary to modified to the reticle that P+ buried regions injects, it is not necessary to increase Extra reticle;All process conditions such as source and drain injection technology such as the present invention can be with the CMOS works in BCD technique platforms Skill is shared.
4th, because device of the present invention has larger conducting resistance while have higher breakdown voltage, all devices of the present invention Part can meet the use characteristic of switching device and analog device simultaneously.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description:
Fig. 1 is the structural representation of LDMOS device of the embodiment of the present invention;
Fig. 2 is the ionization by collision distribution map of existing LDMOS device;
Fig. 3 is the ionization by collision distribution map of LDMOS device of the embodiment of the present invention;
Fig. 4 is the electric-field intensity of LDMOS device of the embodiment of the present invention and existing LDMOS device below shallow trench oxygen layer Curve comparison figure;
Device architecture schematic diagram in each step of the manufacture method of Fig. 5 A- Fig. 5 I LDMOS devices of the embodiment of the present invention.
Embodiment
Fig. 1 is the structural representation of LDMOS device of the embodiment of the present invention;LDMOS device of the embodiment of the present invention is N-type LDMOS device, including:
N+ buried regions 102, is formed in P-type silicon substrate 101.
P+ buried regions 103, is formed above the subregion of the N+ buried regions 102, the bottom of the P+ buried regions 103 and described N+ buried regions 102 is contacted.
N-type epitaxy layer 104, is formed at described after the surface of silicon substrate 101, the bottom difference of the N-type epitaxy layer 104 N+ buried regions 102 and the P+ buried regions 103 are contacted.
In p type diffused layer 105, the N-type epitaxy layer 104 for being formed at the top of P+ buried regions 103, the p-type diffusion The p type impurity of layer 105 is diffuseed to form from the P+ buried regions 103 into the N-type epitaxy layer 104.
Shallow trench oxygen layer 106, is formed in the N-type epitaxy layer 104 and for active area 114a isolation.
P-well 108, is formed in the N-type epitaxy layer 104, and the p-well 108 and the p type diffused layer 105 are separated by one section Distance.
N traps 107, are formed in the p type diffused layer 105;Isolation has one between the N traps 107 and the p-well 108 The individual shallow trench oxygen layer 106, it is the first shallow trench oxygen layer 106, the N traps 107 and institute to make the shallow trench oxygen layer 106 State the first shallow trench autoregistration of oxygen layer 106.
N-type implanted layer 109, is formed in the N-type epitaxy layer 104, the side of N-type implanted layer 109 first and the p-well 108 contacts side surfaces, the second side of the N-type implanted layer 109 extends in the p type diffused layer 105 and shallow by described first Groove oxygen layer 106 and the N traps 107 are surrounded.Preferably, the implanted dopant of the ion implanting of the N-type implanted layer 109 is phosphorus Or arsenic, Implantation Energy is 50KeV~600KeV, and implantation dosage scope is 1e11cm-2~1e13cm-2
P-type assisted depletion layer 110, is formed at the lower section of N-type implanted layer 109, and the of the p-type assisted depletion layer 110 Side and the contacts side surfaces of the p-well 108, the second side and the side of the p type diffused layer 105 of the p-type assisted depletion layer 110 Face is contacted, and the top of the assisted depletion of p-well 108 layer and the N-type implanted layer 109 are contacted.Preferably, the p-type auxiliary consumption The implanted dopant of the ion implanting of layer 110 is boron to the greatest extent, and Implantation Energy is 800KeV~1500KeV, and implantation dosage scope is 1e11cm-2~1e13cm-2
Grid structure, the gate dielectric layer 111 and polysilicon gate 112 for being formed from the surface of N-type epitaxy layer 104 is constituted; Preferably, the gate dielectric layer 111 is gate oxide, and the side of the polysilicon gate 112 is formed with side wall 113.The grid The surface of p-well 108 described in structure covering part simultaneously extends transverse to the surface of N-type implanted layer 109 and first shallow trench On the surface of oxygen layer 106 of field, the surface of the p-well 108 covered by the grid structure is used to form raceway groove.
Source region 114a, is formed from the N+ district's groups in the p-well 108 into the source region 114a's and the grid structure First side autoregistration.
Drain region 114b, is formed from N+ district's groups in the N traps 107 into the drain region 114b and first shallow trench The field autoregistration of oxygen layer 106.
P type substrate draw-out area 115, is formed from the P+ district's groups in the p-well 108 into for drawing the p-well 108.
By the N-type implanted layer 109 between the N traps 107 and the p-well 108, p-type assisted depletion layer 110th, the p type diffused layer 105 and the N-type epitaxy layer 104 constitute the drift region of LDMOS device;The N-type implanted layer 109 Doping concentration it is higher, the conducting resistance of the LDMOS device is lower;The p-type assisted depletion layer 110 and p-type diffusion Layer 105 is used to exhaust the N-type implanted layer 109 from bottom, and the doping concentration of the p-type assisted depletion layer 110 is more than The doping concentration of the diffusion layer of p-well 108 causes the N-type implanted layer 109 exhausts rear surface field flat.
The source region 114a, the drain region 114b, the P type substrate draw-out area 115 and the polysilicon gate 112 lead to respectively Cross contact hole 116 and top metal lead 117 connects and realizes source electrode respectively, drain electrode, P type substrate extraction electrode and grid draw Go out.
LDMOS device of the embodiment of the present invention not only is injected to form N-type note by increasing the N-type impurity of high dose in drift region Entering layer effectively reduces the conducting resistance of device;Also aided in by being formed close to the p-type of source respectively in the bottom of N-type implanted layer The p type diffused layer of depletion layer and close drain terminal optimizes come the surface electric field distribution to drift region, so as to improve device Breakdown voltage, so the embodiment of the present invention can avoid leading during the N-type impurity injection for increasing drift region merely in the prior art The problem of breakdown voltage of cause is reduced.In order to intuitively illustrate the above-mentioned advantage of the embodiment of the present invention, Fig. 2-Fig. 4 refer to:
As shown in Fig. 2 being the ionization by collision distribution map of existing LDMOS device;Existing LDMOS device passes through adjusting device Doping injection, although can effectively reduce the conducting resistance of device in the N-type impurity injection that N-type drift region increases high dose, Be due to the shallow-trench isolation i.e. influence of shallow trench oxygen layer 106 (STI) pattern itself, with using local oxidation (LOCOS) every From device compare, the N-type injection of increase drift region is more easily caused the decline of device electric breakdown strength, STI106 bottoms sharp corner electricity Field can drastically raise with the raising of N-type drift region doped level and reach critical electric field so that more than 50V breakdown voltage Region shown in the dotted line frame 1 in 30V or so, Fig. 2 is reduced to for STI106 bottoms sharp corner, region described in dotted line frame 2 is dotted line The enlarged drawing in region shown in frame 1, it is known that in whole drift region, the electric field of dotted line frame 1 is concentrated the most.
As shown in figure 3, being the ionization by collision distribution map of LDMOS device of the embodiment of the present invention;The embodiment of the present invention utilizes BCD Original process conditions in technique platform, use the P of higher dosage below the N-type implanted layer 109 close to the drift region of source Type injects to form p-type assisted depletion layer 110, in the note for the top of the N+ buried regions 102 increase P+ buried regions 103 for being used to isolate close to drain terminal Enter, P+ buried regions 103 was integrated in BCD technique platforms originally, it is only necessary to which reticle is modified, it is not necessary to increased additionally Reticle.Impurity is by picking into N-type drift region assisted depletion area formed below i.e. p type diffused layer 105 in P+ buried regions 103; N-type implanted layer 109 can be exhausted from bottom to increase by p-type assisted depletion layer 110 and p type diffused layer 105 The breakdown voltage of device, the setting of p-type assisted depletion layer 110 and the doping concentration of p type diffused layer 105 also helps change surface electricity Field distribution;As described in Figure 3, electric field is not centered at the corner positions of dotted line frame 1 as shown in Figure 2, and electric field is than more uniform It is distributed in the bottom of whole shallow trench oxygen 106.
As shown in figure 4, being LDMOS device of the embodiment of the present invention and existing LDMOS device below shallow trench oxygen layer Electric field strength profile comparison diagram.Wherein curve 3 corresponds to electric-field strength of the existing LDMOS device below shallow trench oxygen layer and write music Line, it is known that its electric-field intensity has a peak value in STI106 bottoms sharp corner, and the electric-field intensity at other regions reduces, when Device will puncture when electric-field intensity at the peak value reaches critical value.Wherein curve 4 corresponds to LDMOS devices of the embodiment of the present invention Electric field strength profile of the part below shallow trench oxygen layer, it is known that its electric-field intensity, than more uniform, does not go out in STI106 bottoms Existing obvious high and low region.Comparison curves 4 and 3 understands that, when device breakdown, curve 4 encloses area and is obviously greater than curve 3 Enclosed area, namely the breakdown voltage of the embodiment of the present invention are greater than the breakdown voltage of existing device.Existing device passes through in drift After moving area's increase N-type implanted layer breakdown voltage can be made to be reduced to 30V or so from more than 50V breakdown voltage, and the present invention is implemented Example device can also really make breakdown voltage maintain more than 50V after increase N-type implanted layer, at the same can make the conducting resistance of device from 49 are reduced to 35.
As shown in Fig. 5 A to Fig. 5 I, be LDMOS device of the embodiment of the present invention manufacture method each step in device junction Structure schematic diagram.The manufacture method of LDMOS device of the embodiment of the present invention comprises the following steps:
Step 1: as shown in Figure 5A, N+ buried regions 102 is formed in P-type silicon substrate 101 using ion implantation technology.The P The resistivity of type silicon substrate 101 is the ohmcm of 0.007 ohmcm~0.013.
Step 2: as shown in Figure 5 B, P+ is formed above the subregion of the N+ buried regions 102 using ion implantation technology Buried regions 103, the ion implanted regions of the P+ buried regions 103 are defined by photoetching process.
Step 3: as shown in Figure 5 C, being formed with the silicon substrate 101 of the N+ buried regions 102 and the P+ buried regions 103 Surface forms the N+ buried regions 102 and the P+ buried regions 103 after N-type epitaxy layer 104, the bottom difference of the N-type epitaxy layer 104 Contact.
Step 4: as shown in Figure 5 C, progress is picked the p type impurity of the P+ buried regions 103 into technique to the P+ buried regions Spread in the N-type epitaxy layer 104 at 103 tops and form p type diffused layer 105.
Step 5: as shown in Figure 5 D, forming shallow trench oxygen layer 106, the shallow trench in the N-type epitaxy layer 104 Field oxygen layer 106 is used to isolate active area 114a.Need to utilize active area photoetching when forming shallow trench oxygen layer 106, in the N Shallow trench area is opened on type epitaxial layer 104, the silicon formation shallow trench of the shallow trench area is etched, is filled in the shallow trench Oxide, forms the shallow trench oxygen layer 106. after the oxide of filling is performed etching and ground
Step 6: as shown in fig. 5e, photoetching opens the injection zone of p-well 108 and carries out p-type ion implanting in institute in the region Formation p-well 108 in N-type epitaxy layer 104 is stated, the p-well 108 and the p type diffused layer 105 are at a distance;N is opened in photoetching The injection zone of trap 107 simultaneously forms N traps 107 in region progress N-type ion implanting in the p type diffused layer 105, in the N Isolation has a shallow trench oxygen layer 106 between trap 107 and the p-well 108, and it is first to make the shallow trench oxygen layer 106 Shallow trench oxygen layer 106, the N traps 107 and the first shallow trench autoregistration of oxygen layer 106.
Step 7: as illustrated in figure 5f, photoetching, which opens the region of N-type implanted layer 109 and carries out N-type ion implanting in the region, to exist The side of formation N-type implanted layer 109 in the N-type epitaxy layer 104, the side of N-type implanted layer 109 first and the p-well 108 connects Touch, the second side of the N-type implanted layer 109 extends in the p type diffused layer 105 and will first shallow trench field oxygen layer 106 and the N traps 107 surround.Preferably, the implanted dopant of the ion implanting of the N-type implanted layer 109 is phosphorus or arsenic, injection Energy is 50KeV~600KeV, and implantation dosage scope is 1e11cm-2~1e13cm-2
Step 8: as illustrated in figure 5f, photoetching opens p-type assisted depletion 110 region of layer and carries out p-type ion note in the region Enter to be formed p-type assisted depletion layer 110 in the N-type epitaxy layer 104, the p-type assisted depletion layer 110 is located at the N-type and noted Enter the lower section of layer 109, the first side of the p-type assisted depletion layer 110 and the contacts side surfaces of the p-well 108, the p-type auxiliary consumption Second side of most layer 110 and the contacts side surfaces of the p type diffused layer 105, the top of the assisted depletion of p-well 108 layer and the N Type implanted layer 109 is contacted.Preferably, the implanted dopant of the ion implanting of the p-type assisted depletion layer 110 is boron, Implantation Energy For 800KeV~1500KeV, implantation dosage scope is 1e11cm-2~1e13cm-2
Step 9: as depicted in fig. 5g, gate dielectric layer 111 and polysilicon gate are deposited successively on the surface of N-type epitaxy layer 104 112, chemical wet etching formation grid structure is carried out to the polysilicon gate 112 and the gate dielectric layer 111, the grid structure covers The surface of p-well 108 described in cover simultaneously extends transverse to the surface of N-type implanted layer 109 and first shallow trench oxygen layer On 106 surfaces, the surface of the p-well 108 covered by the grid structure is used to form raceway groove.
As illustrated in fig. 5h, in the polysilicon after the silica of one layer 2500 angstroms~3500 angstroms of deposit, dry etching The side of grid 112 forms side wall 113.
Step 10: as shown in fig. 5i, carrying out N+ source and drain ion implanting formation source region 114a and drain region 114b, the source region 114a is located in the p-well 108, the first side autoregistration of the source region 114a and the grid structure;Described drain region 114b In the N traps 107, the drain region 114b and the first shallow trench autoregistration of oxygen layer 106;P+ ion implantings are carried out to be formed P type substrate draw-out area 115, the P type substrate draw-out area 115 is located in the p-well 108, for drawing the p-well 108.
By the N-type implanted layer 109 between the N traps 107 and the p-well 108, p-type assisted depletion layer 110th, the p type diffused layer 105 and the N-type epitaxy layer 104 constitute the drift region of LDMOS device;The N-type implanted layer 109 Doping concentration it is higher, the conducting resistance of the LDMOS device is lower;The p-type assisted depletion layer 110 and p-type diffusion Layer 105 is used to exhaust the N-type implanted layer 109 from bottom, and the doping concentration of the p-type assisted depletion layer 110 is more than The doping concentration of the diffusion layer of p-well 108 causes the N-type implanted layer 109 exhausts rear surface field flat.
As shown in figure 1, last also include step:Interlayer film is formed, is connected by contact hole technique formation contact hole 116; Form top metal lead 117, the source region 114a, the drain region 114b, the P type substrate draw-out area 115 and the polycrystalline Si-gate 112 is connected by contact hole 116 and top metal lead 117 and realizes source electrode respectively respectively, drain electrode, P type substrate draw The extraction of electrode and grid.
The manufacturing process of LDMOS device described in the embodiment of the present invention can be integrated in BCD techniques, the LDMOS device Manufacturing process in the p-well 108 it is identical with the technique of p-well 108 of the cmos device in the BCD techniques and it is synchronous formed, The technique phase of N traps 107 of the N traps 107 in the manufacturing process of the LDMOS device and the cmos device in the BCD techniques In the N+ source and drain ion implanting and the BCD techniques in same and synchronous formation, the manufacturing process of the LDMOS device The N+ source and drain ion implantings of cmos device are identical and synchronously formed, the P type substrate in the manufacturing process of the LDMOS device The P+ source and drain ion implanting of draw-out area 115 it is identical with the P+ source and drain ion implantings of the cmos device in the BCD techniques and It is synchronous to be formed;In the formation process of the grid structure in the manufacturing process of the LDMOS device and the BCD techniques The formation process of the grid structure of cmos device is identical and is synchronously formed.
The present invention is described in detail above by specific embodiment, but these not constitute the limit to the present invention System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should It is considered as protection scope of the present invention.

Claims (8)

1. a kind of LDMOS device, it is characterised in that including:
N+ buried regions, is formed in P-type silicon substrate;
Above P+ buried regions, the subregion for being formed at the N+ buried regions, the bottom of the P+ buried regions and N+ buried regions contact;
N-type epitaxy layer, is formed at the N+ buried regions and the P after the surface of silicon, the bottom difference of the N-type epitaxy layer + buried regions is contacted;
P type diffused layer, is formed in the N-type epitaxy layer at the top of the P+ buried regions, the p type impurity of the p type diffused layer by The P+ buried regions is diffuseed to form into the N-type epitaxy layer;
Shallow trench oxygen layer, is formed in the N-type epitaxy layer and for the isolation of active area;
P-well, is formed in the N-type epitaxy layer, and the p-well and the p type diffused layer are at a distance;
N traps, are formed in the p type diffused layer;Isolation has the shallow trench oxygen between the N traps and the p-well Layer, it is the first shallow trench oxygen layer, the N traps and first shallow trench oxygen layer autoregistration to make the shallow trench oxygen layer;
N-type implanted layer, is formed in the N-type epitaxy layer, the contacts side surfaces of the side of N-type implanted layer first and the p-well, institute The second side for stating N-type implanted layer is extended in the p type diffused layer and by first shallow trench oxygen layer and the N traps bag Enclose;
P-type assisted depletion layer, is formed at below the N-type implanted layer, the first side of the p-type assisted depletion layer and the p-well Contacts side surfaces, the second side of p-type assisted depletion layer and the contacts side surfaces of the p type diffused layer, the p-well assisted depletion The top of layer and N-type implanted layer contact;
Grid structure, is formed from the gate dielectric layer and polysilicon gate composition on the N-type epitaxy layer surface, and the grid structure covers P-well surface described in cover is simultaneously extended transverse on the N-type injection layer surface and first shallow trench oxygen layer surface, The p-well surface covered by the grid structure is used to form raceway groove;
Source region, is formed from N+ district's groups in the p-well into the first side autoregistration of the source region and the grid structure;
Drain region, is formed from N+ district's groups in the N traps into the drain region and first shallow trench oxygen layer autoregistration;
P type substrate draw-out area, is formed from the P+ district's groups in the p-well into for drawing the p-well;
By the N-type implanted layer between the N traps and the p-well, p-type assisted depletion layer, the p type diffused layer The drift region of LDMOS device is constituted with the N-type epitaxy layer;The doping concentration of the N-type implanted layer is higher, the LDMOS devices The conducting resistance of part is lower;The p-type assisted depletion layer and the p type diffused layer are used to enter the N-type implanted layer from bottom Row exhausts, and the doping concentration of the p-type assisted depletion layer causes the N-type to inject more than the doping concentration of the p type diffused layer It is flat that layer exhausts rear surface field.
2. LDMOS device as claimed in claim 1, it is characterised in that:The implanted dopant of the ion implanting of the N-type implanted layer For phosphorus or arsenic, Implantation Energy is 50KeV~600KeV, and implantation dosage scope is 1e11cm-2~1e13cm-2
3. LDMOS device as claimed in claim 1, it is characterised in that:The injection of the ion implanting of the p-type assisted depletion layer Impurity is boron, and Implantation Energy is 800KeV~1500KeV, and implantation dosage scope is 1e11cm-2~1e13cm-2
4. a kind of manufacture method of LDMOS device, it is characterised in that comprise the following steps:
Step 1: forming N+ buried regions in P-type silicon substrate using ion implantation technology;
Step 2: P+ buried regions is formed above the subregion of the N+ buried regions using ion implantation technology, the P+ buried regions Ion implanted regions are defined by photoetching process;
Step 3: being formed with the surface of silicon formation N-type epitaxy layer of the N+ buried regions and the P+ buried regions, the N The N+ buried regions and P+ buried regions contact after the bottom difference of type epitaxial layer;
Step 4: pick the p type impurity of the P+ buried regions into technique to the N-type epitaxy layer at the top of the P+ buried regions It is middle to spread and form p type diffused layer;
Step 5: forming shallow trench oxygen layer in the N-type epitaxy layer, the shallow trench oxygen layer is active for isolating Area;
Step 6: photoetching opens p-well injection zone and carries out p-type ion implanting in the region forms P in the N-type epitaxy layer Trap, the p-well and the p type diffused layer are at a distance;Photoetching open N traps injection zone and the region carry out N-type from Son is infused in formation N traps in the p type diffused layer, and isolation has the shallow trench oxygen between the N traps and the p-well Layer, it is the first shallow trench oxygen layer, the N traps and first shallow trench oxygen layer autoregistration to make the shallow trench oxygen layer;
Step 7: photoetching opens N-type implanted layer region and carries out N-type ion implanting shape in the N-type epitaxy layer in the region Into N-type implanted layer, the contacts side surfaces of the side of N-type implanted layer first and the p-well, the second side extension of the N-type implanted layer Surrounded into the p type diffused layer and by first shallow trench oxygen layer and the N traps;
Step 8: photoetching opens p-type assisted depletion layer region and carries out p-type ion implanting in the N-type epitaxy layer in the region Middle formation p-type assisted depletion layer, the p-type assisted depletion layer is located at below the N-type implanted layer, the p-type assisted depletion layer The first side and the p-well contacts side surfaces, the second side of p-type assisted depletion layer and the side of the p type diffused layer connect Touch, the top of the p-well assisted depletion layer and N-type implanted layer contact;
Step 9: deposit gate dielectric layer and polysilicon gate successively on the N-type epitaxy layer surface, to the polysilicon gate and described Gate dielectric layer carries out chemical wet etching formation grid structure, and p-well surface described in the grid structure covering part simultaneously extends transverse to In the N-type injection layer surface and first shallow trench oxygen layer surface, the p-well covered by the grid structure Surface is used to form raceway groove;
Step 10: carrying out N+ source and drain ion implanting formation source region and drain region, the source region is located in the p-well, the source region and First side autoregistration of the grid structure;The drain region is located in the N traps, the drain region and first shallow trench oxygen Layer autoregistration;P+ ion implantings formation P type substrate draw-out area is carried out, the P type substrate draw-out area is located in the p-well, is used for Draw the p-well;
By the N-type implanted layer between the N traps and the p-well, p-type assisted depletion layer, the p type diffused layer The drift region of LDMOS device is constituted with the N-type epitaxy layer;The doping concentration of the N-type implanted layer is higher, the LDMOS devices The conducting resistance of part is lower;The p-type assisted depletion layer and the p type diffused layer are used to enter the N-type implanted layer from bottom Row exhausts, and the doping concentration of the p-type assisted depletion layer causes the N-type to inject more than the doping concentration of the p type diffused layer It is flat that layer exhausts rear surface field.
5. method as claimed in claim 4, it is characterised in that:The injection of the ion implanting of N-type implanted layer described in step 7 Impurity is phosphorus or arsenic, and Implantation Energy is 50KeV~600KeV, and implantation dosage scope is 1e11cm-2~1e13cm-2
6. method as claimed in claim 4, it is characterised in that:The ion implanting of the layer of p-type assisted depletion described in step 8 Implanted dopant is boron, and Implantation Energy is 800KeV~1500KeV, and implantation dosage scope is 1e11cm-2~1e13cm-2
7. method as claimed in claim 4, it is characterised in that:The resistivity of the P-type silicon substrate is 0.007 ohmcm ~0.013 ohmcm.
8. method as claimed in claim 4, it is characterised in that:The manufacturing process of the LDMOS device is integrated in BCD techniques In, the p-well in the manufacturing process of the LDMOS device it is identical with the p-well technique of the cmos device in the BCD techniques and It is synchronous to be formed, the N-well process of the N traps in the manufacturing process of the LDMOS device and the cmos device in the BCD techniques In the N+ source and drain ion implanting and the BCD techniques in identical and synchronous formation, the manufacturing process of the LDMOS device The N+ source and drain ion implantings of cmos device are identical and synchronously formed, the P type substrate in the manufacturing process of the LDMOS device The P+ ion implantings of draw-out area are identical with the P+ source and drain ion implantings of the cmos device in the BCD techniques and synchronously formed;Institute State the formation process and the grid of the cmos device in the BCD techniques of the grid structure in the manufacturing process of LDMOS device The formation process of pole structure is identical and is synchronously formed.
CN201310574832.XA 2013-11-18 2013-11-18 LDMOS device and manufacture method Active CN104659090B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310574832.XA CN104659090B (en) 2013-11-18 2013-11-18 LDMOS device and manufacture method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310574832.XA CN104659090B (en) 2013-11-18 2013-11-18 LDMOS device and manufacture method

Publications (2)

Publication Number Publication Date
CN104659090A CN104659090A (en) 2015-05-27
CN104659090B true CN104659090B (en) 2017-08-08

Family

ID=53250008

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310574832.XA Active CN104659090B (en) 2013-11-18 2013-11-18 LDMOS device and manufacture method

Country Status (1)

Country Link
CN (1) CN104659090B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298935B (en) * 2016-08-16 2019-08-13 上海华虹宏力半导体制造有限公司 LDMOS device and its manufacturing method
TWI624065B (en) * 2016-09-22 2018-05-11 立錡科技股份有限公司 Double diffused metal oxide semiconductor device and manufacturing method thereof
CN106449412A (en) * 2016-09-30 2017-02-22 上海华虹宏力半导体制造有限公司 Technological method for switch N type LDMOS device
CN107887437A (en) * 2016-09-30 2018-04-06 中芯国际集成电路制造(上海)有限公司 Ldmos transistor and forming method thereof, semiconductor devices and forming method thereof
US11195909B2 (en) * 2018-02-20 2021-12-07 Maxim Integrated Products, Inc. LDMOS transistors with breakdown voltage clamps
CN116137292A (en) * 2021-11-17 2023-05-19 无锡华润上华科技有限公司 LDMOS device and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130168A (en) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 Isolated LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
CN103022125A (en) * 2011-09-22 2013-04-03 上海华虹Nec电子有限公司 NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101175228B1 (en) * 2009-12-04 2012-08-21 매그나칩 반도체 유한회사 Semiconductor device
US8421150B2 (en) * 2011-08-03 2013-04-16 Richtek Technology Corporation R.O.C. High voltage device and manufacturing method thereof
US8541862B2 (en) * 2011-11-30 2013-09-24 Freescale Semiconductor, Inc. Semiconductor device with self-biased isolation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130168A (en) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 Isolated LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
CN103022125A (en) * 2011-09-22 2013-04-03 上海华虹Nec电子有限公司 NLDMOS (N type Lateral Double Diffusion Metal-Oxide-Semiconductor) device in BCD (Bipolar, CMOS and DMOS) process and manufacturing method

Also Published As

Publication number Publication date
CN104659090A (en) 2015-05-27

Similar Documents

Publication Publication Date Title
CN104659090B (en) LDMOS device and manufacture method
CN104992977B (en) NLDMOS device and its manufacturing method
CN102386211B (en) LDMOS device and fabrication method thereof
CN103178093B (en) The structure of high-voltage junction field-effect transistor and preparation method
CN105428415B (en) NLDMOS device and its manufacturing method
CN102376762B (en) Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
CN108242467B (en) LDMOS device and manufacturing method thereof
CN105789311A (en) Transverse diffusion field effect transistor and manufacturing method therefor
CN105914231B (en) Charge storage type IGBT and its manufacturing method
CN114038914A (en) Double-withstand-voltage semiconductor power device and preparation method thereof
CN103633089B (en) Polysilicon resistance and manufacture method thereof
CN104659091A (en) Ldmos device and manufacturing method thereof
CN110504260B (en) Transverse groove type IGBT with self-bias PMOS and preparation method thereof
CN105140289A (en) N-type LDMOS device and technical method thereof
CN105514166A (en) NLDMOS device and manufacture method thereof
CN105206675A (en) Nldmos device and manufacturing method thereof
CN102386227B (en) Both-way surface field subdued drain electrode isolation double diffused drain metal-oxide -semiconductor field effect transistor (DDDMOS) transistor and method
CN104617139B (en) LDMOS device and manufacture method
CN115274859B (en) LDMOS transistor and manufacturing method thereof
CN105679831A (en) Lateral diffusion field effect transistor and manufacturing method thereof
CN104064596B (en) NLDMOS device and manufacture method thereof
CN104201203B (en) High withstand voltage LDMOS device and manufacture method thereof
CN110459596B (en) Transverse insulated gate bipolar transistor and preparation method thereof
CN113838914A (en) RET IGBT device structure with separation gate structure and manufacturing method
CN103681791B (en) NLDMOS device and manufacture method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant