TW201814904A - Double diffused metal oxide semiconductor device and manufacturing method thereof - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 51
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 210000000746 body region Anatomy 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims description 34
- 239000012535 impurity Substances 0.000 claims description 31
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000007943 implant Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 238000002513 implantation Methods 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
Description
本發明有關於一種雙擴散金屬氧化物半導體元件及其製造方法，特別是指一種在雙擴散金屬氧化物半導體(Double Diffused Metal Oxide Semiconductor, DMOS)元件於不導通操作時，提高其元件崩潰防護電壓，且於導通操作時，亦能夠降低其導通電阻的雙擴散金屬氧化物半導體元件及其製造方法。The invention relates to a double-diffused metal oxide semiconductor device and a method for manufacturing the same, and particularly to a method for increasing a device breakdown protection voltage when a double-diffused metal oxide semiconductor (DMOS) device is in non-conducting operation. In addition, during a conducting operation, a double-diffused metal oxide semiconductor device capable of reducing its on-resistance and a manufacturing method thereof.
請參考第1圖，其顯示先前技術之N型雙擴散金屬氧化物半導體元件之剖視圖。如第1圖所示，先前技術之N型雙擴散金屬氧化物半導體元件100包含：基板17、絕緣結構13、高壓井區15、本體區16、源極18、汲極19、與閘極11。其中，基板17的導電型為P型，高壓井區15的導電型為N型，形成於基板17上，絕緣結構13為區域氧化(local oxidation of silicon, LOCOS)結構，以定義操作區13a，作為先前技術之N型雙擴散金屬氧化物半導體元件100操作時主要的作用區。操作區13a的範圍由第1圖中，由兩個指向相反方向的箭號所示意。Please refer to FIG. 1, which shows a cross-sectional view of a conventional N-type double-diffused metal oxide semiconductor device. As shown in FIG. 1, the N-type double-diffused metal oxide semiconductor device 100 of the prior art includes a substrate 17, an insulation structure 13, a high-voltage well region 15, a body region 16, a source electrode 18, a drain electrode 19, and a gate electrode 11. . Among them, the conductivity type of the substrate 17 is P-type, the conductivity type of the high-voltage well region 15 is N-type, is formed on the substrate 17, and the insulating structure 13 is a local oxidation of silicon (LOCOS) structure to define the operation area 13a, The N-type double-diffused metal oxide semiconductor device 100 of the prior art operates as a main active region. The range of the operating area 13a is shown in Fig. 1 by two arrows pointing in opposite directions.
這種先前技術之N型雙擴散金屬氧化物半導體元件100有一缺點:在此先前技術之N型雙擴散金屬氧化物半導體元件100中，在導通與不導通的操作條件下，其基板17係電連接至接地電位(圖未示)，而高壓井區15的電位為相對高的電位，會造成在導通操作中，高壓井區15在操作區13a中完全空乏，因此導通電阻相對較高，限制了操作的速度，與元件的性能。The N-type double-diffused metal oxide semiconductor device 100 of the prior art has a disadvantage: In the N-type double-diffused metal oxide semiconductor device 100 of the prior art, the substrate 17 is electrically conductive under operating conditions of conduction and non-conduction. Connected to the ground potential (not shown), and the potential of the high-voltage well region 15 is relatively high, which will cause the high-voltage well region 15 to be completely empty in the operation region 13a during the conduction operation, so the on-resistance is relatively high, limiting The speed of operation and the performance of the components.
對此一缺點之改善，另有先前技術提出利用於DMOS元件中形成降低表面電場(reduce surface field, RESURF)作用，藉此抑制DMOS元件於不導通操作時的高電場，以期能增加元件崩潰防護電壓。然而，此一先前技術之方式仍有缺點: 雖然增加了元件崩潰防護電壓，但是導通電阻亦相對提高，如此一來，將會限制了操作的速度，與元件的性能。To improve this shortcoming, another previous technology proposed to use the effect of reducing the surface electric field (RESURF) in the DMOS device, thereby suppressing the high electric field of the DMOS device during non-conducting operation, so as to increase the protection against component breakdown. Voltage. However, this prior art method still has disadvantages: although the element breakdown protection voltage is increased, the on-resistance is also relatively increased. As a result, the speed of operation and the performance of the element will be limited.
有鑑於此，本發明提出一種在雙擴散金屬氧化物半導體元件於不導通操作時，提高其元件崩潰防護電壓，且於導通操作時，亦能夠降低其導通電阻的雙擴散金屬氧化物半導體元件及其製造方法。In view of this, the present invention proposes a double-diffused metal-oxide-semiconductor device capable of increasing its breakdown protection voltage when the double-diffused metal-oxide-semiconductor device is in non-conducting operation, and capable of reducing its on-resistance during the conductive operation, and Its manufacturing method.
就其中一觀點言，本發明提供了一種雙擴散金屬氧化物半導體(double diffused metal oxide semiconductor, DMOS)元件，包含：一基板，具有第一導電型，且該基板於一垂直方向上，具有相對之一上表面與一下表面；一磊晶層，形成於該基板上，具有相對該上表面之一磊晶層表面，且於該垂直方向上，堆疊並連接於該上表面上；一高壓井區，形成於該磊晶層中，具有第二導電型，且於該垂直方向上，堆疊並連接於該基板之該上表面上，其中，該高壓井區與該基板之該上表面之間具有一第一PN接面；一本體區，形成於該磊晶層中，具有第一導電型，且於該垂直方向上，堆疊並連接於該磊晶層表面下，且由剖視圖視之，於該通道方向上，該本體區與該高壓井區間具有一通道方向接面；一閘極，形成於該磊晶層上，於該垂直方向上，該閘極堆疊並連接於該磊晶層表面上，且由剖視圖視之，該閘極覆蓋至少部分的該通道方向接面；一源極，形成於該磊晶層中，具有第二導電型，且於該垂直方向上，堆疊並連接於該磊晶層表面之下，且由剖視圖視之，該源極位於該本體區中；一汲極，形成於該磊晶層中，具有第二導電型，且於該垂直方向上，堆疊並連接於該磊晶層表面下，且於該通道方向上，該源極與該汲極位於該通道方向接面不同側，且由剖視圖視之，該汲極與該閘極由該高壓井區隔開；一漂移埋區，形成於該磊晶層中，具有第二導電型，其中，由剖視圖視之，於該通道方向上，部分該漂移埋區位於該汲極的正下方，且，該漂移埋區的長度大於或等於該汲極的長度; 以及一埋區，形成於該基板與該磊晶層中，具有第一導電型，且於該垂直方向上，部分該埋區位於該基板中，且另一部分該埋區位於該磊晶層中，其中，由剖視圖視之，於該通道方向上，至少部分該埋區位於該漂移埋區的正下方，且，該埋區的長度大於或等於該汲極的長度，其中，該埋區的長度大於或等於該漂移埋區的長度; 其中，由剖視圖視之，於該通道方向上，該漂移埋區與該埋區之間或該高壓井區與該埋區之間具有一第二PN接面，且，由剖視圖視之，該第二PN接面自該磊晶層表面開始沿著該垂直方向而向下計算所具有的深度，淺於該第一PN接面自該磊晶層表面開始沿著該垂直方向而向下計算所具有的深度；其中，該漂移埋區於該通道方向上具有靠近該閘極之一第一邊界及遠離該閘極之一第二邊界，該埋區於該通道方向上具有靠近該閘極之一第三邊界及遠離該閘極之一第四邊界；其中，該第一邊界及該第三邊界，於該通道方向上，介於該汲極與該通道方向接面之間；該第二邊界及該第四邊界，於該通道方向上，至少超過一第五邊界，其中該第五邊界位於該汲極與靠近該汲極之一絕緣結構之間，其中該絕緣結構用以定義該雙擴散金屬氧化物半導體元件的一元件區。In one aspect, the present invention provides a double diffused metal oxide semiconductor (DMOS) device, including: a substrate having a first conductivity type, and the substrate in a vertical direction having a relative One upper surface and one lower surface; an epitaxial layer formed on the substrate, having an epitaxial layer surface opposite to the upper surface, and stacked and connected to the upper surface in the vertical direction; a high-pressure well A region is formed in the epitaxial layer, has a second conductivity type, and is stacked and connected to the upper surface of the substrate in the vertical direction, wherein the high-voltage well region and the upper surface of the substrate are stacked and connected. Having a first PN junction; a body region formed in the epitaxial layer, having a first conductivity type, and stacked and connected below the surface of the epitaxial layer in the vertical direction, and viewed from a sectional view, In the channel direction, the body region and the high-pressure well section have a channel direction interface; a gate is formed on the epitaxial layer, and in the vertical direction, the gate is stacked and connected to the epitaxial layer. On the surface And viewed from a cross-sectional view, the gate electrode covers at least part of the channel direction junction; a source electrode is formed in the epitaxial layer, has a second conductivity type, and is stacked and connected to the epitaxy in the vertical direction. Below the surface of the crystal layer, and viewed from the cross-sectional view, the source electrode is located in the body region; a drain electrode is formed in the epitaxial layer, has a second conductivity type, and is stacked and connected to the vertical direction. Under the surface of the epitaxial layer and in the direction of the channel, the source and the drain are located on different sides of the interface in the direction of the channel, and viewed from a cross-sectional view, the drain and the gate are separated by the high-pressure well area. A drift buried region formed in the epitaxial layer and having a second conductivity type, in which a portion of the drift buried region is located directly below the drain in the channel direction as viewed from a cross-sectional view; and The length of the buried region is greater than or equal to the length of the drain; and a buried region formed in the substrate and the epitaxial layer, having a first conductivity type, and in the vertical direction, a portion of the buried region is located in the substrate And another part of the buried region is located in the epitaxial layer, where As seen from the cross-sectional view, in the direction of the channel, at least part of the buried area is located directly below the drift buried area, and the length of the buried area is greater than or equal to the length of the drain, wherein the length of the buried area is greater than Or equal to the length of the drift buried area; wherein a second PN junction is provided between the drift buried area and the buried area or between the high pressure well area and the buried area in the direction of the channel as viewed from a cross-sectional view. And, viewed from the cross-sectional view, the second PN junction starts from the surface of the epitaxial layer along the vertical direction and calculates the depth downward, which is shallower than the first PN junction from the surface of the epitaxial layer. The depth is calculated along the vertical direction; wherein the drift buried area has a first boundary near the gate and a second boundary far from the gate in the direction of the channel, the buried area is at The channel direction has a third boundary near the gate and a fourth boundary far from the gate; wherein the first boundary and the third boundary are in the channel direction between the drain and the gate. Between the interface in the direction of the channel; the second boundary and the fourth boundary In the direction of the channel, at least a fifth boundary is exceeded, wherein the fifth boundary is located between the drain and an insulating structure near the drain, wherein the insulating structure is used to define a double-diffused metal oxide semiconductor device. A component area.
在一種較佳的實施型態中，雙擴散金屬氧化物半導體元件更包含一場氧化區，形成於該磊晶層上之該操作區中，且於該垂直方向上，該場氧化區堆疊並連接於該高壓井區，且於該通道方向上，該場氧化區介於該通道方向接面與該汲極之間。In a preferred embodiment, the double-diffused metal oxide semiconductor device further includes a field oxide region formed in the operation region on the epitaxial layer, and the field oxide regions are stacked and connected in the vertical direction. In the high-pressure well region, and in the direction of the channel, the field oxidation region is between the interface in the direction of the channel and the drain.
在一種較佳的實施型態中，雙擴散金屬氧化物半導體元件更包含一接點區，形成於該磊晶層中，具有第一導電型，且於該垂直方向上，堆疊並連接於該磊晶層表面之下，且由剖視圖視之，該接點區位於該本體區中。In a preferred embodiment, the double-diffused metal oxide semiconductor device further includes a contact region formed in the epitaxial layer, having a first conductivity type, and stacked and connected to the vertical direction. Below the surface of the epitaxial layer and viewed from a cross-sectional view, the contact region is located in the body region.
就又一觀點言，本發明提供了一種雙擴散金屬氧化物半導體元件製造方法，包含：提供一基板，該基板具有第一導電型，且該基板於一垂直方向上，具有相對之一上表面與一下表面；形成一磊晶層於該基板上，該磊晶層具有相對該上表面之一磊晶層表面，且於該垂直方向上，堆疊並連接於該上表面上；形成一高壓井區於該磊晶層中，該高壓井區具有第二導電型，且於該垂直方向上，堆疊並連接於該基板之該上表面上，其中，該高壓井區與該基板之該上表面之間具有一第一PN接面；形成一本體區於該磊晶層中，該本體區具有第一導電型，且於該垂直方向上，堆疊並連接於該磊晶層表面下，且由剖視圖視之，於該通道方向上，該本體區與該高壓井區間具有一通道方向接面；形成一閘極於該磊晶層上，於該垂直方向上，該閘極堆疊並連接於該磊晶層表面上，且由剖視圖視之，該閘極覆蓋至少部分的該通道方向接面；形成一源極於該磊晶層中，該源極具有第二導電型，且於該垂直方向上，堆疊並連接於該磊晶層表面之下，且由剖視圖視之，該源極位於該本體區中；形成一汲極於該磊晶層中，該汲極具有第二導電型，且於該垂直方向上，堆疊並連接於該磊晶層表面下，且於該通道方向上，該源極與該汲極位於該通道方向接面不同側，且由剖視圖視之，該汲極與該閘極由該高壓井區隔開；形成一漂移埋區於該磊晶層中，該漂移埋區具有第二導電型，其中，由剖視圖視之，於該通道方向上，部分該漂移埋區位於該汲極的正下方，且，該漂移埋區的長度大於或等於該汲極的長度; 以及形成一埋區於該基板與該磊晶層中，該埋區具有第一導電型，且於該垂直方向上，部分該埋區位於該基板中，且另一部分該埋區位於該磊晶層中，其中，由剖視圖視之，於該通道方向上，至少部分該埋區位於該漂移埋區的正下方，且，該埋區的長度大於或等於該汲極的長度，其中，該埋區的長度大於或等於該漂移埋區的長度; 其中，由剖視圖視之，於該通道方向上，該漂移埋區與該埋區之間或該高壓井區與該埋區之間具有一第二PN接面，且，由剖視圖視之，該第二PN接面自該磊晶層表面開始沿著該垂直方向而向下計算所具有的深度，淺於該第一PN接面自該磊晶層表面開始沿著該垂直方向而向下計算所具有的深度；其中，該漂移埋區於該通道方向上具有靠近該閘極之一第一邊界及遠離該閘極之一第二邊界，該埋區於該通道方向上具有靠近該閘極之一第三邊界及遠離該閘極之一第四邊界；其中，該第一邊界及該第三邊界，於該通道方向上，介於該汲極與該通道方向接面之間；該第二邊界及該第四邊界，於該通道方向上，至少超過一第五邊界，其中該第五邊界位於該汲極與靠近該汲極之一絕緣結構之間，其中該絕緣結構用以定義該雙擴散金屬氧化物半導體元件的一元件區。In yet another aspect, the present invention provides a method for manufacturing a double-diffused metal oxide semiconductor device, including: providing a substrate having a first conductivity type, and the substrate having an opposite upper surface in a vertical direction. And the lower surface; forming an epitaxial layer on the substrate, the epitaxial layer having an epitaxial layer surface opposite to the upper surface, and stacked and connected to the upper surface in the vertical direction; forming a high pressure well In the epitaxial layer, the high-pressure well region has a second conductivity type, and is stacked and connected to the upper surface of the substrate in the vertical direction, wherein the high-pressure well region and the upper surface of the substrate There is a first PN junction between them; a body region is formed in the epitaxial layer, the body region has a first conductivity type, and is stacked and connected below the surface of the epitaxial layer in the vertical direction, and is formed by In the cross-sectional view, in the channel direction, the body region and the high-pressure well section have a channel direction interface; a gate electrode is formed on the epitaxial layer, and in the vertical direction, the gate electrode is stacked and connected to the gate electrode. Epitaxial layer surface And viewed from a cross-sectional view, the gate electrode covers at least part of the channel-direction junction; a source electrode is formed in the epitaxial layer, the source electrode has a second conductivity type, and is stacked and connected in the vertical direction Below the surface of the epitaxial layer and viewed from the cross-sectional view, the source is located in the body region; a drain is formed in the epitaxial layer, the drain has a second conductivity type, and is in the vertical direction , Stacked and connected under the surface of the epitaxial layer, and in the direction of the channel, the source electrode and the drain electrode are located on different sides of the interface direction of the channel, and viewed from a cross-sectional view, the drain electrode and the gate electrode are formed by the The high-pressure well region is separated; a drift buried region is formed in the epitaxial layer, and the drift buried region has a second conductivity type, in which, as viewed from a cross-sectional view, part of the drift buried region is located at the drain electrode in the direction of the channel. And the length of the drift buried region is greater than or equal to the length of the drain; and a buried region is formed in the substrate and the epitaxial layer, the buried region has a first conductivity type and is in the vertical direction Part of the buried area is located in the substrate, and part of the buried area is Located in the epitaxial layer, wherein, as viewed from a cross-sectional view, at least part of the buried region is directly below the drift buried region in the channel direction, and the length of the buried region is greater than or equal to the length of the drain electrode, Wherein, the length of the buried area is greater than or equal to the length of the drift buried area; where viewed from the sectional view, between the drift buried area and the buried area or between the high pressure well area and the buried area in the direction of the channel. There is a second PN junction, and the second PN junction is calculated from the surface of the epitaxial layer along the vertical direction from the surface of the epitaxial layer, and the depth of the second PN junction is shallower than the first PN junction. The depth from the surface of the epitaxial layer is calculated from the surface of the epitaxial layer down the vertical direction; wherein the drift buried region has a first boundary near the gate and a distance from the gate in the direction of the channel. A second boundary, the buried region has a third boundary near the gate and a fourth boundary far from the gate in the channel direction; wherein the first boundary and the third boundary are in the channel direction Between the drain and the interface of the channel; the The second boundary and the fourth boundary exceed at least a fifth boundary in the direction of the channel, wherein the fifth boundary is located between the drain and an insulating structure near the drain, where the insulating structure is used to define An element region of the double-diffused metal oxide semiconductor element.
在一種較佳的實施型態中，雙擴散金屬氧化物半導體元件製造方法更包含: 形成一場氧化區於該磊晶層上之該操作區中，且於該垂直方向上，該場氧化區堆疊並連接於該高壓井區，且於該通道方向上，該場氧化區介於該通道方向接面與該汲極之間。In a preferred embodiment, the method for manufacturing a double-diffused metal oxide semiconductor device further includes: forming a field oxide region in the operation region on the epitaxial layer, and in the vertical direction, the field oxide region is stacked. And connected to the high-pressure well area, and in the direction of the channel, the field oxidation area is between the channel-direction junction and the drain electrode.
在一種較佳的實施型態中，雙擴散金屬氧化物半導體元件製造方法更包含: 形成一接點區於該磊晶層中，該接點區具有第一導電型，且於該垂直方向上，堆疊並連接於該磊晶層表面之下，且由剖視圖視之，該接點區位於該本體區中。In a preferred embodiment, the method for manufacturing a double-diffused metal oxide semiconductor device further includes: forming a contact region in the epitaxial layer, the contact region having a first conductivity type, and in the vertical direction , Stacked and connected below the surface of the epitaxial layer, and viewed from a cross-sectional view, the contact area is located in the body area.
在一種較佳的實施型態中，該漂移埋區中之第二導電型雜質濃度大於該高壓井區中之第二導電型雜質濃度，且，該埋區中之第一導電型雜質濃度大於該基板中之第一導電型雜質濃度。In a preferred embodiment, the second conductivity type impurity concentration in the drift buried area is greater than the second conductivity type impurity concentration in the high pressure well area, and the first conductivity type impurity concentration in the buried area is greater than The first conductivity type impurity concentration in the substrate.
在一種較佳的實施型態中，該第一邊界及該第三邊界，於該通道方向上，位於該場氧化區的正下方的區域間。In a preferred embodiment, the first boundary and the third boundary are located between the regions directly below the field oxidation region in the channel direction.
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。Detailed descriptions will be provided below through specific embodiments to make it easier to understand the purpose, technical content, features and effects of the present invention.
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之一較佳實施例的詳細說明中，將可清楚的呈現。本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The drawings in the present invention are schematic, and are mainly intended to represent the process steps and the order relationship between the layers. As for the shape, thickness, and width, they are not drawn to scale.
請參考第2圖，其顯示本發明的一實施例。本實施例係以N型雙擴散金屬氧化物半導體(double diffused metal oxide semiconductor, DMOS)元件為例說明。Please refer to FIG. 2, which shows an embodiment of the present invention. This embodiment is described by taking an N-type double diffused metal oxide semiconductor (DMOS) device as an example.
如第2圖所示，雙擴散金屬氧化物半導體元件200包含：基板27、磊晶層22、絕緣結構23f、絕緣結構23r、高壓井區25、本體區26、場氧化區24、接點區26a、埋區41、漂移埋區42、源極28、汲極29以及閘極21。其中，值得注意的是，本發明與先前技術具有下述的差異: 由於本發明包含埋區41與漂移埋區42，因此漂移埋區42與埋區41之間或者高壓井區25與埋區41之間會具有一深度較淺的PN接面(PN junction)PN2。然而，先前技術並不具有此一深度較淺的PN接面PN2 (關於埋區41與漂移埋區42的特徵及細節及深度較淺的PN接面PN2的特徵，容後詳述)。As shown in FIG. 2, the double-diffused metal oxide semiconductor device 200 includes a substrate 27, an epitaxial layer 22, an insulating structure 23f, an insulating structure 23r, a high-voltage well region 25, a body region 26, a field oxidation region 24, and a contact region. 26a, buried region 41, drift buried region 42, source 28, drain 29, and gate 21. It is worth noting that the present invention has the following differences from the prior art: Since the present invention includes a buried region 41 and a drift buried region 42, the drift buried region 42 and the buried region 41 or the high-pressure well region 25 and the buried region A shallower PN junction PN2 is provided between 41. However, the prior art does not have such a shallow PN junction PN2 (for the characteristics and details of the buried region 41 and the drift buried region 42 and the characteristics of the shallow PN junction PN2, details will be described later).
其中，基板27具有第一導電型，例如但不限於為P型，且於垂直方向(如圖中粗虛線箭號所示的方向)上，具有相對之上表面21a與下表面21b。 磊晶層22以磊晶製程步驟形成於基板27上，具有相對上表面21a之磊晶層表面22a，且於垂直方向上，堆疊並連接於上表面21a上。絕緣結構23f及絕緣結構23r例如但不限於為區域氧化(local oxidation of silicon, LOCOS)結構，以定義操作區23a，作為雙擴散金屬氧化物半導體元件200操作時主要的作用區。且本體區26、源極28、與汲極29，由剖視圖第2圖視之，皆位於操作區23a之中。高壓井區25形成於磊晶層22中，具有第二導電型，例如但不限於為N型，且於垂直方向上，堆疊並連接於基板27之上表面21a上。在本實施例中，由於基板27具有第一導電型，例如但不限於為P型，且高壓井區25具有第二導電型，例如但不限於為N型，因此高壓井區25與基板27之上表面21a之間具有一PN接面PN1。The substrate 27 has a first conductivity type, such as, but not limited to, a P-type, and has an upper surface 21a and a lower surface 21b opposite to each other in a vertical direction (a direction indicated by a thick dashed arrow in the figure). The epitaxial layer 22 is formed on the substrate 27 by an epitaxial process step, has an epitaxial layer surface 22a opposite to the upper surface 21a, and is stacked and connected to the upper surface 21a in a vertical direction. The insulating structure 23f and the insulating structure 23r are, for example, but not limited to, a local oxidation of silicon (LOCOS) structure. The operating region 23a is defined as a main active region of the double-diffused metal oxide semiconductor device 200 during operation. The body region 26, the source electrode 28, and the drain electrode 29 are located in the operation region 23a as viewed from the second view of the cross-sectional view. The high-pressure well region 25 is formed in the epitaxial layer 22 and has a second conductivity type, such as, but not limited to, an N-type, and is stacked and connected to the upper surface 21 a of the substrate 27 in a vertical direction. In this embodiment, since the substrate 27 has a first conductivity type, such as but not limited to a P-type, and the high-pressure well region 25 has a second conductivity type, such as but not limited to an N-type, the high-pressure well region 25 and the substrate 27 There is a PN interface PN1 between the upper surfaces 21a.
本體區26形成於磊晶層22中，具有第一導電型，其例如但不限於為P型，且於垂直方向上，堆疊並連接於磊晶層表面202a下，且於通道方向(如圖中粗實線箭號所示的方向)上，本體區26與高壓井區25具有一通道方向接面JN，如第2圖中粗實線所示意。閘極21形成於磊晶層22上，且於垂直方向上，閘極21堆疊並連接於磊晶層表面22a上，且由剖視圖第2圖視之，閘極21覆蓋至少部分通道方向接面JN。在本實施例中，例如但不限於覆蓋全部的通道方向接面JN。源極28形成於磊晶層22中，具有第二導電型，例如但不限於為N型，且於垂直方向上，堆疊並連接於磊晶層表面22a之下，且由剖視圖第2圖視之，源極28位於本體區26中。汲極29形成於磊晶層22中，具有第二導電型，例如但不限於為N型，且於垂直方向上，堆疊並連接於磊晶層表面22a下，且於通道方向上，源極28與汲極29位於通道方向接面JN之不同側，且由剖視圖第2圖視之，汲極29與閘極21由高壓井區25隔開。The body region 26 is formed in the epitaxial layer 22 and has a first conductivity type, such as, but not limited to, a P-type, and is stacked and connected below the epitaxial layer surface 202a in a vertical direction and in a channel direction (as shown in FIG. In the direction indicated by the solid and thick solid line arrows), the body region 26 and the high-pressure well region 25 have a channel direction junction JN, as shown by the thick solid line in FIG. 2. The gate 21 is formed on the epitaxial layer 22, and in a vertical direction, the gate 21 is stacked and connected to the surface 22a of the epitaxial layer, and as viewed from the second view of the cross-sectional view, the gate 21 covers at least part of the channel direction junction JN. In this embodiment, for example, but not limited to, all the channel direction joints JN are covered. The source electrode 28 is formed in the epitaxial layer 22 and has a second conductivity type, such as, but not limited to, N-type, and is stacked and connected below the epitaxial layer surface 22a in a vertical direction. In other words, the source electrode 28 is located in the body region 26. The drain electrode 29 is formed in the epitaxial layer 22 and has a second conductivity type, such as, but not limited to, N-type, and is stacked and connected under the epitaxial layer surface 22a in the vertical direction, and in the channel direction, the source electrode 28 and the drain electrode 29 are located on different sides of the junction JN in the channel direction, and viewed from the second view of the sectional view, the drain electrode 29 and the gate electrode 21 are separated by a high-pressure well region 25.
場氧化區24形成於磊晶層22上之操作區23a中，且於垂直方向上，場氧化區24堆疊並連接於高壓井區25，且於通道方向上，場氧化區24介於通道方向接面JN與汲極29之間。The field oxidation region 24 is formed in the operation region 23 a on the epitaxial layer 22. In the vertical direction, the field oxidation region 24 is stacked and connected to the high-pressure well region 25. In the channel direction, the field oxidation region 24 is in the channel direction. Junction JN and drain 29.
接點區26a形成於磊晶層22中，具有第一導電型，例如但不限於P型，且於垂直方向上，堆疊並連接於磊晶層表面22a之下，且由剖視圖第2圖視之，接點區26a位於本體區26中，用以作為本體區26電性接點。The contact region 26a is formed in the epitaxial layer 22 and has a first conductivity type, such as, but not limited to, a P-type, and is stacked and connected below the epitaxial layer surface 22a in a vertical direction. In other words, the contact area 26 a is located in the body area 26 and serves as an electrical contact of the body area 26.
漂移埋區42形成於磊晶層22中，具有第二導電型，例如但不限於N型。在一實施例中，漂移埋區42中之第二導電型 (例如但不限於N型)濃度大於高壓井區25中之第二導電型 (例如但不限於N型) 雜質濃度。其中，由剖視圖第2圖視之，於通道方向上，部分漂移埋區42位於汲極29的正下方。且，值得注意的是，在一實施例中，漂移埋區42的長度W42大於汲極29的長度W29。然而，在另一實施例中，漂移埋區42的長度W42亦可等於汲極29的長度W29。The drift buried region 42 is formed in the epitaxial layer 22 and has a second conductivity type, such as, but not limited to, an N-type. In one embodiment, the concentration of the second conductivity type (eg, but not limited to N-type) in the drift buried region 42 is greater than the impurity concentration of the second conductivity type (eg, but not limited to N-type) in the high-pressure well region 25. Among them, as seen in the second view of the cross-sectional view, in the channel direction, part of the drift buried region 42 is located directly below the drain electrode 29. Moreover, it is worth noting that, in an embodiment, the length W42 of the drift buried region 42 is greater than the length W29 of the drain electrode 29. However, in another embodiment, the length W42 of the drift buried region 42 may also be equal to the length W29 of the drain electrode 29.
埋區41形成於基板27與磊晶層22中，具有第一導電型，例如但不限於為P型。在一實施例中，埋區41中之第一導電型(例如但不限於P型) 雜質濃度大於基板27中之第一導電型(例如但不限於P型) 雜質濃度。且於垂直方向上，部分埋區41(在本實施例中，例如為下半部)位於基板27中，且另一部分(在本實施例中，例如為上半部)埋區41位於磊晶層22中。由剖視圖第2圖視之，於通道方向上，部分埋區41位於漂移埋區42的正下方。且，值得注意的是，在一實施例中，埋區41的長度W41大於汲極29的長度W29。然而，在另一實施例中，埋區41的長度W41亦可等於汲極29的長度W29。The buried region 41 is formed in the substrate 27 and the epitaxial layer 22 and has a first conductivity type, such as, but not limited to, a P-type. In an embodiment, the impurity concentration of the first conductivity type (for example, but not limited to P type) in the buried region 41 is greater than the impurity concentration of the first conductivity type (for example, but not limited to P type) in the substrate 27. And in the vertical direction, part of the buried region 41 (for example, the lower half in this embodiment) is located in the substrate 27, and another part (for example, the upper half in this embodiment) of the buried region 41 is located in the epitaxial In layer 22. From the second view of the cross-sectional view, in the channel direction, a part of the buried region 41 is located directly below the drift buried region 42. Moreover, it is worth noting that, in an embodiment, the length W41 of the buried region 41 is greater than the length W29 of the drain electrode 29. However, in another embodiment, the length W41 of the buried region 41 may be equal to the length W29 of the drain electrode 29.
又，值得注意的是，在一實施例中，埋區41的長度W41大於漂移埋區42的長度W42。然而，在另一實施例中，埋區41的長度W41亦可等於漂移埋區42的長度W42。意即，在本實施例中，長度W41≥長度W42。需說明的是，在本實施例中，漂移埋區42與埋區41之間，由高壓井區25隔開；而在一實施例中，漂移埋區42與埋區41亦可以直接鄰接，因此，PN接面PN2在不同的實施例中，可由埋區41與高壓井區25形成，亦可以為埋區41與漂移埋區42所形成。又，值得注意的是，在本實施例中，漂移埋區42與汲極29之間，由高壓井區25隔開；而在一實施例中，漂移埋區42與汲極29亦可以直接鄰接。It is also worth noting that, in an embodiment, the length W41 of the buried region 41 is greater than the length W42 of the drift buried region 42. However, in another embodiment, the length W41 of the buried region 41 may be equal to the length W42 of the drift buried region 42. That is, in this embodiment, the length W41 ≧ the length W42. It should be noted that, in this embodiment, the drift buried region 42 and the buried region 41 are separated by the high-pressure well region 25. In one embodiment, the drift buried region 42 and the buried region 41 may also be directly adjacent to each other. Therefore, in different embodiments, the PN junction PN2 may be formed by the buried region 41 and the high-pressure well region 25, and may also be formed by the buried region 41 and the drift buried region 42. It is also worth noting that, in this embodiment, the drift buried region 42 and the drain electrode 29 are separated by a high-pressure well region 25; and in one embodiment, the drift buried region 42 and the drain electrode 29 can also be directly Adjacency.
於通道方向上，埋區41於通道方向上具有靠近閘極21之邊界B1及遠離閘極21之邊界B2，而漂移埋區42於通道方向上具有靠近閘極21之邊界C1及遠離閘極21之邊界C2。由剖視圖第2圖視之，埋區41之邊界B1與漂移埋區42之邊界C1，於通道方向上，介於汲極29與通道方向接面JN之間。埋區41之邊界B2與漂移埋區42之邊界C2，於通道方向上，至少超過邊界M1。根據第2圖所示，邊界M1係位於汲極29與靠近汲極29之絕緣結構23r之間。In the channel direction, the buried region 41 has a boundary B1 near the gate 21 and a boundary B2 far from the gate 21 in the channel direction, and the drift buried region 42 has a boundary C1 near the gate 21 and far from the gate in the channel direction. 21 of the boundary C2. From the second view of the cross-sectional view, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 are in the channel direction between the drain electrode 29 and the channel direction junction JN. The boundary B2 of the buried region 41 and the boundary C2 of the drift buried region 42 at least exceed the boundary M1 in the channel direction. As shown in FIG. 2, the boundary M1 is located between the drain electrode 29 and the insulating structure 23 r near the drain electrode 29.
值得注意的是，在一實施例中，埋區41之邊界B1與漂移埋區42之邊界C1，於通道方向上，介於汲極29與通道方向接面JN之間。意即，在一實施例中，埋區41之邊界B1與漂移埋區42之邊界C1可位於汲極29與通道方向接面JN之間的區域L1間。然而，在另一實施例中，埋區41之邊界B1與漂移埋區42之邊界C1則可於通道方向上，位於場氧化區24的正下方的區域L2間。It is worth noting that, in an embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 are between the drain electrode 29 and the channel direction junction JN in the channel direction. That is, in an embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 may be located between the region L1 between the drain electrode 29 and the channel-direction junction JN. However, in another embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 may be located in the channel direction between the region L2 directly below the field oxidation region 24.
又，值得注意的是，在一實施例中，埋區41之邊界B2與漂移埋區42之邊界C2，於通道方向上，可於通道方向上，位於邊界M1及第2圖所示的邊界M2之間的區域P。又，值得注意的是，在一實施例中，亦可以由一第一導電型或第二導電型摻雜之區域，將原生基板分為基板27與磊晶層22兩個區域，此為本領域中具有通常知識者所熟知，在此不予贅述。It is also worth noting that, in an embodiment, the boundary B2 of the buried area 41 and the boundary C2 of the drift buried area 42 are located in the channel direction and in the channel direction at the boundary M1 and the boundary shown in FIG. 2 Area P between M2. It is also worth noting that, in an embodiment, the primary substrate can also be divided into two regions of the substrate 27 and the epitaxial layer 22 by a region doped with a first conductivity type or a second conductivity type. Those with ordinary knowledge in the field are well-known and will not be repeated here.
值得注意的是，本發明與先前技術具有下述的差異: 由於本發明包含埋區41與漂移埋區42，且，在本實施例中，由於埋區41具有第一導電型，例如但不限於為P型，且漂移埋區42具有第二導電型，例如但不限於為N型，且高壓井區25具有第二導電型，例如但不限於為N型，因此，在本實施例中，漂移埋區42與埋區41之間會具有一PN接面PN2。或者，高壓井區25與埋區41之間會具有一PN接面PN2。由剖視圖視之， PN接面PN2自磊晶層表面22a開始沿著垂直方向而向下計算所具有的深度H2，淺於PN接面PN1(高壓井區25與基板27之上表面21a之間所形成的)自磊晶層表面22a開始沿著垂直方向而向下計算所具有的深度H1。意即，深度H2＜深度H1。It is worth noting that the present invention has the following differences from the prior art: Since the present invention includes a buried region 41 and a drift buried region 42, and in this embodiment, since the buried region 41 has a first conductivity type, for example, but not It is limited to P type, and the drift buried region 42 has a second conductivity type, such as but not limited to N type, and the high pressure well region 25 has a second conductivity type, such as but not limited to N type. Therefore, in this embodiment, There will be a PN junction PN2 between the drift buried region 42 and the buried region 41. Alternatively, there may be a PN interface PN2 between the high-pressure well area 25 and the buried area 41. From the cross-sectional view, the PN junction PN2 has a depth H2 calculated from the epitaxial layer surface 22a in the vertical direction and is lower than the PN junction PN1 (between the high-pressure well region 25 and the upper surface 21a of the substrate 27) The formed depth H1 is calculated from the epitaxial layer surface 22a downward in the vertical direction. That is, the depth H2 <the depth H1.
本發明正是因為在靠近汲極29處具有一較淺深度H2的PN接面PN2，因而在雙擴散金屬氧化物半導體元件200不導通的操作下，由於漂移埋區42具有濃度較高壓井區25高的N型雜質摻雜，且埋區41具有濃度較基板27高的P型雜質摻雜；在靠近汲極29處的PN接面PN2附近，可形成空乏區，與雙擴散金屬氧化物半導體元件200本身操作時的橫向空乏區結合，形成大範圍的空乏區，以抑制雙擴散金屬氧化物半導體元件200於不導通操作時的高電場。如此一來，可以使PN接面PN2的崩潰防護電壓提高，又同時能夠降低導通電阻。The present invention is because the PN junction PN2 with a shallower depth H2 is near the drain 29. Therefore, under the operation that the double-diffused metal oxide semiconductor device 200 is not conductive, the drift buried region 42 has a higher concentration well killing region. 25 high N-type impurity doping, and the buried region 41 has a higher P-type impurity doping than the substrate 27; near the PN junction PN2 near the drain 29, an empty region can be formed, and double-diffused metal oxide The lateral empty regions during the operation of the semiconductor device 200 are combined to form a large range of empty regions to suppress the high electric field of the double-diffused metal oxide semiconductor device 200 during non-conducting operation. In this way, the collapse protection voltage of the PN interface PN2 can be increased, and at the same time, the on-resistance can be reduced.
然而，先前技術並不具有此一深度較淺的PN接面PN2。相較於本發明具有二個PN接面(意即PN接面PN1與PN接面PN2，且，靠近汲極29處的PN接面PN2的深度H2淺於PN接面PN1的深度H1)，先前技術僅具有單一個PN接面PN0中。且，在先前技術中，靠近汲極19處的PN接面PN0的深度(圖未示)與靠近源極18處的PN接面PN0的深度(圖未示)皆是一樣的，並沒有深淺之差異。However, the prior art does not have such a shallow PN junction PN2. Compared with the present invention having two PN junctions (meaning PN junction PN1 and PN junction PN2, and the depth H2 of the PN junction PN2 near the drain 29 is shallower than the depth H1 of the PN junction PN1), The prior art has only a single PN junction PN0. Moreover, in the prior art, the depth (not shown) of the PN junction PN0 near the drain 19 and the depth (not shown) of the PN junction PN0 near the source 18 are the same, and there is no depth. Difference.
請參考第3A~3G圖，其顯示本發明之雙擴散金屬氧化物半導體元件製造方法的一實施例。Please refer to FIGS. 3A to 3G, which show an embodiment of a method for manufacturing a double-diffused metal oxide semiconductor device according to the present invention.
首先，如剖視示意圖第3A圖所示，提供P型基板27，其中，基板27例如但不限於為P型矽基板，亦可以為其他P型半導體基板。P型基板27於垂直方向上(如第3A圖中粗虛線箭號所示的方向)，具有相對之上表面21a與下表面21b。接著如第3A圖所示，形成磊晶層22於P型基板27上，且於垂直方向上，具有相對上表面21a之磊晶層表面22a，磊晶層22堆疊並連接於上表面21a上。接著例如以離子植入製程，將第二導電型雜質，以加速離子的形式，如第3A圖中細虛線箭號所示意，植入定義的區域內形成高壓井區25於磊晶層22中，具有第二導電型，例如但不限於為N型，且於垂直方向上，堆疊並連接於基板27之上表面21a上。高壓井區25與基板27之上表面21a之間具有一PN接面PN1。須說明的是，埋區41形成於基板27與磊晶層22中，具有第一導電型，例如但不限於為P型，且於垂直方向上，部分埋區41(在本實施例中，例如為下半部)位於基板27中，且另一部分(在本實施例中，例如為上半部)埋區41位於磊晶層22中。在一實施例中，埋區41中之第一導電型 (例如但不限於P型) 雜質濃度大於基板27中之第一導電型 (例如但不限於P型) 雜質濃度。埋區41例如但不限於以微影製程形成光阻層(未示出)為遮罩，以定義離子植入範圍，並以離子植入製程，將P型雜質，以加速離子的形式，植入定義的植入範圍內，而形成埋區離子植入區於基板27中，接著再將光阻層去除；接著再於磊晶層22形成後，以退火(anneal)製程步驟，將部分植入範圍內的P型雜質，熱擴散至磊晶層22中，以形成埋區41；此為本領域中具有通常知識者所熟知，在此不予贅述。First, as shown in FIG. 3A of the cross-sectional view, a P-type substrate 27 is provided. The substrate 27 is, for example but not limited to, a P-type silicon substrate, and may also be other P-type semiconductor substrates. The P-type substrate 27 has an upper surface 21 a and a lower surface 21 b opposite to each other in a vertical direction (as indicated by a thick dashed arrow in FIG. 3A). Next, as shown in FIG. 3A, an epitaxial layer 22 is formed on the P-type substrate 27 and has an epitaxial layer surface 22a opposite to the upper surface 21a in a vertical direction. The epitaxial layer 22 is stacked and connected to the upper surface 21a. . Then, for example, in the ion implantation process, the second conductive type impurities are accelerated in the form of ions. As shown by the thin dashed arrows in FIG. 3A, a high-pressure well region 25 is formed in the epitaxial layer 22 in a defined area. Has a second conductivity type, such as, but not limited to, N-type, and is stacked and connected to the upper surface 21 a of the substrate 27 in a vertical direction. There is a PN interface PN1 between the high-pressure well region 25 and the upper surface 21a of the substrate 27. It should be noted that the buried region 41 is formed in the substrate 27 and the epitaxial layer 22 and has a first conductivity type, such as, but not limited to, a P-type. In the vertical direction, part of the buried region 41 (in this embodiment, The lower half, for example, is located in the substrate 27, and the other part (for example, the upper half in this embodiment) of the buried region 41 is located in the epitaxial layer 22. In an embodiment, the impurity concentration of the first conductivity type (such as, but not limited to, P type) in the buried region 41 is greater than the impurity concentration of the first conductivity type (such as, but not limited to, P type) in the substrate 27. The buried region 41 is, for example but not limited to, a photoresist layer (not shown) formed as a mask by a lithography process to define an ion implantation range, and an ion implantation process is used to implant P-type impurities in the form of accelerated ions to implant Within the defined implantation range, a buried area ion implantation area is formed in the substrate 27, and then the photoresist layer is removed; after the epitaxial layer 22 is formed, an annealing process step is used to partially implant the P-type impurities in the range of heat are thermally diffused into the epitaxial layer 22 to form the buried region 41; this is well known to those having ordinary knowledge in the art, and will not be repeated here.
接著，如第3B圖所示，漂移埋區42形成於磊晶層22中，具有第二導電型，例如但不限於為N型。在一實施例中，漂移埋區42中之第二導電型雜質(例如但不限於N型)濃度大於高壓井區25中之第二導電型雜質濃度(例如但不限於N型)。漂移埋區42例如但不限於以微影製程形成光阻層(未示出)為遮罩，以定義離子植入範圍，並以離子植入製程，將N型雜質，以加速離子的形式，植入定義的植入範圍內，而形成漂移埋區離子植入區於基板27中，接著再將光阻層去除；接著再於磊晶層22形成後，以退火(anneal)製程步驟，將部分植入範圍內的N型雜質，熱擴散至磊晶層22中，以形成漂移埋區42；此為本領域中具有通常知識者所熟知，在此不予贅述。由剖視圖第3B圖視之，於通道方向上，部分埋區41位於漂移埋區42的正下方。Next, as shown in FIG. 3B, the drift buried region 42 is formed in the epitaxial layer 22 and has a second conductivity type, such as, but not limited to, an N type. In one embodiment, the concentration of the second conductivity type impurity (for example, but not limited to N-type) in the drift buried region 42 is greater than the concentration of the second conductivity type impurity (for example, but not limited to N-type) in the high-pressure well region 25. The drift buried region 42 is, for example but not limited to, a photoresist layer (not shown) formed as a mask by a lithography process to define an ion implantation range, and an N-type impurity is used in the form of accelerated ions in the ion implantation process. Implanted within the defined implantation range to form a drift buried region ion implanted region in the substrate 27, and then remove the photoresist layer; after the epitaxial layer 22 is formed, an annealing process step is performed to Part of the N-type impurities in the implanted range are thermally diffused into the epitaxial layer 22 to form the drift buried region 42; this is well known to those having ordinary knowledge in the art and will not be described in detail here. As seen from the sectional view in FIG. 3B, in the channel direction, part of the buried region 41 is located directly below the drift buried region 42.
值得注意的是，如第3B圖所示，在一實施例中，埋區41的長度W41大於漂移埋區42的長度W42。然而，在另一實施例中，埋區41的長度W41亦可等於漂移埋區42的長度W42。意即，在本實施例中，長度W41≥長度W42。It is worth noting that, as shown in FIG. 3B, in one embodiment, the length W41 of the buried region 41 is greater than the length W42 of the drift buried region 42. However, in another embodiment, the length W41 of the buried region 41 may be equal to the length W42 of the drift buried region 42. That is, in this embodiment, the length W41 ≧ the length W42.
須說明的是，上述形成埋區41與漂移埋區42之製程步驟的順序可以互換，本發明不限於要先形成埋區41再形成漂移埋區42。亦可以先形成漂移埋區42再形成埋區41。It should be noted that the order of the process steps of forming the buried region 41 and the drift buried region 42 may be interchanged, and the present invention is not limited to the formation of the buried region 41 and then the drift buried region 42. It is also possible to form the drift buried region 42 before forming the buried region 41.
接下來，如剖視示意圖第3C圖所示，形成絕緣結構23f及絕緣結構23r於磊晶層22上，以定義操作區23a；同時或接著形成場氧化區24於磊晶層22上之操作區23a中，且於垂直方向上，場氧化區24堆疊並連接於高壓井區25。其中，絕緣結構23f、絕緣結構23r與場氧化區24為如圖所示之區域氧化(local oxidation of silicon, LOCOS)結構或淺溝槽絕緣(shallow trench isolation, STI)結構。Next, as shown in FIG. 3C of the cross-sectional view, forming an insulating structure 23f and an insulating structure 23r on the epitaxial layer 22 to define an operation region 23a; simultaneously or subsequently forming a field oxide region 24 on the epitaxial layer 22 In the region 23a, the field oxidation region 24 is stacked and connected to the high-pressure well region 25 in the vertical direction. The insulating structure 23f, the insulating structure 23r, and the field oxide region 24 are a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure as shown in the figure.
接下來，如剖視示意圖第3D圖所示，形成本體區26於磊晶層22中，具有第一導電型，例如但不限於為P型，且於垂直方向上，堆疊並連接於磊晶層表面22a下，且於通道方向上，本體區26與高壓井區25間具有通道方向接面JN，如第3D圖中粗實線所示意。本體區26例如但不限於以微影製程形成光阻層26b為遮罩，以定義離子植入範圍，並以離子植入製程，將P型雜質，以加速離子的形式，植入定義的植入範圍內，而形成本體區離子植入區於基板27中，接著再將光阻層去除。Next, as shown in the cross-sectional schematic diagram 3D, a body region 26 is formed in the epitaxial layer 22 and has a first conductivity type, such as, but not limited to, a P-type, and is stacked and connected to the epitaxial in a vertical direction. Below the layer surface 22a and in the channel direction, there is a channel direction junction JN between the body region 26 and the high-pressure well region 25, as shown by the thick solid line in FIG. 3D. The body region 26 uses, for example, but is not limited to, a photoresist layer 26b as a mask to define an ion implantation range, and an ion implantation process to implant a P-type impurity in the form of accelerated ions into a defined implant. Within the range, an ion implantation region in the body region is formed in the substrate 27, and then the photoresist layer is removed.
接下來，如剖視示意圖第3E圖所示，形成閘極21於磊晶層22上，且於垂直方向上，閘極21堆疊並連接於磊晶層表面22a上，且由剖視圖第3E圖視之，閘極21覆蓋至少部分通道方向接面JN，在本實施例中，例如但不限於覆蓋全部的通道方向接面JN。Next, as shown in FIG. 3E of the cross-sectional view, the gate electrode 21 is formed on the epitaxial layer 22, and the gate electrode 21 is stacked and connected to the epitaxial layer surface 22a in a vertical direction, and the cross-sectional view is shown in FIG. 3E. In view of this, the gate electrode 21 covers at least a part of the channel direction junction JN. In this embodiment, for example, but not limited to, it covers all the channel direction junction JN.
接下來，如剖視示意圖第3F圖所示，形成源極28與汲極29於磊晶層22中，具有第二導電型，例如但不限於為N型，且於垂直方向上，堆疊並連接於磊晶層表面22a下，且由剖視示意圖第3F圖視之，源極28位於本體區26中。汲極29形成於磊晶層22中，具有第二導電型，例如但不限於為N型，且於垂直方向上，堆疊並連接於磊晶層表面22a下，且於通道方向上，源極28與汲極29位於通道方向接面JN不同側，且由剖視示意圖第3F圖視之，汲極29與閘極21由高壓井區25隔開。Next, as shown in FIG. 3F of the schematic cross-sectional view, a source electrode 28 and a drain electrode 29 are formed in the epitaxial layer 22 and have a second conductivity type, such as but not limited to an N type, and are stacked and stacked in a vertical direction. The source electrode 28 is located below the epitaxial layer surface 22 a and is viewed from the sectional view in FIG. 3F. The source electrode 28 is located in the body region 26. The drain electrode 29 is formed in the epitaxial layer 22 and has a second conductivity type, such as, but not limited to, N-type, and is stacked and connected under the epitaxial layer surface 22a in the vertical direction, and in the channel direction, the source electrode 28 and the drain electrode 29 are located on different sides of the junction JN in the channel direction, and as seen from the sectional view in FIG. 3F, the drain electrode 29 and the gate electrode 21 are separated by a high-pressure well region 25.
其中，例如在N型雙擴散金屬氧化物半導體元件200中，於導通操作中，導通電流由N型汲極29流經高壓井區25與本體區26，而至源極28，此通道路徑是指因施加正電壓於閘極21，而於P型本體區26與閘極21接面處形成通道(channel)，因此導通操作時，導通電流由汲極29流至源極28，此為本領域中具有通常知識者所熟知，在此不予贅述。For example, in the N-type double-diffused metal oxide semiconductor device 200, during the conduction operation, the conduction current flows from the N-type drain electrode 29 through the high-voltage well region 25 and the body region 26 to the source electrode 28. This channel path is It means that a channel is formed at the interface between the P-type body region 26 and the gate 21 due to the application of a positive voltage to the gate 21, so during the conduction operation, the conduction current flows from the drain 29 to the source 28. Those with ordinary knowledge in the field are well-known and will not be repeated here.
源極28與汲極29例如但不限於由相同的微影製程步驟與相同的離子植入製程步驟所形成。如第3F圖所示，例如但不限於以微影製程形成光阻層28a與閘極21為遮罩，定義N型源極28與N型汲極29，並以離子植入製程，將N型雜質，以加速離子的形式，如第3F圖中虛線箭號所示意，植入定義的區域內，而形成N型源極28與N型汲極29於磊晶層表面22a下。The source electrode 28 and the drain electrode 29 are formed by, for example, but not limited to, the same lithography process steps and the same ion implantation process steps. As shown in FIG. 3F, for example, but not limited to, a photoresist layer 28a and a gate electrode 21 are formed as masks by a lithography process, and an N-type source electrode 28 and an N-type drain electrode 29 are defined. In the form of accelerated ions, as shown by the dashed arrows in FIG. 3F, the type impurities are implanted into the defined area, and an N-type source 28 and an N-type drain 29 are formed under the epitaxial layer surface 22a.
值得注意的是，在一實施例中，埋區41之邊界B1與漂移埋區42之邊界C1，於通道方向上，介於汲極29與通道方向接面JN之間。意即，在一實施例中，埋區41之邊界B1與漂移埋區42之邊界C1可位於汲極29與通道方向接面JN之間的區域L1間。然而，在另一實施例中，埋區41之邊界B1與漂移埋區42之邊界C1則可於通道方向上，位於場氧化區24的正下方的區域L2間。It is worth noting that, in an embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 are between the drain electrode 29 and the channel direction junction JN in the channel direction. That is, in an embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 may be located between the region L1 between the drain electrode 29 and the channel-direction junction JN. However, in another embodiment, the boundary B1 of the buried region 41 and the boundary C1 of the drift buried region 42 may be located in the channel direction between the region L2 directly below the field oxidation region 24.
又，值得注意的是，在一實施例中，埋區41之邊界B2與漂移埋區42之邊界C2，於通道方向上，可於通道方向上，位於邊界M1及第2圖所示的邊界M2之間的區域P。It is also worth noting that, in an embodiment, the boundary B2 of the buried area 41 and the boundary C2 of the drift buried area 42 are located in the channel direction and in the channel direction at the boundary M1 and the boundary shown in FIG. 2 Area P between M2.
由剖視示意圖第3F圖視之，在本實施例中，漂移埋區42與埋區41之間會具有一PN接面PN2。或者，高壓井區25與埋區41之間會具有一PN接面PN2。由剖視圖視之， PN接面PN2自磊晶層表面22a開始沿著垂直方向而向下計算所具有的深度H2，淺於PN接面PN1(高壓井區25與基板27之上表面21a之間所形成的)自磊晶層表面22a開始沿著垂直方向而向下計算所具有的深度H1。意即，深度H2＜深度H1。As seen from the schematic sectional view in FIG. 3F, in this embodiment, a PN interface PN2 is provided between the drift buried region 42 and the buried region 41. Alternatively, there may be a PN interface PN2 between the high-pressure well area 25 and the buried area 41. From the cross-sectional view, the PN junction PN2 has a depth H2 calculated from the epitaxial layer surface 22a in a vertical direction and is shallower than the PN junction PN1 (between the high-pressure well region 25 and the upper surface 21a of the substrate 27). The formed depth H1 is calculated from the epitaxial layer surface 22a downward in the vertical direction. That is, the depth H2 <the depth H1.
接下來，如剖視示意圖第3G圖所示，形成接點區26a於磊晶層22中，具有第一導電型，例如但不限於為P型，且於垂直方向上，堆疊並連接於磊晶層表面22a下。接點區26a例如但不限於以微影製程形成光阻層26b為遮罩，以定義離子植入範圍，並以離子植入製程，將P型雜質，以加速離子的形式，植入定義的植入範圍內，而形成接點區離子植入區於磊晶層22中，接著再將光阻層去除；接著再以退火(anneal)製程步驟，將植入範圍內的P型雜質退火，以形成接點區26a；此為本領域中具有通常知識者所熟知，製程步驟細節在此不予贅述。Next, as shown in FIG. 3G of the cross-sectional view, a contact region 26a is formed in the epitaxial layer 22, and has a first conductivity type, such as, but not limited to, a P-type, and is stacked and connected to the epitaxial in a vertical direction. Under the crystal layer surface 22a. The contact area 26a is, for example, but not limited to, a photoresist layer 26b formed as a mask by a lithography process to define an ion implantation range, and an ion implantation process is used to implant P-type impurities in the form of accelerated ions to implant the defined Within the implantation range, a contact region ion implantation region is formed in the epitaxial layer 22, and then the photoresist layer is removed; and then an annealing process step is used to anneal the P-type impurities in the implantation range. The contact area 26a is formed; this is well known to those having ordinary knowledge in the art, and the details of the process steps are not repeated here.
值得注意的是，以上第2圖及第3A~3G圖中，本體區26亦可替換成P型井區(相同概念當然也可適用於N型元件，只要相應改變摻雜區即可)。本發明中所述的本體區係利用自我對準植入製程決定通道的長度。也就是說，通道是藉由本體區的自我對準植入製程而形成的。然而，本發明中所述的P型井區係利用P型井區與多晶矽層(poly)的彼此重疊而決定通道的長度。也就是說，通道是藉由P型井區的遮罩而形成的。It is worth noting that, in the above Figure 2 and Figures 3A to 3G, the body region 26 can also be replaced with a P-type well region (of course, the same concept can also be applied to N-type elements, as long as the doped region is changed accordingly). The body region in the present invention uses a self-aligned implantation process to determine the length of the channel. In other words, the channel is formed by the self-aligned implantation process in the body region. However, the P-type well region described in the present invention uses the P-type well region and the polycrystalline silicon layer (poly) to overlap each other to determine the length of the channel. In other words, the channel is formed by the mask of the P-well area.
以上第2圖及第3A~3G圖雖係以N型元件為例來加以說明，但相同概念當然也可適用於P型元件，只要相應改變摻雜的雜質種類與濃度即可。Although Fig. 2 and Figs. 3A to 3G above use N-type elements as an example for description, the same concept can of course be applied to P-type elements, as long as the type and concentration of impurities doped can be changed accordingly.
此外，請參考第4~6圖。第4~6圖示出，對應於第2圖，本發明之雙擴散金屬氧化物半導體元件的電性示意圖。In addition, please refer to Figures 4 to 6. Figures 4 to 6 show the electrical schematic diagrams of the double-diffused metal oxide semiconductor device according to the present invention corresponding to Figure 2.
根據第4圖所示，本發明之雙擴散金屬氧化物半導體元件200在相同的崩潰防護電壓的條件下，相較於先前技術，其導通電阻明顯下降。而本發明之雙擴散金屬氧化物半導體元件200在相同的導通電阻的條件下，相較於先前技術，其崩潰防護電壓明顯有被提高。藉此，可知本發明之雙擴散金屬氧化物半導體元件200於不導通操作時，在提高其元件崩潰防護電壓的同時，亦能夠於導通操作時降低其導通電阻。As shown in FIG. 4, under the condition of the same breakdown protection voltage, the double diffusion metal oxide semiconductor device 200 of the present invention has a significantly reduced on-resistance compared with the prior art. Compared with the prior art, the double-diffused metal oxide semiconductor device 200 of the present invention has a significantly higher breakdown protection voltage than the prior art. Therefore, it can be known that the double-diffused metal oxide semiconductor device 200 of the present invention can increase its element breakdown protection voltage during non-conduction operation, and can also reduce its on-resistance during on-operation.
第5圖顯示根據先前技術與本發明之崩潰防護電壓之示意圖。根據第5圖所示，本發明之雙擴散金屬氧化物半導體元件200，相較於先前技術，其崩潰防護電壓明顯有被提高。又，第6圖顯示根據先前技術與本發明之導通操作之示意圖。根據第6圖所示，本發明之雙擴散金屬氧化物半導體元件200，相較於先前技術，其於導通操作時的汲極電流，高於先前技術。意即，本發明之雙擴散金屬氧化物半導體元件200在提高其元件崩潰防護電壓的同時，亦能夠降低其導通電阻。FIG. 5 is a schematic diagram of a crash protection voltage according to the prior art and the present invention. As shown in FIG. 5, compared with the prior art, the double-diffused metal oxide semiconductor device 200 of the present invention has a significantly increased breakdown protection voltage. In addition, FIG. 6 is a schematic diagram showing a conduction operation according to the prior art and the present invention. As shown in FIG. 6, compared with the prior art, the double-diffused metal oxide semiconductor device 200 of the present invention has a higher drain current during the conducting operation than the prior art. In other words, the double-diffused metal oxide semiconductor device 200 of the present invention can reduce the on-resistance of the device while increasing the protection voltage of its breakdown.
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如深井區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術。凡此種種，皆可根據本發明的教示類推而得。此外，所說明之各個實施例，並不限於單獨應用，亦可以組合應用，例如但不限於將兩實施例併用。因此，本發明的範圍應涵蓋上述及其他所有等效變化。此外，本發明的任一實施型態不必須達成所有的目的或優點，因此，請求專利範圍任一項也不應以此為限。The present invention has been described above with reference to the preferred embodiments, but the above is only for making those skilled in the art easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. In the same spirit of the invention, those skilled in the art can think of various equivalent changes. For example, without affecting the main characteristics of the component, other process steps or structures can be added, such as deep wells, etc .; for example, the lithography technology is not limited to photomask technology, and can also include electron beam lithography technology. All these can be deduced by analogy according to the teachings of the present invention. In addition, each of the embodiments described is not limited to being applied alone, and can also be applied in combination, such as, but not limited to, combining the two embodiments. Therefore, the scope of the invention should cover the above and all other equivalent variations. In addition, any embodiment of the present invention does not have to achieve all the objectives or advantages. Therefore, any one of the scope of the claimed patent should not be limited to this.
100‧‧‧習知雙擴散金屬氧化物半導體元件100‧‧‧Conventional double-diffused metal oxide semiconductor device
200‧‧‧雙擴散金屬氧化物半導體元件200‧‧‧Double-diffused metal oxide semiconductor device
11、21‧‧‧閘極11, 21‧‧‧Gate
13、23f、23r‧‧‧絕緣結構13, 23f, 23r‧‧‧ Insulation structure
13a、23a‧‧‧元件區13a, 23a ‧‧‧ component area
14、24‧‧‧場氧化區14, 24‧‧‧field oxidation zone
15、25‧‧‧高壓井區15, 25‧‧‧High-pressure well area
16、26‧‧‧本體區16, 26‧‧‧ body area
16a、26a‧‧‧接點區16a, 26a‧‧‧ contact area
18、28‧‧‧源極18, 28‧‧‧ source
19、29‧‧‧汲極19, 29‧‧‧ Drain
17、27‧‧‧基板17, 27‧‧‧ substrate
21a‧‧‧上表面21a‧‧‧upper surface
21b‧‧‧下表面21b‧‧‧ lower surface
22‧‧‧磊晶層22‧‧‧Epitaxial layer
22a‧‧‧磊晶層表面22a‧‧‧Epitaxial layer surface
26b、28a‧‧‧光阻層26b, 28a‧‧‧Photoresistive layer
41‧‧‧埋區41‧‧‧Buried area
42‧‧‧漂移埋區42‧‧‧ Drift buried area
B1、B2‧‧‧邊界B1, B2‧‧‧ border
C1、C2‧‧‧邊界C1, C2‧‧‧ border
JN‧‧‧通道方向接面JN‧‧‧ aisle interface
M1、M2‧‧‧邊界M1, M2‧‧‧ border
N1、N2、N3‧‧‧邊界N1, N2, N3‧‧‧ boundaries
H1、H2‧‧‧深度H1, H2‧‧‧ depth
L1‧‧‧區域L1‧‧‧ area
L2‧‧‧區域L2‧‧‧ area
P‧‧‧區域P‧‧‧Area
PN0‧‧‧PN接面PN0‧‧‧PN interface
PN1‧‧‧PN接面PN1‧‧‧PN interface
PN2‧‧‧PN接面PN2‧‧‧PN interface
W29‧‧‧長度W29‧‧‧ length
W41‧‧‧長度W41‧‧‧ length
W42‧‧‧長度W42‧‧‧ length
第1圖顯示先前技術之N型雙擴散金屬氧化物半導體元件之剖視圖。 第2圖顯示本發明之雙擴散金屬氧化物半導體元件的一實施例之剖視圖。 第3A~3G圖顯示本發明之雙擴散金屬氧化物半導體元件製造方法的一實施例。 第4~6圖示出，對應於第2圖，本發明之雙擴散金屬氧化物半導體元件的電性示意圖。FIG. 1 shows a cross-sectional view of a conventional N-type double-diffused metal oxide semiconductor device. FIG. 2 shows a cross-sectional view of an embodiment of a double-diffused metal oxide semiconductor device according to the present invention. 3A to 3G show an embodiment of a method for manufacturing a double-diffused metal oxide semiconductor device according to the present invention. Figures 4 to 6 show the electrical schematic diagrams of the double-diffused metal oxide semiconductor device according to the present invention corresponding to Figure 2.
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| CN201766079U (en) * | 2010-06-11 | 2011-03-16 | 东南大学 | Silicon carbide high-voltage N-type metal oxide semiconductor tube with floating buried layer |
| US9269806B2 (en) * | 2013-10-03 | 2016-02-23 | Macronix International Co., Ltd. | Semiconductor device and method of fabricating same |
| CN104659090B (en) * | 2013-11-18 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | LDMOS device and manufacture method |
| CN104681621B (en) * | 2015-02-15 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | A kind of source electrode raises high-voltage LDMOS and its manufacture method that voltage is used |
-
2017
- 2017-01-16 TW TW106101340A patent/TWI624065B/en active
- 2017-01-23 CN CN201710062427.8A patent/CN107871782B/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491941A (en) * | 2018-05-15 | 2019-11-22 | 立锜科技股份有限公司 | High voltage device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107871782B (en) | 2020-06-30 |
| CN107871782A (en) | 2018-04-03 |
| TWI624065B (en) | 2018-05-11 |
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