TWI608546B - Lateral double diffused metal oxide semiconductor device and manufacturing method thereof - Google Patents

Description

Lateral double-diffused metal oxide semiconductor device and method of manufacturing same

The present invention relates to a lateral double diffused metal oxide semiconductor (LDMOS) device and a method of fabricating the same, and more particularly to an LDMOS device capable of reducing on-resistance and a method of fabricating the same.

1 shows a schematic cross-sectional view of a conventional lateral double diffused metal oxide semiconductor (LDMOS) device 100. As shown in FIG. 1, the LDMOS device 100 includes a P-type substrate 101, a drift region 102, an isolation oxide region 103, a drift oxide region 104, a body region 106, a drain 110, a source 108, and a gate 111. The conductive region of the drift region 102 is N-type, formed on the P-type substrate 101, and the isolation oxide region 103 is a local oxidation of silicon (LOCOS) structure to define the operation region 103a as the main operation of the LDMOS device 100. The scope of action. The range of the operation area 103a is indicated by a thick black arrow in Fig. 1. The gate 111 covers a portion of the drift oxidized region 104. This conventional LDMOS device 100 can be used as a power component, but thus sacrifices on-resistance, limiting the speed of operation, and the performance of the component.

In view of the above, the present invention has been directed to an improvement of the prior art described above, and provides an LDMOS device and a method of fabricating the same, an LDMOS device capable of reducing on-resistance, and a method of fabricating the same.

In one aspect, the present invention provides a Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) device comprising: a P-type substrate having a relatively upper surface and a lower surface in a height direction a first epitaxial layer formed on the P-type substrate and stacked and connected to the upper surface in the height direction; a second epitaxial layer formed on the first epitaxial layer And being stacked and connected to the first epitaxial layer in the height direction; a P-type buried layer (PBL) is formed in the first epitaxial layer and the second epitaxial layer And the PBL is stacked and connected to the upper surface in the height direction, and includes a junction between the first epitaxial layer and the second epitaxial layer; a P-type high-voltage well region is formed in the second And on the PBL in the epitaxial layer, and stacked and connected to the PBL in the height direction; a P-type body region, at least a portion of the P-type body region is formed in the P-type high voltage in the second epitaxial layer On the well area, and in the height direction, stacked and connected to the P-type high-pressure well area; a well region formed in the second epitaxial layer and adjacent to the P-type body region in a lateral direction; an isolation oxide region formed on the second epitaxial layer to define an operation region; a drift An oxidation region is formed in the operation region on the second epitaxial layer, and in the height direction, the drift oxidation region is stacked and connected to the N-type well region; and a gate is formed in the second epitaxial region a layer, and the gate is located in the operation region and covers at least a portion of the drift oxidation region, and in the height direction, the gate is stacked and connected to the second epitaxial layer and covers part of the N-type well region and a portion of the P-type body region; an N-type contact region formed in the P-type body region; a P-type contact region formed in the P-type body region, and the N-type contact in the lateral direction Adjacent to the region; an upper source is formed on the second epitaxial layer, and is stacked and connected to the N-type contact region and the P-type contact region in the height direction; a lower source is formed in the region a lower surface of the P-type substrate, and stacked and connected to the lower surface in the height direction; and an N-type drain formed thereon In the N-type well region, the N-type drain is interposed between the drift oxidation region and the isolation oxidation region; wherein, in a normal operation, an on-current flows from the N-type drain through the lower source.

In another aspect, the present invention provides a method for fabricating a lateral double-diffused metal oxide semiconductor (LDMOS) device, comprising: providing a P-type substrate having a relative height in a height direction An upper surface and a lower surface; forming a first epitaxial layer on the P-type substrate, and stacking and connecting on the upper surface in the height direction; forming a P-type buried layer (P-type buried layer, a PBL) ion implantation layer in the first epitaxial layer; forming a second epitaxial layer on the first epitaxial layer, and stacked and connected to the first epitaxial layer in the height direction; Processing the PBL ion implantation layer by a thermal process to form a P-type buried layer (PBL) in the first epitaxial layer and the second epitaxial layer, and the PBL is at the height Oriented, stacked and connected to the upper surface, and including a junction between the first epitaxial layer and the second epitaxial layer; forming a P-type high voltage well region on the PBL in the second epitaxial layer And in the height direction, stacked and connected to the PBL; forming a P-type body region, At least a portion of the P-type body region is located on the P-type high-pressure well region in the second epitaxial layer, and is stacked and connected to the P-type high-pressure well region in the height direction; forming an N-type well region In the second epitaxial layer, adjacent to the P-type body region in a lateral direction; forming an isolation oxide region on the second epitaxial layer to define an operation region; forming a drift oxidation region in the second protrusion In the operation region on the crystal layer, and in the height direction, the drift oxidation region is stacked and connected to the N-type well region; a gate is formed on the second epitaxial layer, and the gate is located in the operation And covering at least a portion of the drift oxidation region, and in the height direction, the gate is stacked and connected to the second epitaxial layer and covers part of the N-type well region and a portion of the P-type body region; forming a N a contact region is formed in the P-type body region; a P-type contact region is formed in the P-type body region, and is adjacent to the N-type contact region in the lateral direction; forming an N-type drain on the N In the well region, and the N-type drain is interposed between the drift oxidation region and the isolation oxidation region; forming an upper source and the second epitaxy On and in the height direction, are stacked and connected to the N-type junction region and the P-type junction region; and shaped Forming a source below the lower surface of the P-type substrate and stacking and connecting the lower surface in the height direction; wherein, in a normal operation, an on current flows through the N-type drain The lower source.

In one preferred embodiment, the isolation oxide region and the drift oxidation region are a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure.

In a preferred embodiment, the conduction current flows through the N-type well region, the P-type body region, the N-type contact region, the upper source, and the P through the N-type drain. a contact region, the P-type body region, the P-type high voltage well region, the PBL, the P-type substrate, and the lower source.

In a preferred embodiment, the upper source includes a metal layer or a deuterated metal layer.

In a preferred embodiment, the lower source comprises a metal layer or a deuterated metal layer.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

100,200,300‧‧‧LDMOS components

101,201‧‧‧P type substrate

102‧‧‧ drift zone

103,203,303‧‧‧Isolation Oxidation Zone

103a, 203a‧‧‧Operating area

104,204‧‧‧Drag oxidation zone

106,206‧‧‧P type body area

108‧‧‧ source

110,210‧‧‧汲polar

111,211‧‧‧ gate

201a‧‧‧ upper surface

201b‧‧‧ lower surface

202a‧‧‧First epitaxial layer

202b‧‧‧Second epilayer

205‧‧‧P type high pressure well area

207‧‧‧N type well area

208‧‧‧N type contact area

209‧‧‧P type contact area

212‧‧‧P-type buried layer (PBL)

212a‧‧‧Connected

212b‧‧‧PBL ion implantation layer

212c‧‧‧ photoresist layer

213‧‧‧Lower source

214‧‧‧Upper source

Figure 1 shows a conventional LDMOS device 100.

Fig. 2 shows a first embodiment of the present invention.

The 3A-3M diagram shows a second embodiment of the present invention.

Fig. 4 shows a third embodiment of the present invention.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Fig. 2 is a cross-sectional view showing a first embodiment of the present invention showing a Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) device 200 in accordance with the present invention. As shown in FIG. 2, the LDMOS device includes: a P-type substrate 201, a first epitaxial layer 202a, a second epitaxial layer 202b, an isolation oxide region 203, a drift oxide region 204, a P-type high voltage well region 205, and P. The main body region 206, the N-type well region 207, the N-type contact region 208, the P-type contact region 209, the N-type drain 210, the gate 211, and the P-type buried layer (PBL) 212, The lower source 213 and the upper source 214.

Among them, the P-type substrate 201 has a relatively upper surface 201a and a lower surface 201b in the height direction (the direction indicated by the thick black dotted arrow in the figure). The first epitaxial layer 202a is formed on the P-type substrate 201, and is stacked and connected to the upper surface 201a in the height direction. The second epitaxial layer 202b is formed on the first epitaxial layer 202a, and is stacked and connected to the first epitaxial layer 202a in the height direction. The PBL 212 is formed in the first epitaxial layer 202a and the second epitaxial layer 202b, and the PBL 212 is stacked and connected to the upper surface 201a in the height direction, and includes the first epitaxial layer 202a and the second epitaxial layer 202b. The junction 212a. A P-type high voltage well region 205 is formed on the PBL 212 in the second epitaxial layer 202b, and is stacked and connected to the PBL 212 in the height direction.

A portion of the P-type body region 206 is formed on the P-type high voltage well region 205 in the second epitaxial layer 202b, and is stacked and connected to the P-type high voltage well region 205 in the height direction. The N-type well region 207 is formed in the second epitaxial layer 202b and is adjacent to the P-type body region 206 in the lateral direction (the direction indicated by the thick black solid arrow in the figure). An isolation oxide region 203 is formed on the second epitaxial layer 202b to define an operation region 203a. The drift oxide region 204 is formed in the operation region 203a on the second epitaxial layer 202b, and in the height direction, the drift oxide region 204 is stacked and connected to the N-type well region 207. The gate 211 is formed on the second epitaxial layer 202b, and the gate 211 is located in the operation region 203a and covers at least a portion of the drift oxide region 204. In the height direction, the gate electrode 211 is stacked and connected to the second epitaxial layer. 202b and covers a portion of the N-type well region 207 and a portion of the P-type body region 206.

An N-type contact region 208 is formed in the P-type body region 206. A P-type contact region 209 is formed in the P-type body region 206 and is adjacent to the N-type contact region 208 in the lateral direction. The upper source 214 is formed on the second epitaxial layer 202b, and is stacked and connected to the N-type contact region 208 and the P-type contact region 209 in the height direction. The lower source electrode 213 is formed under the lower surface 201b of the P-type substrate 201, and is stacked and connected under the lower surface 201b in the height direction. The N-type drain 210 is formed in the N-type well region 207, and the N-type drain 210 is interposed between the drift oxide region 204 and the isolation oxide region 203. Wherein, in normal operation, the on current flows from the N-type drain 210 through the lower source 213, as indicated by the thick black solid arrow in FIG. 3M.

The 3A-3M diagram shows a second embodiment of the present invention. 3A-3M is a cross-sectional view showing a method of fabricating a Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) device 200 in accordance with the present invention. First, as shown in FIG. 3A, a P-type substrate 201 is provided. The P-type substrate 201 is, for example but not limited to, a P-type germanium substrate, and may be another semiconductor substrate. The P-type substrate 201 has a relatively upper surface 201a and a lower surface 201b in the height direction (the direction indicated by the thick black dotted arrow in the figure). Next, as shown in FIG. 3B, the first epitaxial layer 202a is formed on the P-type substrate 201, and is stacked and connected to the upper surface 201a in the height direction. The first epitaxial layer 202a is formed, for example but not limited to, a P-type epitaxial layer on the P-type substrate 201.

Next, as shown in FIGS. 3C and 3D, a P-type buried layer (PBL) ion implantation layer 212b is formed in the first epitaxial layer 202a. For example, but not limited to, forming a photoresist layer 212c as a mask by a lithography process to define the PBL 212, and using an ion implantation process, the P-type impurity is in the form of an accelerated ion, such as the thin dotted arrow in FIG. 3C. It is shown that the implanted defined regions are formed, and the PBL ion implantation layer 212b is formed in the first epitaxial layer 202a, and then the photoresist layer 212c is removed, as shown in FIG. 3D.

Next, as shown in FIG. 3E, a second epitaxial layer 202b is formed on the first epitaxial layer 202a, and is stacked and connected to the first epitaxial layer 202a in the height direction. Next, as shown in FIG. 3F, the PBL ion implantation layer 212b is processed by a thermal process to form a P-type buried layer (PBL) 212 on the first epitaxial layer 202a and the second epitaxial layer. In layer 202b, and PBL 212 is stacked and connected in the height direction The upper surface 201a includes a junction 212a between the first epitaxial layer 202a and the second epitaxial layer 202b. The epitaxial process of forming the second epitaxial layer 202b does not have to be a separate process step, and may also be combined in the epitaxial process.

Next, as shown in FIG. 3G, a P-type high voltage well region 205 is formed on the PBL 212 in the second epitaxial layer 202b, and is stacked and connected to the PBL 212 in the height direction. The method of forming the P-type high voltage well region 205 is, for example, but not limited to, formed by a lithography process, an ion implantation process, and a thermal process. Next, as shown in FIG. 3H, a P-type body region 206 is formed, wherein at least a portion of the P-type body region 206 is located on the P-type high-voltage well region 205 in the second epitaxial layer 202b, and stacked in the height direction. Connected to a P-type high pressure well region 205.

Next, as shown in FIG. 3I, an N-type well region 207 is formed in the second epitaxial layer 202b, and is adjacent to the P-type body region in the lateral direction (the direction indicated by the thick black solid arrow in the figure). 206. Next, as shown in FIG. 3J, an isolation oxide region 203 is formed on the second epitaxial layer 202b to define the operation region 203a; and at the same time or subsequently, the operation region 203a of the drift oxidation region 204 on the second epitaxial layer 202b is formed. The drift oxidation zone 203 is stacked and connected to the N-type well region 204 in the height direction. The isolation oxide region 203 and the drift oxide region 204 are a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure as shown.

Next, as shown in FIG. 3K, a gate 211 is formed on the second epitaxial layer 202b, and the gate 211 is located in the operation region 203a and covers at least a portion of the drift oxide region 204, and in the height direction, the gate The 211 is stacked and connected to the second epitaxial layer 202b and covers a portion of the N-type well region 207 and a portion of the P-type body region 206. Next, as shown in FIG. 3L, an N-type contact region 208 is formed in the P-type body region 206; a P-type contact region 209 is formed in the P-type body region 206, and is laterally connected to the N-type contact region. 208 abuts; an N-type drain 210 is formed in the N-well region 207, and an N-type drain 210 is interposed between the drift oxide region 204 and the isolation oxide region 203. The N-type contact region 208 and the N-type drain electrode 210 can be formed, for example, by the same lithography process and ion implantation process.

Next, as shown in FIG. 3M, the upper source 214 is formed on the second epitaxial layer 202b, and is stacked and connected in the height direction to the N-type contact region 208 and the P-type contact region 209; The lower source 213 is under the lower surface 201a of the P-type substrate 201, and is stacked and connected under the lower surface 201a in the height direction. It should be noted that in the normal operation of the LDMOS device 200, the on-current flows through the N-type well region 207, the P-type body region 206, the N-type contact region 208, and the upper source 214, for example, by the N-type drain 210. P-type contact region 209, P-type body region 206, P-type high voltage well region 205, PBL 212, P-type substrate 201, and lower source electrode 213. The upper source 214 and the lower source 213 include, for example, a metal layer or a deuterated metal layer. Wherein, the conduction current flows from the N-type well region 207 to the P-type body region 206, which means that a positive voltage is applied to the gate electrode 211, and a channel is formed at the junction between the P-type body region 206 and the gate electrode 211. During the conducting operation, the on current flows from the N-well region 207 to the P-type body region 206, which is well known to those of ordinary skill in the art and will not be described herein.

Fig. 4 shows a third embodiment of the present invention. This embodiment shows a schematic cross-sectional view of an LDMOS device 300 in accordance with the present invention. This embodiment is intended to explain the manner in which the isolation oxide region 303 is formed in accordance with the present invention, and is not limited to that shown in the first embodiment. This embodiment is different from the first embodiment in that, as shown in FIG. 4, the isolation oxide region 303 is a shallow trench isolation (STI) structure instead of being isolated and oxidized as in the first embodiment. The region 203 is a local oxidation of silicon (LOCOS) structure. The other processes are the same as in the first embodiment, and the LDMOS device 300 as shown in Fig. 4 is formed. Of course, according to the present invention, the drift oxidized region 204 is also not limited to a LOCOS structure, but may be an STI structure.

It should be noted that the present invention differs from the prior art in many features, including the normal operation, in the LDMOS device 200 according to the present invention, the resistance of the series in the conduction operation includes electrically connecting from the upper source 214 to the lower The serial path of the source 213 can be relatively low. The peak of the P-type impurity concentration of the high-pressure P-type well region 205 is not distributed on the upper surface of the second epitaxial layer 202b. In addition, the PBL 212 can be formed in the first epitaxial layer 202a and the second epitaxial layer 202b by the two epitaxial layers, that is, the first epitaxial layer 202a and the second epitaxial layer 202b, and the PBL 212 in the height direction, including the first epitaxial A junction 212a between the layer 212a and the second epitaxial layer 202b. In addition, according to the LDMOS device 200 of the present invention, the lower source 213 is located under the lower surface 201b, so that the LDMOS device 200 of the present invention can be placed under the lower surface 201b and connected in series with another power device, such as the drain of another power device. Can improve the efficiency of heat dissipation.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as a threshold voltage adjustment region, may be added without affecting the main characteristics of the component; for example, the lithography technique is not limited to the reticle technology, and may also include electron beam lithography; The conductive type P type and the N type can be interchanged, and only other areas need to be interchanged. The above and other equivalent variations are intended to be covered by the scope of the invention.

200‧‧‧LDMOS components

201‧‧‧P type substrate

201a‧‧‧ upper surface

201b‧‧‧ lower surface

202a‧‧‧First epitaxial layer

202b‧‧‧Second epilayer

203‧‧‧Isolated Oxidation Zone

203a‧‧‧Operating area

204‧‧‧ Drift oxidation zone

205‧‧‧P type high pressure well area

206‧‧‧P type body area

207‧‧‧N type well area

208‧‧‧N type contact area

209‧‧‧P type contact area

210‧‧‧汲polar

211‧‧‧ gate

212‧‧‧P-type buried layer (PBL)

212a‧‧‧Connected

213‧‧‧Lower source

214‧‧‧Upper source

Claims (10)

A Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) device comprising: a P-type substrate having a relatively upper surface and a lower surface in a height direction; a first epitaxial layer, Formed on the P-type substrate, and stacked and connected to the upper surface in the height direction; a second epitaxial layer is formed on the first epitaxial layer, and stacked in the height direction Connected to the first epitaxial layer; a P-type buried layer (PBL) is formed in the first epitaxial layer and the second epitaxial layer, and the PBL is in the height direction And stacked on the upper surface and including a junction between the first epitaxial layer and the second epitaxial layer; a P-type high voltage well region formed on the PBL in the second epitaxial layer, And in the height direction, stacked and connected to the PBL; a P-type body region, at least a portion of the P-type body region is formed on the P-type high-voltage well region in the second epitaxial layer, and in the height direction Upper, stacked and connected to the P-type high-pressure well region; an N-type well region formed on the second epitaxial layer a layer adjacent to the P-type body region in a lateral direction; an isolation oxide region formed on the second epitaxial layer to define an operation region; and a drift oxidation region formed on the second epitaxial layer In the operation area, and in the height direction, the drift oxidation region is stacked and connected to the N-type well region; a gate is formed on the second epitaxial layer, and the gate is located in the operation region And covering at least part of the drift oxidation region, and in the height direction, the gate is stacked and connected to the second epitaxial layer and covers part of the N-type well region and a portion of the P-type body region; a dot region formed in the P-type body region; a P-type contact region formed in the P-type body region and adjacent to the N-type contact region in the lateral direction; an upper source formed in the And on the second epitaxial layer, and in the height direction, stacked and connected to the N-type contact region and the P-type contact region; a source, formed under the lower surface of the P-type substrate, and stacked and connected under the lower surface in the height direction; and an N-type drain formed in the N-type well region, and the An N-type drain is interposed between the drift oxidation region and the isolation oxide region; wherein, in a normal operation, an on-current flows from the N-type drain through the lower source. The lateral double-diffused metal oxide semiconductor device according to claim 1, wherein the isolation oxide region and the drift oxidation region are local oxidation of silicon (LOCOS) structures or shallow trench isolation. , STI) structure. The lateral double-diffused metal oxide semiconductor device according to claim 1, wherein the conduction current flows through the N-type well region, the P-type body region, and the N-type contact sequentially by the N-type drain a region, the upper source, the P-type contact region, the P-type body region, the P-type high voltage well region, the PBL, the P-type substrate, and the lower source. The lateral double-diffused metal oxide semiconductor device of claim 1, wherein the upper source comprises a metal layer or a deuterated metal layer. The lateral double-diffused metal oxide semiconductor device of claim 1, wherein the lower source comprises a metal layer or a deuterated metal layer. A method for manufacturing a lateral double-diffused metal oxide semiconductor (LDMOS) device, comprising: providing a P-type substrate having a relative upper surface and a lower surface in a height direction; forming a first An epitaxial layer is deposited on the P-type substrate and stacked on the upper surface in the height direction; a P-type buried layer (PBL) ion implantation layer is formed on the first surface Forming a second epitaxial layer on the first epitaxial layer, and stacking and connecting to the first epitaxial layer in the height direction; Processing the PBL ion implantation layer by a thermal process to form a P-type buried layer (PBL) in the first epitaxial layer and the second epitaxial layer, and the PBL is at the height Oriented, stacked and connected to the upper surface, and including a junction between the first epitaxial layer and the second epitaxial layer; forming a P-type high voltage well region on the PBL in the second epitaxial layer And in the height direction, stacked and connected to the PBL; forming a P-type body region, wherein at least a portion of the P-type body region is located on the P-type high-voltage well region in the second epitaxial layer, and In the height direction, stacked and connected to the P-type high-pressure well region; forming an N-type well region in the second epitaxial layer and adjacent to the P-type body region in a lateral direction; forming an isolation oxidation region in the Forming an operation region on the second epitaxial layer; forming a drift oxidation region in the operation region on the second epitaxial layer, and in the height direction, the drift oxidation region is stacked and connected to the N-type a well region; forming a gate on the second epitaxial layer, and the gate is located in the operation region and covering at least part of the drift oxidation And in the height direction, the gate is stacked and connected to the second epitaxial layer and covers part of the N-type well region and a portion of the P-type body region; forming an N-type contact region in the P-type body region Forming a P-type contact region in the P-type body region and adjoining the N-type contact region in the lateral direction; forming an N-type drain in the N-type well region, and the N-type germanium Between the drift oxidation region and the isolation oxidation region; forming an upper source on the second epitaxial layer, and stacking and connecting to the N-type contact region and the P-type in the height direction a contact region; and a lower source is formed under the lower surface of the P-type substrate, and is stacked and connected to the lower surface in the height direction; wherein, in a normal operation, an on current is caused by the N The type of drain flows through the lower source. The method of manufacturing a lateral double-diffused metal oxide semiconductor device according to claim 6, wherein the isolation oxide region and the drift oxidation region are local oxidation of silicon (LOCOS) structures or shallow trench insulation (shallow Trench isolation, STI) structure. A lateral double-diffused metal oxide semiconductor device as described in claim 6 The manufacturing method, wherein the conduction current flows through the N-type well region, the P-type body region, the N-type contact region, the upper source, the P-type contact region, and the P through the N-type drain a body body region, the P-type high voltage well region, the PBL, the P-type substrate, and the lower source. The method of manufacturing a lateral double-diffused metal oxide semiconductor device according to claim 6, wherein the upper source comprises a metal layer or a deuterated metal layer. The method of manufacturing a lateral double-diffused metal oxide semiconductor device according to claim 6, wherein the lower source comprises a metal layer or a deuterated metal layer.