CN102610641A - High-voltage LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof - Google Patents
High-voltage LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a high-voltage LDMOS (laterally diffused metal oxide semiconductor) device. A special-shaped doped ring surrounding the lead-out end of a heavily-doped drain region is led to the drain end of a common high-voltage LDMOS device; and the drift region, body region and source end of the original LDMOS device form a parasitic SCR (silicon controlled rectifier) device through the special-shaped doped ring. On one hand, the current distribution after the LDMOS is turned on can reduce the turn-on voltage of the parasitic SCR device; and on the other hand, after the parasitic SCR device is turned on, the specific on-resistance of the whole device can be reduced due to the high electric conductivity of the SCR. The high-voltage LDMOS device disclosed by the invention is actually a composite device structure of a common LDMOS device and an SCR device, which sufficiently utilizes the advantages of the LDMOS device and the SCR device, realizes high reverse breakdown voltage and reduces the specific on-resistance of the device under a certain working bias condition.
Description
Technical field
The present invention relates to a kind of high-voltage LDMOS (Laterally Diffused Metal OxideSemiconductor, LDMOS) device.
Background technology
As far as high-voltage LDMOS device, puncture voltage (Breakdowm Voltage, BV) and conduction resistance (on-resistance Rsp) is a pair of very important technical indicator that needs balance.Withstand voltage and the conduction resistance of high pressure DMOS device depends on the compromise selection of doping content, thickness and the drift region length of epitaxial loayer.High puncture voltage requires thick light dope epitaxial loayer and long drift region; Low conduction resistance then requires heavy doping epitaxial loayer that approaches and the drift region of lacking; Therefore must select best extension parameter and drift region length; So that under the prerequisite that satisfies certain source drain breakdown voltage, obtain minimum conduction resistance.
And for SCR (Silicon Controlled Rectifiers, silicon controlled rectifier) device, because the characteristic of negative differential resistance under the specified conditions;, device has very strong conductive capability after opening; Conduction resistance is less, and is higher but its device is opened required voltage, difficult with open-minded.
Summary of the invention
Technical problem to be solved by this invention provides a kind of high-voltage LDMOS device that has high-breakdown-voltage and low conduction resistance simultaneously.For this reason, the present invention also will provide the manufacturing approach of said high-voltage LDMOS device.
For solving the problems of the technologies described above, the structure of high-voltage LDMOS device of the present invention is: in low-doped substrate, have drift region and tagma, the doping type and the substrate of drift region are opposite, and the doping type in tagma is identical with substrate; Have the drift region inversion layer on the surface of drift region, the doping type and the drift region of drift region inversion layer are opposite; Has isolation structure one on the surface in tagma; Have isolation structure two on the surface of drift region, isolation structure two is also on the inversion layer of drift region; Also have isolation structure three and isolation structure four on the surface of drift region; On tagma and isolation structure two, have polysilicon gate and polysilicon field plate; One end of polysilicon gate is on the tagma, and the other end is on isolation structure two; The polysilicon field plate is on isolation structure two; Among the tagma, have body electrode leads to client and source region exit, the body electrode leads to client is between isolation structure one and source region exit, and doping type is opposite with the source region exit; The source region exit is between body electrode leads to client and polysilicon gate, and doping type and tagma are opposite; Among the drift region, have drain region exit and transoid doping ring, the doping type of drain region exit is identical with the doping type of drift region, and the doping type of transoid doping ring is opposite with the drain region exit; Said transoid mix ring from depression angle be rendered as annular round the drain region exit, then be rendered as the structure of two sections spaces from analysing and observe angle, a segment structure wherein is between isolation structure two and isolation structure three; Drain region exit 10 is between isolation structure three and isolation structure four; Source electrode, grid and drain electrode are metal electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate simultaneously, transoid is mixed and encircled and the drain region exit.
The method of making above-mentioned high-voltage LDMOS device comprises the steps:
The 1st step, on low-doped substrate, adopt photoetching process and ion implantation technology to form the drift region, the doping type and the substrate of drift region are opposite;
The 2nd step, on low-doped substrate, adopt photoetching process and ion implantation technology to form the tagma, the doping type in tagma is identical with substrate;
The 3rd step, on the drift region, adopt photoetching process and ion implantation technology to form the drift region inversion layer, the doping type and the drift region of drift region inversion layer are opposite;
The 4th step formed a plurality of isolation structures at silicon chip surface, and wherein isolation structure one is on the surface in tagma, and isolation structure two is on the surface of drift region and on the inversion layer of drift region, and isolation structure three, isolation structure four are all on the surface of drift region;
The 5th step, at the first growth one deck gate oxide of silicon chip surface, deposit one deck polysilicon again, thereby this layer of etching polysilicon and gate oxide formation polysilicon gate and drain terminal polysilicon field plate; One end of polysilicon gate is on the tagma, and the other end is on isolation structure two; Drain terminal polysilicon field plate is then on isolation structure two;
The 6th step, carry out heavy doping ion injection formation source region exit and drain region exit in tagma and drift region, the type that ion injects is identical with the type of drift region; The source region exit is among the tagma and near an end of polysilicon gate; The drain region exit is among the drift region and between isolation structure three and isolation structure four;
In the 7th step, carry out injecting organizator electrode leads to client and center on the annular doping district of drain region exit in tagma and drift region with source electrode, ion that the drain electrode doping type is opposite; The body electrode leads to client is among the tagma and between isolation structure one and source region exit; The annular doping district claims transoid mix ring or special shaped doped ring again, and the exit among the drift region and round the drain region is observed from depression angle and to be presented annular, then is rendered as the structure of two sections spaces from analysing and observe angle; Wherein a segment structure in annular doping district is between isolation structure two and isolation structure three, and the drain region exit is between isolation structure three and isolation structure four;
In the 8th step, first deposition of dielectric layer etches contact hole then, and in contact hole, fills metal electrode, forms resulting devices; Metal electrode comprises source electrode, grid and drain electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate simultaneously, transoid is mixed and encircled and the drain region exit.
Perhaps, the structure of high-voltage LDMOS device of the present invention is: in low-doped substrate, have drift region and tagma, the doping type and the substrate of drift region are opposite, and the doping type in tagma is identical with substrate; Have the drift region inversion layer on the surface of drift region, the doping type and the drift region of drift region inversion layer are opposite; Has isolation structure one on the surface in tagma; Have isolation structure two on the surface of drift region, isolation structure two is also on the inversion layer of drift region; Surface in the drift region also has isolation structure three; On tagma and isolation structure two, have polysilicon gate and polysilicon field plate; One end of polysilicon gate is on the tagma, and the other end is on isolation structure two; The polysilicon field plate is on isolation structure two; Among the tagma, have body electrode leads to client and source region exit, the body electrode leads to client is between isolation structure one and source region exit, and doping type is identical with the tagma; The source region exit is between body electrode leads to client and polysilicon gate, and doping type and tagma are opposite; Among the drift region, have drain region exit and transoid doping ring, the doping type of drain region exit is identical with the doping type of drift region, and the doping type of transoid doping ring is opposite with the drain region exit; Said transoid mix ring from depression angle be rendered as annular round the drain region exit, then be rendered as the structure of two sections spaces from analysing and observe angle, a segment structure wherein is between isolation structure two and drain region exit; The drain region exit mixes between ring and isolation structure three c in transoid; Source electrode, grid and drain electrode are metal electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate simultaneously, transoid is mixed and encircled and the drain region exit.
The method of making above-mentioned high-voltage LDMOS device comprises the steps:
The 1st step, on low-doped substrate, adopt photoetching process and ion implantation technology to form the drift region, the doping type and the substrate of drift region are opposite;
The 2nd step, on low-doped substrate, adopt photoetching process and ion implantation technology to form the tagma, the doping type in tagma is identical with substrate;
The 3rd step, on the drift region, adopt photoetching process and ion implantation technology to form the drift region inversion layer, the doping type and the drift region of drift region inversion layer are opposite;
The 4th step formed a plurality of isolation structures at silicon chip surface, and wherein isolation structure one is on the surface in tagma, and isolation structure two is the surperficial of drift region and on the inversion layer of drift region, isolation structure three is on the surface of drift region;
The 5th step, at the first growth one deck gate oxide of silicon chip surface, deposit one deck polysilicon again, thereby this layer of etching polysilicon and gate oxide formation polysilicon gate and drain terminal polysilicon field plate; One end of polysilicon gate is on the tagma, and the other end is on isolation structure two; Drain terminal polysilicon field plate is then on isolation structure two;
The 6th step, carry out heavy doping ion injection formation source region exit and drain region exit in tagma and drift region, the type that ion injects is identical with the drift region; The source region exit is among the tagma and near an end of polysilicon gate; The drain region exit is among the drift region and between isolation structure two and isolation structure three;
In the 7th step, carry out injecting organizator electrode leads to client and center on the annular doping district of drain region exit in tagma and drift region with source electrode, ion that the drain electrode doping type is opposite; The body electrode leads to client is among the tagma and between isolation structure one and source region exit; The annular doping district claims transoid doping ring or special shaped doped ring again; The exit among the drift region and round the drain region; Present annular from the depression angle observation; Then be rendered as the structure of two sections spaces from analysing and observe angle, wherein a segment structure is between isolation structure two and drain region exit, and the drain region exit is between annular doping district and isolation structure three;
In the 8th step, first deposition of dielectric layer etches contact hole then, and in contact hole, fills metal electrode, forms resulting devices; Metal electrode comprises source electrode, grid and drain electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate simultaneously, transoid is mixed and encircled and the drain region exit.
High-voltage LDMOS device of the present invention is introduced the special shaped doped ring around highly doped drain region exit at the drain terminal of common high-voltage LDMOS device, and this special shaped doped ring will form parasitic SCR device with drift region, tagma and the source end of former LDMOS device.On the one hand, the CURRENT DISTRIBUTION after the LDMOS conducting can reduce the turning-on voltage of parasitic SCR device.On the other hand, after this parasitic SCR device is opened, because the high conductive capability of SCR can reduce the conducting resistance of entire device.Like this; High-voltage LDMOS device of the present invention is actually the multiple device structure of common LDMOS device and SCR device; Make full use of LDMOS and SCR device advantage separately, be implemented in when satisfying high reverse breakdown voltage, under certain working bias voltage condition, reduced the conducting resistance of device.
Description of drawings
Fig. 1 is the profile of an embodiment of high-voltage LDMOS device of the present invention;
Fig. 2 is the profile of another embodiment of high-voltage LDMOS device of the present invention;
Fig. 3 is the I-V characteristic curve of high-voltage LDMOS device of the present invention and traditional LDMOS device;
Fig. 4 a～Fig. 4 h is each step sketch map of manufacturing approach of high-voltage LDMOS device of the present invention.
Description of reference numerals among the figure:
1 is source electrode; 2 is grid; 3 are drain electrode; 4 is the body electrode leads to client; 5 is the source region exit; 6 is the tagma; 7 is the drift region surface inversion layer; 8 is the drift region; 9 is low-doped substrate; 10 is the drain region exit; 11 is isolation structure; 12 is dielectric substance layer; 13 are drain terminal transoid doping ring.
Embodiment
See also Fig. 1, this is an embodiment of high-voltage LDMOS device of the present invention.Have deep high voltage well 8 and low pressure trap 6 in the low-doped substrate 9.The doping type of deep high voltage well 8 is opposite with substrate 9, as the drift region.The doping type of low pressure trap 6 is identical with substrate 9, as the tagma.8 surface has trap 7 in the drift region, and the doping type of trap 7 is opposite with drift region 8, as the drift region inversion layer.6 surface has isolation structure one 11a in the tagma.8 surface has isolation structure two 11b in the drift region, and isolation structure 11b is also on drift region inversion layer 7.8 surface also has isolation structure three 11c and isolation structure four 11d in the drift region, and isolation structure three 11c and isolation structure four 11d are not all on drift region inversion layer 7.On tagma 6 and isolation structure two 11b, have polysilicon gate 20a and polysilicon field plate 20b.The end of polysilicon gate 20a is on tagma 6, and the other end is on isolation structure two 11b.Polysilicon field plate 20b is on isolation structure two 11b.Among tagma 6, have body electrode leads to client 4 and source region exit 5.Body electrode leads to client 4 is between isolation structure one 11a and source region exit 5, and doping type is opposite with source region exit 5.Source region exit 5 is between body electrode leads to client 4 and polysilicon gate 20a, and its doping type is opposite with tagma 6.Among drift region 8, have drain region exit 10 and transoid doping ring 13.The doping type of drain region exit 10 is identical with drift region 8, and the doping type of transoid doping ring 13 is opposite with drain region exit 10.Wherein transoid mix ring 13 from depression angle be rendered as annular round the drain region exit 10.Transoid is mixed and is encircled 13 structures that are rendered as two sections spaces from cutaway view; A segment structure wherein is between isolation structure two 11b and isolation structure three 11c; Another segment structure not shown (can obtain as the center line symmetry In a particular embodiment) through boundary line on the right of Fig. 1.Drain region exit 10 is between isolation structure three 11c and isolation structure four 11d.Source electrode 1, grid 2 and drain and 3 be metal electrode.Simultaneously contact electrode leads to client 4 and source electrode exit 5 of the bottom of source electrode 1 wherein.The bottom contact polysilicon gate 20a of grid 2.The bottom of drain electrode 3 contacts drain terminal polysilicon field plate 20b, transoid doping ring 13 and drain region exit 10 simultaneously.
See also Fig. 2, this is another embodiment of high-voltage LDMOS device of the present invention.Compared to Figure 1 difference is a drain region exit 10 and the relation of the ring 13 that mixes around the transoid of drain region exit 10.Among Fig. 1, isolated between drain region exit 10 and the transoid doping ring 13 with an isolation structure 11 around drain region exit 10.Among Fig. 2, drain region exit 10 mixes ring 13 all at active area with transoid, mixes in transoid and has omitted an isolation structure 11 between ring 13 and the drain region exit 10.
Particularly, among the embodiment of Fig. 2,6 surface has isolation structure one 11a in the tagma.8 surface has isolation structure two 11b in the drift region, and isolation structure 11b is also on drift region inversion layer 7.8 surface also has isolation structure three 11c in the drift region, and isolation structure three 11c are not on drift region inversion layer 7.Wherein transoid mix ring 13 from depression angle be rendered as annular round the drain region exit 10.Transoid is mixed and is encircled 13 structures that are rendered as two sections spaces from cutaway view; A segment structure wherein is between isolation structure two 11b and drain region exit 10; Another segment structure not shown (can obtain as the center line symmetry In a particular embodiment) through boundary line on the right of Fig. 1.Drain region exit 10 mixes between ring 13 and isolation structure three 11c in transoid.
See also Fig. 3, this is I-V (current-voltage) the characteristic sketch map relatively of high-voltage LDMOS device of the present invention and common high-voltage LDMOS device.Wherein solid line is the I-V characteristic of high-voltage LDMOS device of the present invention, and dotted line is the common high-voltage LDMOS structure I-V characteristic with same voltage endurance capability, and the A point is two characteristic crosspoints of I-V.As can beappreciated from fig. 3, when adding, the drain terminal bias voltage was lower than A point bias voltage, the electric current of the current ratio high-voltage LDMOS device of the present invention of common high-voltage LDMOS device was big slightly, and this is because the drift region of high-voltage LDMOS device of the present invention is slightly long, causes electric current smaller.After the drain terminal bias voltage was greater than A point bias voltage, the parasitic SCR in the high-voltage LDMOS device of the present invention was open-minded, caused electric current to increase.Can find out from the result; Through introducing transoid doping ring around highly doped drain region exit; In high-voltage LDMOS device, form a parasitic SCR structure, thereby under certain bias condition, can improve the conductive capability of device greatly, reduced the conduction resistance of device.
The manufacturing approach of high-voltage LDMOS device of the present invention (is example with Fig. 1) comprises the steps:
The 1st step saw also Fig. 4 a, on low-doped substrate 9, adopted photoetching process and ion implantation technology to form drift region 8, and the doping type of drift region 8 is opposite with substrate 9.Particularly, utilize photoresist to open the subregion earlier and carry out the ion injection opposite, advance (being annealing process), form deep high voltage well 8, as the drift region through high temperature with the doping type of substrate 9.
The 2nd step saw also Fig. 4 b, on low-doped substrate 9, adopted photoetching process and ion implantation technology to form tagma 6, and the doping type in tagma 6 is identical with substrate 9.Particularly, utilize photoresist to open the subregion earlier and carry out the ion injection identical, advance (being annealing process), form low pressure well region 6, as the tagma through high temperature with the doping type of substrate 9.
The 3rd step saw also Fig. 4 c, on device drift region 8, adopted photoetching process and ion implantation technology to form drift region inversion layer 7.Particularly, utilize photoresist to open the subregion earlier and carry out the ion injection opposite with the doping type of drift region 8, formed ion implanted region 7 is as the drift region inversion layer.
The 4th step saw also Fig. 4 d, formed a plurality of isolation structures 11 at silicon chip surface.These a plurality of isolation structures 11 are silica, can be that an oxygen is isolated (LOCOS) or the manufacturing of shallow-trench isolation (STI) technology.Wherein isolation structure one 11a in the tagma 6 surface, isolation structure two 11b are on the surface of drift region 8 and on drift region inversion layer 7, isolation structure three 11c, isolation structure four 11d are on the surface of drift region 8 and all not on drift region inversion layer 7.
The 5th step saw also Fig. 4 e, at the first growth one deck gate oxide (not shown) of silicon chip surface, and deposit one deck polysilicon 20 again, thus this layer of etching polysilicon 20 forms polysilicon gate 20a and drain terminal polysilicon field plate 20b with gate oxide.The end of polysilicon gate 20a is on tagma 6, and the other end is on isolation structure two 11b.Drain terminal polysilicon field plate 20b is then on isolation structure two 11b near drain terminal.
The 6th step saw also Fig. 4 f, and end in the source (tagma 6) and drain terminal (drift region 8) carry out heavy doping ion and inject formation source region exit 5 and drain region exit 10, and the type that ion injects is identical with the drift region.Source region exit 5 is among tagma 6 and near the end of polysilicon gate 20a.Drain region exit 10 is among the drift region 8 and between isolation structure three 11c and isolation structure four 11d.
The 7th step saw also Fig. 4 g, and the end in the source (tagma 6) and drain terminal (drift region 8) carry out injecting with source electrode, the opposite ion of drain electrode doping type, organizator electrode leads to client 4 and center on the annular doping district 13 of drain region exit 10.Body electrode leads to client 4 is among the tagma 6 and between isolation structure one 11a and source region exit 5.Annular doping district 13 claims transoid mix ring or special shaped doped ring again, and the exit 10 among drift region 8 and round the drain region is observed from depression angle and to be presented annular, from cutaway view, then is rendered as the structure of two sections spaces.Wherein a segment structure in annular doping district 13 is between isolation structure two 11b and isolation structure three 11c, and another segment structure is not shown.Drain region exit 10 is between isolation structure three 11c and isolation structure four 11d.
The 8th step saw also Fig. 4 h, and postchannel process is a standard CMOS postchannel process flow process, and first deposition of dielectric layer 12 etches contact hole then, and in contact hole, fills metal electrode, formed resulting devices.Metal electrode comprises source electrode 1, grid 2 and drains 3.Simultaneously contact electrode leads to client 4 and source electrode exit 5 of the bottom of source electrode 1 wherein.The bottom contact polysilicon gate 20a of grid 2.The bottom of drain electrode 3 contacts drain terminal polysilicon field plate 20b, transoid doping ring 13 and drain region exit 10 simultaneously.
Said the 3rd step of method can also be placed on before the 2nd step, perhaps was placed on before the 5th step.
The manufacturing approach of above-mentioned high-voltage LDMOS device also is applicable to makes high-voltage LDMOS device shown in Figure 2; Just in the 4th step, form an isolation structure 11 less; Simultaneously in the 7th step: annular doping district 13 then is rendered as the structure of two sections spaces from cutaway view; Wherein a segment structure is between isolation structure two 11b and drain region exit 10, and another segment structure is not shown.Drain region exit 10 is between annular doping district 13 and isolation structure three 11c.
Requirement according to process conditions and device property; Can optimize the structure of special shaped doped ring 13 and drain region exit 10; And the method that increases a dedicated mask plate regulates CONCENTRATION DISTRIBUTION in the special shaped doped ring 13 (this dedicated mask plate and corresponding processing step thereof also can be adjusted its order in whole process flow and change the opposite sex CONCENTRATION DISTRIBUTION in the ring 13 of mixing), realizes the present invention equally.
In sum; High-voltage LDMOS device of the present invention is introduced the special shaped doped ring around highly doped drain region exit through the drain terminal at common high-voltage LDMOS device, and this special shaped doped ring will form parasitic SCR device with drift region, tagma and the source end of former LDMOS device.On the one hand, the CURRENT DISTRIBUTION after the LDMOS conducting can reduce the turning-on voltage of parasitic SCR device.On the other hand, after this parasitic SCR device is opened, because the high conductive capability of SCR can reduce the conducting resistance of entire device.Like this; High-voltage LDMOS device of the present invention is actually the multiple device structure of common LDMOS device and SCR device; Make full use of LDMOS and SCR device advantage separately, be implemented in when satisfying high reverse breakdown voltage, under certain working bias voltage condition, reduced the conducting resistance of device.
Claims (6)
1. a high-voltage LDMOS device is characterized in that, the structure of said high-voltage LDMOS device is:
In low-doped substrate, have drift region and tagma, the doping type and the substrate of drift region are opposite, and the doping type in tagma is identical with substrate;
Have the drift region inversion layer on the surface of drift region, the doping type and the drift region of drift region inversion layer are opposite;
Has isolation structure one on the surface in tagma; Have isolation structure two on the surface of drift region, isolation structure two is also on the inversion layer of drift region; Also have isolation structure three and isolation structure four on the surface of drift region;
On tagma and isolation structure two, have polysilicon gate and polysilicon field plate; One end of polysilicon gate is on the tagma, and the other end is on isolation structure two; The polysilicon field plate is on isolation structure two;
Among the tagma, have body electrode leads to client and source region exit, the body electrode leads to client is between isolation structure one and source region exit, and doping type is identical with the tagma doping type; The source region exit is between body electrode leads to client and polysilicon gate, and doping type and tagma are opposite;
Among the drift region, have drain region exit and transoid doping ring, the doping type of drain region exit is identical with the drift region, and the doping type of transoid doping ring is opposite with the drain region exit; Said transoid mix ring from depression angle be rendered as annular round the drain region exit, then be rendered as the structure of two sections spaces from analysing and observe angle, a segment structure wherein is between isolation structure two and isolation structure three; Drain region exit 10 is between isolation structure three and isolation structure four;
Source electrode, grid and drain electrode are metal electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate simultaneously, transoid is mixed and encircled and the drain region exit.
2. a high-voltage LDMOS device is characterized in that, the structure of said high-voltage LDMOS device is:
In low-doped substrate, have drift region and tagma, the doping type and the substrate of drift region are opposite, and the doping type in tagma is identical with substrate;
Have the drift region inversion layer on the surface of drift region, the doping type and the drift region of drift region inversion layer are opposite;
Has isolation structure one on the surface in tagma; Have isolation structure two on the surface of drift region, isolation structure two is also on the inversion layer of drift region; Surface in the drift region also has isolation structure three;
On tagma and isolation structure two, have polysilicon gate and polysilicon field plate; One end of polysilicon gate is on the tagma, and the other end is on isolation structure two; The polysilicon field plate is on isolation structure two;
Among the tagma, have body electrode leads to client and source region exit, the body electrode leads to client is between isolation structure one and source region exit, and doping type is identical with the tagma; The source region exit is between body electrode leads to client and polysilicon gate, and doping type and tagma are opposite;
Among the drift region, have drain region exit and transoid doping ring, the doping type of drain region exit is identical with the drift region, and the doping type and the drift region of transoid doping ring are opposite; Said transoid mix ring from depression angle be rendered as annular round the drain region exit, then be rendered as the structure of two sections spaces from analysing and observe angle, a segment structure wherein is between isolation structure two and drain region exit; The drain region exit mixes between ring and the isolation structure three in transoid;
Source electrode, grid and drain electrode are metal electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate simultaneously, transoid is mixed and encircled and the drain region exit.
3. a method of making the described high-voltage LDMOS device of claim 1 is characterized in that, comprises the steps:
The 1st step, on low-doped substrate, adopt photoetching process and ion implantation technology to form the drift region, the doping type and the substrate of drift region are opposite;
The 2nd step, on low-doped substrate, adopt photoetching process and ion implantation technology to form the tagma, the doping type in tagma is identical with substrate;
The 3rd step, on the drift region, adopt photoetching process and ion implantation technology to form the drift region inversion layer, the doping type and the drift region of drift region inversion layer are opposite;
The 4th step formed a plurality of isolation structures at silicon chip surface, and wherein isolation structure one is on the surface in tagma, and isolation structure two is on the surface of drift region and on the inversion layer of drift region, and isolation structure three, isolation structure four are all on the surface of drift region;
The 5th step, at the first growth one deck gate oxide of silicon chip surface, deposit one deck polysilicon again, thereby this layer of etching polysilicon and gate oxide formation polysilicon gate and drain terminal polysilicon field plate;
One end of polysilicon gate is on the tagma, and the other end is on isolation structure two;
Drain terminal polysilicon field plate is then on isolation structure two;
The 6th step, carry out heavy doping ion injection formation source region exit and drain region exit in tagma and drift region, the type that ion injects is identical with the drift region;
The source region exit is among the tagma and near an end of polysilicon gate;
The drain region exit is among the drift region and between isolation structure three and isolation structure four;
In the 7th step, carry out injecting organizator electrode leads to client and center on the annular doping district of drain region exit in tagma and drift region with source electrode, ion that the drain electrode doping type is opposite;
The body electrode leads to client is among the tagma and between isolation structure one and source region exit;
The annular doping district claims transoid mix ring or special shaped doped ring again, and the exit among the drift region and round the drain region is observed from depression angle and to be presented annular, then is rendered as the structure of two sections spaces from analysing and observe angle; Wherein a segment structure in annular doping district is between isolation structure two and isolation structure three, and the drain region exit is between isolation structure three and isolation structure four;
In the 8th step, first deposition of dielectric layer etches contact hole then, and in contact hole, fills metal electrode, forms resulting devices; Metal electrode comprises source electrode, grid and drain electrode;
The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously;
The bottom contact polysilicon gate of grid;
The bottom of drain electrode contacts drain terminal polysilicon field plate simultaneously, transoid is mixed and encircled and the drain region exit.
4. the method for manufacturing high-voltage LDMOS device according to claim 3 is characterized in that, said the 3rd step of method was placed on before the 2nd step, perhaps was placed on before the 5th step.
5. a method of making the described high-voltage LDMOS device of claim 2 is characterized in that, comprises the steps:
The 1st step, on low-doped substrate, adopt photoetching process and ion implantation technology to form the drift region, the doping type and the substrate of drift region are opposite;
The 2nd step, on low-doped substrate, adopt photoetching process and ion implantation technology to form the tagma, the doping type in tagma is identical with substrate;
The 3rd step, on the drift region, adopt photoetching process and ion implantation technology to form the drift region inversion layer, the doping type and the drift region of drift region inversion layer are opposite;
The 4th step formed a plurality of isolation structures at silicon chip surface, and wherein isolation structure one is on the surface in tagma, and isolation structure two is the surperficial of drift region and on the inversion layer of drift region, isolation structure three is on the surface of drift region;
The 5th step, at the first growth one deck gate oxide of silicon chip surface, deposit one deck polysilicon again, thereby this layer of etching polysilicon and gate oxide formation polysilicon gate and drain terminal polysilicon field plate;
One end of polysilicon gate is on the tagma, and the other end is on isolation structure two;
Drain terminal polysilicon field plate is then on isolation structure two;
The 6th step, carry out heavy doping ion injection formation source region exit and drain region exit in tagma and drift region, the type that ion injects is identical with the drift region;
The source region exit is among the tagma and near an end of polysilicon gate;
The drain region exit is among the drift region and between isolation structure two and isolation structure three;
In the 7th step, carry out injecting organizator electrode leads to client and center on the annular doping district of drain region exit in tagma and drift region with source electrode, ion that the drain electrode doping type is opposite;
The body electrode leads to client is among the tagma and between isolation structure one and source region exit;
The annular doping district claims transoid doping ring or special shaped doped ring again; The exit among the drift region and round the drain region; Present annular from the depression angle observation; Then be rendered as the structure of two sections spaces from analysing and observe angle, wherein a segment structure is between isolation structure two and drain region exit, and the drain region exit is between annular doping district and isolation structure three;
In the 8th step, first deposition of dielectric layer etches contact hole then, and in contact hole, fills metal electrode, forms resulting devices; Metal electrode comprises source electrode, grid and drain electrode;
The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously;
The bottom contact polysilicon gate of grid;
The bottom of drain electrode contacts drain terminal polysilicon field plate simultaneously, transoid is mixed and encircled and the drain region exit.
6. the method for manufacturing high-voltage LDMOS device according to claim 5 is characterized in that, said the 3rd step of method was placed on before the 2nd step, perhaps was placed on before the 5th step.
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