CN209981222U - High-voltage multi-time epitaxial super-junction MOSFET structure - Google Patents
High-voltage multi-time epitaxial super-junction MOSFET structure Download PDFInfo
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- CN209981222U CN209981222U CN201920638621.0U CN201920638621U CN209981222U CN 209981222 U CN209981222 U CN 209981222U CN 201920638621 U CN201920638621 U CN 201920638621U CN 209981222 U CN209981222 U CN 209981222U
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- 210000000746 body region Anatomy 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 238000000407 epitaxy Methods 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims 2
- 230000005669 field effect Effects 0.000 claims 1
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 description 10
- 238000001259 photo etching Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008570 general process Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000008094 contradictory effect Effects 0.000 description 1
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Abstract
The utility model belongs to the technical field of semiconductor device's manufacturing, a high pressure many times epitaxial type surpasses knot MOSFET's structure is related to, surpass knot device unit and include the first epitaxial layer of first conductivity type and first conductivity type substrate, be equipped with the second epitaxial layer of first conductivity type on the first epitaxial layer of first conductivity type, be equipped with second conductivity type body region in the second epitaxial layer of first conductivity type, be equipped with second conductivity type post below second conductivity type body region, second conductivity type post passes first conductivity type second epitaxial layer from second conductivity type body region bottom and extends to in the first epitaxial layer of first conductivity type, and the second conductivity type post is deep into the first epitaxial intraformational degree of depth of first conductivity type and is no more than 5 μm; the utility model discloses a many times epitaxial technology grows the epitaxial layer of two kinds of different resistivities, and the resistivity and the thickness of the degree of depth, the first epitaxial layer of adjustment N type and the second epitaxial layer of N type of going deep into the first epitaxial layer of N type through adjustment P type post can realize higher pressure resistance.
Description
Technical Field
The utility model relates to a super junction MOSFET structure specifically is a high pressure many times epitaxial type surpasses super junction MOSFET's structure, belongs to semiconductor device's manufacturing technical field.
Background
The on-resistance of the traditional power MOSFET device is mainly determined by the length and the doping concentration of the drift region, and the smaller the length of the drift region is, the smaller the on-resistance is, the higher the doping concentration of the drift region is, and the smaller the on-resistance is. However, these two changes result in a reduction in the breakdown voltage of the device, and thus the on-resistance and the breakdown voltage are in an contradictory or trade-off relationship, i.e., the reduction in the on-resistance is limited by the breakdown voltage.
The advent of superjunction structures breaks this limitation. The super junction structure is formed by replacing an N-type drift region with P-type columns and N-type columns which are alternately arranged, the withstand voltage of the device is mainly determined by the length and the total charge of the P-type columns, the larger the length of the P-type columns is, the higher the breakdown voltage is, however, the process capability is limited, the P-type columns of the super junction structure cannot be infinitely long, and therefore, the withstand voltage capability is also limited, and the ultra-high voltage power MOSFET device cannot be achieved at present.
Disclosure of Invention
The utility model aims at overcoming the not enough that exists among the prior art, providing a high pressure many times epitaxial type surpasses knot MOSFET's structure and manufacturing method, through epitaxial technology, grow the epitaxial layer of two kinds of different resistivities, go deep into the degree of depth of the first epitaxial layer of N type, the resistivity and the thickness of the first epitaxial layer of adjustment N type and N type second epitaxial layer through adjustment P type post, can realize higher withstand voltage ability.
In order to realize the technical purpose, the technical proposal of the utility model is that: a structure of a high-voltage multi-epitaxial super-junction MOSFET comprises a plurality of super-junction device units which are connected in parallel, the super junction device unit comprises a first conductive type first epitaxial layer and a first conductive type substrate positioned below the first conductive type first epitaxial layer, is characterized in that a first conductive type second epitaxial layer formed by multiple times of epitaxy is arranged on the first conductive type first epitaxial layer, a second conductive type body region is arranged in the first conductive type second epitaxial layer, a plurality of times of extension second conductive type columns are arranged below the second conductive type body region, extend from the bottom of the second conductive type body region to the first conductive type first epitaxial layer through the first conductive type second epitaxial layer, and the second conductive type column is multi-epitaxially grown to a depth of not more than 5 μm into the first conductive type first epitaxial layer.
Further, the resistivity of the first epitaxial layer of the first conductivity type is greater than the resistivity of the second epitaxial layer of the first conductivity type.
Further, the resistivity of the first conductive type first epitaxial layer is 1ohm-300ohm, and the thickness is 2 μm ~ 700 μm and 700 μm.
Further, a first conductive type source region is arranged in the second conductive type body region, a gate oxide layer, conductive polycrystalline silicon positioned on the gate oxide layer, an insulating medium layer surrounding the gate oxide layer and the conductive polycrystalline silicon and source metal are arranged above the second conductive type body region, and the source metal is respectively contacted with the first conductive type source region and the second conductive type body region.
In order to further realize the above technical object, the utility model discloses still provide a manufacturing method of high pressure many times epitaxial type surpasses knot MOSFET's structure, including a plurality of super junction device unit that connect in parallel each other, characterized by, the manufacturing method who surpasses knot device unit includes following step:
the first step is as follows: selecting a first conductive type silicon substrate as a first conductive type substrate, and growing a first conductive type first epitaxial layer on the upper surface of the first conductive type substrate by adopting an epitaxial process;
the second step is that: injecting second conductive type impurities into the surface of the first conductive type first epitaxial layer under the shielding of the first photoetching plate to form an undispersed second conductive type layer;
the third step: continuously growing a thin second epitaxial layer of the first conductivity type on the surface of the device; under the shielding of the first photoetching plate, injecting second conductive type impurities into the surface of the thin first conductive type second epitaxial layer to form an undispersed second conductive type layer;
the fourth step: repeating the third step for a plurality of times, and finally growing a first conductive type top epitaxial layer, wherein the first conductive type second epitaxial layer and the first conductive type top epitaxial layer form a first conductive type second epitaxial layer together;
the resistivity of the first conductive type first epitaxial layer is greater than that of the first conductive type second epitaxial layer;
the fifth step: performing high-temperature annealing on second conductive type impurity ions injected into the first conductive type second epitaxial layer, and forming a multi-time epitaxial second conductive type column in the first conductive type second epitaxial layer, wherein the depth of the multi-time epitaxial second conductive type column extending into the first conductive type first epitaxial layer is not more than mum;
and a sixth step: injecting second conductive type impurities into the surface of the first conductive type top epitaxial layer through shielding of a second photoetching plate, and carrying out high-temperature well pushing to form a second conductive type body region in the first conductive type second epitaxial layer;
the seventh step: thermally growing an oxide layer on the first conductive type second epitaxial layer, depositing conductive polycrystalline silicon on the oxide layer, and selectively etching the conductive polycrystalline silicon and the oxide layer in sequence to obtain a gate oxide layer and gate polycrystalline silicon on the gate oxide layer;
eighth step: under the shielding of a third photoetching plate, injecting first conductive type ions into the surface of the second conductive type body region, and carrying out high-temperature well pushing to form a first conductive type source region in the second conductive type body region;
the ninth step: depositing an insulating medium layer on the surface of the device, selectively etching the insulating medium layer to form a metal contact through hole;
the tenth step: and depositing metal in the metal contact through hole to obtain source metal, and forming drain metal on the lower surface of the first conduction type substrate.
Further, the super-junction MOSFET structure comprises a super-junction structure of an N-type power semiconductor device and a super-junction structure of a P-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type for the super-junction structure of the N-type power semiconductor device, and the first conductivity type is P-type and the second conductivity type is N-type for the super-junction structure of the P-type power semiconductor device.
Further, the structure of the super junction MOSFET comprises an IGBT device and a MOSFET device.
Further, the multi-epitaxy second conductivity type pillars are greater than 40 μm deep.
The utility model has the advantages of it is following:
1) the utility model discloses on the basis of current super junction structure, divide into first epitaxial layer of N type and N type second epitaxial layer with the epitaxial layer, and the resistivity of the first epitaxial layer of N type is greater than the resistivity of the second epitaxial layer of N type, carry out the combination of different resistivity and thickness to first epitaxial layer of N type and N type second epitaxial layer according to the different voltages that need to realize, form the EPI structure of super junction MOS;
when the device is voltage-resistant, the N-type second epitaxial layer is mainly used for forming a super junction structure with the P-type column, and lateral complete depletion is realized; the resistivity of the N-type first epitaxial layer is larger than that of the N-type second epitaxial layer, so that higher voltage endurance is realized, the resistivity and the thickness can be adjusted according to the voltage to be realized, and the resistivity range of the first epitaxial layer is 1ohm-300ohm, and the thickness is 2 mu m-700 mu m;
the depth of the P-type column penetrating into the N-type first epitaxial layer is further adjusted by adjusting the implantation dose and energy of P impurity ions in the N-type second epitaxial layer, when the distance of the P-type column penetrating into the N-type first epitaxial layer is 0 μm, the voltage resistance is highest at this time, the voltage resistance is reduced in a parabola mode after exceeding 0 μm, if the charge balance unbalance exceeds 5 μm, the voltage is reduced steeply, and due to the process consistency, the in-chip consistency is considered, and the depth of the P-type column penetrating into the N-type first epitaxial layer is controlled to be about 2.5 μm when the general process is realized;
2) the super junction structure of the utility model can realize the voltage withstanding capability of 600V ~ 6500V, and the manufacturing method is compatible with the prior art, and does not need to increase extra development cost.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional structure diagram of a super junction MOSFET cell structure in the prior art.
Fig. 2 is a schematic cross-sectional structure diagram of forming an N-type first epitaxial layer according to embodiment 1 of the present invention.
Fig. 3 is a schematic cross-sectional structure diagram of forming a P-type layer in an N-type first epitaxial layer according to embodiment 1 of the present invention.
Fig. 4 is a schematic cross-sectional view of embodiment 1 of the present invention, in which a P-type layer is formed in a thin N-type second epitaxial layer.
Fig. 5 is a schematic cross-sectional structure diagram of forming an N-type second epitaxial layer according to embodiment 1 of the present invention.
Fig. 6 is a schematic cross-sectional structure diagram of forming a P-type column according to embodiment 1 of the present invention.
Fig. 7 is a schematic sectional structure diagram of a super junction MOSFET cell structure according to embodiment 1 of the present invention.
Description of reference numerals: 1. an N-type substrate; 2. an N-type first epitaxial layer; 3. an N-type second epitaxial layer; 31. a thin N-type second epitaxial layer; 32. an N-type top epitaxial layer; 4. a P-type body region; 5. an N-type source region; 6. extending the P-type column for multiple times; 7. a gate oxide layer; 8. conducting polycrystalline silicon; 9. an insulating dielectric layer; 10. a source metal; 11. a drain metal; 12. a P-type layer.
Detailed Description
The invention is further described with reference to the following specific drawings and examples.
The present invention is not limited to the following embodiments, and the drawings referred to in the following description are provided to understand the contents of the present invention, that is, the present invention is not limited to the device structures exemplified by the drawings, and is applicable to both IGBT devices and MOSFET devices.
Example 1: taking an N-type planar gate super-junction MOSFET device as an example, the first conduction type is an N type, the second conduction type is a P type, and the semiconductor device comprises an active region and a terminal region surrounding the active region on a top plane;
as shown in fig. 7, the active region includes a plurality of super junction device units connected in parallel, including a plurality of super junction device units connected in parallel, where the super junction device unit includes an N-type first epitaxial layer 2 and an N-type substrate 1 located below the N-type first epitaxial layer 2, an N-type second epitaxial layer 3 is disposed on the N-type first epitaxial layer 2, a P-type body region 4 is disposed in the N-type second epitaxial layer 3, a multi-time epitaxial P-type column 6 is disposed below the P-type body region 4, the multi-time epitaxial P-type column 6 passes through the N-type second epitaxial layer 3 from the bottom of the P-type body region 4 and extends into the N-type first epitaxial layer 2, the depth of the multi-time epitaxial P-type column 6 extending into the N-type first epitaxial layer 2 is not more than 5 μm, the depth of the multi-time epitaxial P-type column 6 is more than 40 μm, the resistivity of the N-type first epitaxial layer 2 is more than that of the N-type second epitaxial layer 3, the resistivity of the N-type first epitaxial layer 2 is 1ohm-300 μm, and the thickness is 35;
an N-type source region 5 is arranged in the P-type body region 4, a gate oxide layer 7, conductive polycrystalline silicon 8 positioned on the gate oxide layer 7, an insulating medium layer 9 surrounding the gate oxide layer 7 and the conductive polycrystalline silicon 8 and source metal 10 are arranged above the P-type body region 4, and the source metal 10 is respectively contacted with the N-type source region 5 and the P-type body region 4.
The method for manufacturing the high-voltage multi-time epitaxial super-junction MOSFET structure according to embodiment 1 includes a plurality of super-junction device units connected in parallel, and the method for manufacturing the super-junction device units includes the following steps:
as shown in fig. 2, the first step: selecting an N-type silicon substrate as an N-type substrate 1, and growing an N-type first epitaxial layer 2 on the upper surface of the N-type substrate 1 by adopting an epitaxial process;
as shown in fig. 3, the second step: injecting P-type impurities into the surface of the N-type first epitaxial layer 2 under the shielding of a first photoetching plate to form an un-diffused P-type layer 12;
as shown in fig. 4, the third step: continuously growing a thin N-type second epitaxial layer 31 on the surface of the device; injecting P-type impurities into the surface of the thin N-type second epitaxial layer 31 under the shielding of the first photoetching plate to form an un-diffused P-type layer 12;
as shown in fig. 5, the fourth step: repeating the third step twice, and finally growing a layer of N-type top epitaxial layer 32, wherein the N-type second epitaxial layer 3 is formed by a plurality of thin N-type second epitaxial layers 31 and the N-type top epitaxial layer 32;
the resistivity of the N-type first epitaxial layer 2 is greater than that of the N-type second epitaxial layer 3;
as shown in fig. 6, the fifth step: carrying out high-temperature annealing on the P-type impurity ions injected into the N-type second epitaxial layer 3, and forming a multi-time epitaxial P-type column 6 in the N-type second epitaxial layer 3, wherein the depth of the multi-time epitaxial P-type column 6 extending into the N-type first epitaxial layer 2 is not more than 5 microns; the depth of the multi-time epitaxial P-type column 6 is more than 40 mu m;
as shown in fig. 7, the sixth step: injecting P-type impurities into the surface of the N-type top epitaxial layer 32 through shielding of a second photoetching plate, and carrying out high-temperature well pushing to form a P-type body region 4 in the N-type second epitaxial layer 3;
the seventh step: thermally growing an oxide layer on the N-type second epitaxial layer 3, depositing conductive polycrystalline silicon on the oxide layer, and selectively etching the conductive polycrystalline silicon and the oxide layer in sequence to obtain a gate oxide layer 7 and gate polycrystalline silicon 8 on the gate oxide layer 7;
eighth step: under the shielding of a third photoetching plate, injecting N-type ions into the surface of the P-type body region 4, and carrying out high-temperature trap pushing to form an N-type source region 5 in the P-type body region 4;
the ninth step: depositing an insulating medium layer 9 on the surface of the device, selectively etching the insulating medium layer 9, and forming a metal contact through hole;
the tenth step: depositing metal in the metal contact through hole to obtain source metal 10, and forming drain metal 11 on the lower surface of the N-type substrate 1; as is well known to those skilled in the art, the description is omitted;
the utility model can realize different pressure resistance by adjusting the implantation dosage and energy of P impurity ions in the N type second epitaxial layer, further adjusting the depth of the multi-time epitaxial P type column 6 penetrating into the N type first epitaxial layer 2 and the resistivity and thickness of the N type first epitaxial layer 2 and the N type second epitaxial layer 3; when the distance between the multiple-time extension P-type column 6 and the N-type first epitaxial layer 2 is 0 μm, the voltage endurance is highest, the voltage endurance is reduced in a parabola shape after exceeding 0 μm, when the charge balance is unbalanced by exceeding 5 μm, the voltage is reduced steeply, and due to the process consistency, the in-chip consistency is considered, and the depth of the multiple-time extension P-type column 6 extending into the N-type first epitaxial layer 2 is about 2.5 μm when the general process is realized; for example, in a 1000V product, the depth of the multi-extension P-type column 6 is about 52.5 μm, the thickness of the N-type second epitaxial layer 3 is about 50 μm, the resistivity is about 4ohm, when the depth of the multi-extension P-type column 6 is less than 50 μm, the withstand voltage is only about 600V, and when the depth of the multi-extension P-type column 6 is more than 55 μm, the charge balance is unbalanced, the withstand voltage capability is abruptly reduced, and the withstand voltage capability is lower than 600V; therefore, the depth of the multiple-time extension P-type column 6 extending into the N-type first epitaxial layer 2 is between 0 and 5 μm, the voltage endurance capability of the device can be made high by adjusting the resistivity and thickness of the upper and lower epitaxial layers, and the resistance per unit area is also advantageous.
The present invention and the embodiments thereof have been described above, but the description is not limited thereto, and what is shown in the drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto. In summary, those skilled in the art should understand that they should not be limited to the embodiments described above, and that they can design the similar structure and embodiments without departing from the spirit of the invention.
Claims (3)
1. A structure of a high-voltage multi-time epitaxial super-junction MOSFET comprises a plurality of super-junction device units which are connected in parallel, wherein each super-junction device unit comprises a first conductive type first epitaxial layer (2) and a first conductive type substrate (1) positioned below the first conductive type first epitaxial layer (2), the structure is characterized in that a first conductive type second epitaxial layer (3) formed by multiple times of epitaxy is arranged on the first conductive type first epitaxial layer (2), a second conductive type body area (4) is arranged in the first conductive type second epitaxial layer (3), a multi-time epitaxial second conductive type column (6) is arranged below the second conductive type body area (4), and the multi-time epitaxial second conductive type column (6) penetrates through the first conductive type second epitaxial layer (3) from the bottom of the second conductive type body area (4) and extends into the first conductive type first epitaxial layer (2), and the depth of the second conductive type column (6) extending into the first conductive type first epitaxial layer (2) for multiple times is not more than 5 μm; the resistivity of the first conductivity type first epitaxial layer (2) is greater than the resistivity of the first conductivity type second epitaxial layer (3).
2. The structure of a high voltage multiepitaxial superjunction MOSFET of claim 1, wherein the first epitaxial layer (2) of the first conductivity type has a resistivity of 1-300 ohm and a thickness of 2 μ ι η ~ 700 μ ι η.
3. The structure of the high-voltage multi-epitaxial super-junction MOSFET (metal oxide semiconductor field effect transistor) according to claim 1, wherein a first conduction type source region (5) is arranged in the second conduction type body region (4), a gate oxide layer (7), conductive polysilicon (8) located on the gate oxide layer (7), an insulating dielectric layer (9) surrounding the gate oxide layer (7) and the conductive polysilicon (8), and a source metal (10) are arranged above the second conduction type body region (4), and the source metal (10) is respectively in contact with the first conduction type source region (5) and the second conduction type body region (4).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010694A (en) * | 2019-05-07 | 2019-07-12 | 无锡紫光微电子有限公司 | A kind of structure and manufacturing method of the multiple extension type super node MOSFET of high pressure |
| CN116110944A (en) * | 2023-04-12 | 2023-05-12 | 江苏应能微电子股份有限公司 | Shielded gate trench MOSFET device based on Resurf effect and preparation method thereof |
-
2019
- 2019-05-07 CN CN201920638621.0U patent/CN209981222U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010694A (en) * | 2019-05-07 | 2019-07-12 | 无锡紫光微电子有限公司 | A kind of structure and manufacturing method of the multiple extension type super node MOSFET of high pressure |
| CN110010694B (en) * | 2019-05-07 | 2024-03-12 | 无锡紫光微电子有限公司 | Structure and manufacturing method of high-voltage multiple epitaxial super-junction MOSFET |
| CN116110944A (en) * | 2023-04-12 | 2023-05-12 | 江苏应能微电子股份有限公司 | Shielded gate trench MOSFET device based on Resurf effect and preparation method thereof |
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