CN109686781B - Method for manufacturing super junction device by multiple epitaxy - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000407 epitaxy Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 39
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims abstract description 17
- 238000002347 injection Methods 0.000 claims abstract description 16
- 239000007924 injection Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 238000002513 implantation Methods 0.000 claims description 10
- 210000000746 body region Anatomy 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 abstract description 7
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 238000011084 recovery Methods 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000001459 lithography Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
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- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention belongs to the technical field of manufacturing of semiconductor devices, and relates to a method for manufacturing a multi-epitaxial super junction device, which comprises the steps of growing a plurality of epitaxial layers on a substrate, generally injecting second conductive type impurities and selectively injecting first conductive type impurities into each epitaxial layer, and then pushing wells at high temperature to form a multi-epitaxial super junction structure; according to the invention, the existing deposition epitaxy, the N-type ion implantation, the selective injection of the N-type ions and the high-temperature well are replaced by the deposition epitaxy, the P-type ion implantation, the selective injection of the N-type ions and the high-temperature well, so that the distance between the formed P-type columns is increased (namely the width of the N-type column is increased), the concentration of majority carriers which can be stored in the N-type epitaxy layer is higher when the N-type column is conducted in the forward direction, the time is longer when the N-type column is recovered in the reverse direction, the reverse recovery softness is increased, and the dynamic parameter characteristics of di/dt and dv/dt are improved.
Description
Technical Field
The invention relates to a manufacturing method of a super junction device, in particular to a manufacturing method of a super junction device with multiple epitaxy, and belongs to the technical field of manufacturing of semiconductor devices.
Background
The on-resistance of the traditional power MOSFET device is mainly determined by the length and the doping concentration of the drift region, and the smaller the length of the drift region is, the smaller the on-resistance is, the higher the doping concentration of the drift region is, and the smaller the on-resistance is. However, these two changes result in a reduction in the breakdown voltage of the device, and thus the on-resistance and the breakdown voltage are in an contradictory or trade-off relationship, i.e., the reduction in the on-resistance is limited by the breakdown voltage.
The advent of superjunction structures breaks this limitation. The super junction structure is formed by replacing an N-type drift region with P-type columns and N-type columns which are alternately arranged, the withstand voltage of the device is mainly determined by the length of the P-type columns and the total charge, and the larger the length of the P-type columns is, the higher the breakdown voltage is. On the premise of ensuring that the total charge of the P-type column and the N-type column is equal, the on-resistance of the device can be reduced without influencing the breakdown voltage of the device by reducing the width of the P-type column and increasing the doping concentration of P-type ions. Therefore, the larger the ratio of the length to the width of the P-type column, the higher the tradeoff between the breakdown voltage and the on-resistance.
At present, a common method for preparing a super junction structure is a multi-time epitaxy and lithography plus implantation technology, that is, firstly, N-type epitaxy is performed on an N + type substrate material once, then, a P-type column region is photoetched and P-type ion implantation is performed, then, N-type epitaxy is performed for the second time, a P-type column region is photoetched again and P-type ion implantation is performed, the above procedures are repeated for the third time, the fourth time or even more according to the device breakdown voltage requirement, however, the area occupied by the terminal region of the structure is large, and the production cost of multi-time epitaxy and multi-time lithography and multi-time implantation is high.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a method for manufacturing a multi-epitaxy super-junction device, when a super-junction structure is formed, the existing deposition epitaxy, N-type ion implantation, selective implantation of P-type ions and high-temperature push-in trap are replaced by deposition epitaxy, P-type ion implantation, selective implantation of P-type ions and high-temperature push-in trap, so that the distance between the formed P-type columns is increased (namely the width of the N-type column is increased), the concentration of most current carriers which can be stored in the N-type epitaxy layer is higher when the N-type epitaxy layer is conducted in a forward direction, the time is longer when the N-type epitaxy layer is recovered in a reverse direction, the reverse recovery softness is increased, and the dynamic parameter characteristics of di/dt and dv/dt are improved.
In order to achieve the technical purpose, the technical scheme of the invention is as follows: a method for manufacturing a super junction device with multiple epitaxy comprises a plurality of super junction device units which are connected in parallel, and is characterized in that the method for manufacturing the super junction device units comprises the following steps:
the first step is as follows: selecting a first conductive type silicon substrate as a first conductive type substrate, and growing a first conductive type epitaxial layer on the upper surface of the first conductive type substrate by adopting an epitaxial process;
the second step is that: generally injecting second conductive type impurities into the surface of the first conductive type epitaxial layer to form a second conductive type layer which is not diffused, and then selectively injecting first conductive type impurities to form a first conductive type region which is not diffused;
the third step: continuously growing a layer of second first conductivity type on the epitaxial layer of first conductivity type
The epitaxial layer is continuously and generally implanted with second conductive type impurities on the surface of the second first conductive type epitaxial layer, and then selectively implanted with first conductive type impurities;
the fourth step: repeating the steps, sequentially forming a third first conduction type epitaxial layer, a fourth first conduction type epitaxial layer and a fifth first conduction type epitaxial layer, and finally, growing a top first conduction type epitaxial layer to finish the manufacture of the first conduction type epitaxial layer;
carrying out 6 times of epitaxial growth continuously, carrying out 5 times of generally injecting second conductive type impurities and selectively injecting first conductive type impurities, and finally forming a first conductive type epitaxial layer;
the fifth step: performing high-temperature annealing on the impurity ions injected into the first conductive type epitaxial layer, and forming second conductive type columns and first conductive type columns which are alternately distributed in the first conductive type epitaxial layer;
and a sixth step: thermally growing an oxide layer on the first conductive type epitaxial layer, depositing conductive polycrystalline silicon on the oxide layer, and selectively etching the conductive polycrystalline silicon and the oxide layer in sequence to obtain a gate oxide layer and gate polycrystalline silicon on the gate oxide layer;
the seventh step: under the shielding of the grid polysilicon, injecting second conductive type impurities in a self-alignment manner, annealing at high temperature, forming a second conductive type body region above the second conductive type column, and then selectively injecting first conductive type impurities to form a first conductive type source region positioned in the second conductive type body region;
eighth step: depositing an insulating medium layer on the surface of the device, selectively etching the insulating medium layer to form a metal contact through hole;
the ninth step: and depositing metal in the metal contact through hole to obtain source metal and forming drain metal on the lower surface of the first conduction type substrate.
Further, in the second step and the third step, the selective implantation of the first conductive type impurities is performed under the shielding of a mask layer, the mask layer is etched to obtain a plurality of mask windows for the implantation of the first conductive type impurities, and the width and the interval of the mask windows are the same.
Further, in the fourth step, the number of times of repeating the third step is determined according to the magnitude of the device withstand voltage.
Further, the super junction device unit comprises a super junction device unit of an N-type power semiconductor device and a super junction device unit of a P-type power semiconductor device, the first conduction type is N-type and the second conduction type is P-type for a super junction structure of the N-type power semiconductor device, and the first conduction type is P-type and the second conduction type is N-type for a super junction structure of the P-type power semiconductor device.
Further, the multi-epitaxial super junction device comprises an IGBT device and a MOSFET device.
Compared with the existing super junction structure with multiple epitaxy, the super junction structure has the following advantages:
1) when a super junction structure is formed, the existing deposition epitaxy, the P-type ion common injection, the selective injection of N-type ions and the high-temperature push trap are replaced by the deposition epitaxy, the P-type ion common injection, the selective injection of the P-type ions and the high-temperature push trap, so that the distance between the formed P-type columns is increased (namely the width of the N-type columns is increased), the concentration of majority carriers which can be stored in the N-type epitaxy layer is higher when the forward conduction is carried out, the time is longer when the reverse recovery is carried out, the reverse recovery softness is increased, and the dynamic parameter characteristics of di/dt and dv/dt are improved;
2) the manufacturing method of the invention is compatible with the existing process, and does not need to increase additional development cost.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional view of a first N-type epitaxial layer formed on an N-type substrate according to embodiment 1 of the present invention.
Fig. 2 is a schematic cross-sectional view of forming an un-diffused P-type layer and an N-type region in example 1 of the present invention.
Fig. 3 is a schematic cross-sectional structure diagram of forming a second N-type epitaxial layer on the first N-type epitaxial layer in embodiment 1 of the present invention.
Fig. 4 is a schematic cross-sectional structure diagram of forming an N-type epitaxial layer in embodiment 1 of the present invention.
Fig. 5 is a schematic cross-sectional structure diagram of forming P-type pillars and N-type pillars in embodiment 1 of the present invention.
Fig. 6 is a schematic cross-sectional structural diagram of forming a gate oxide layer and a gate polysilicon layer in embodiment 1 of the present invention.
Fig. 7 is a schematic cross-sectional structure diagram of forming a P-type body region and an N-type source region in embodiment 1 of the present invention.
Fig. 8 is a schematic cross-sectional structure diagram after etching an insulating dielectric layer according to embodiment 1 of the present invention.
Fig. 9 is a schematic cross-sectional structure diagram of forming a source metal and a drain metal in embodiment 1 of the invention.
Description of reference numerals: 1. a drain metal; 2. an N-type substrate; 3. an N-type epitaxial layer; 31. a first N-type epitaxial layer; 32. a second N-type epitaxial layer, 33, a third N-type epitaxial layer; 34. a fourth N-type epitaxial layer; 35. a fifth N-type epitaxial layer; 36. a top N-type epitaxial layer; 4. a P-type column; 5. an N-type column; 6. a gate oxide layer; 7. grid polysilicon; 8. a P-type body region; 9. an N-type source region; 10. an insulating dielectric layer; 11. a source metal; 12. a P-type layer and 13, N-type regions.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
The present invention is not limited to the following embodiments, and the drawings referred to in the following description are provided to make the content of the present invention understandable, that is, the present invention is not limited to the device structures exemplified in the drawings, and is applicable to both IGBT devices and MOSFET devices.
Example 1: taking an N-type plane gate super junction MOSFET device as an example, the first conduction type is N type, the second conduction type is P type, and the super junction device manufacturing method of multi-time epitaxy is characterized in that on a top plane, the semiconductor device comprises an active region and a terminal region surrounding the active region;
the active region comprises a plurality of super junction device units which are connected in parallel, and the manufacturing method of the super junction device units comprises the following steps:
as shown in fig. 1, the first step: selecting an N-type silicon substrate as an N-type substrate 2, and growing a first N-type epitaxial layer 31 on the upper surface of the N-type substrate 2 by adopting an epitaxial process;
as shown in fig. 2, the second step: implanting P-type impurities into the surface of the first N-type epitaxial layer 31 to form an un-diffused P-type layer 12, and then selectively implanting N-type impurities to form an un-diffused N-type region 13;
as shown in fig. 3, the third step: continuously growing a second N-type epitaxial layer 32 on the first N-type epitaxial layer, continuously and generally injecting P-type impurities into the surface of the second N-type epitaxial layer 32, and then selectively injecting N-type impurities;
in the second step and the third step, the selective injection of the N-type impurities is carried out under the shielding of a mask layer, the mask layer is subjected to photoetching to obtain a plurality of mask windows for injecting the N-type impurities, the widths and the intervals of the mask windows are the same, and the selective injection of the N-type impurities is carried out under the shielding of the mask windows;
as shown in fig. 4, the fourth step: repeating the steps, sequentially forming a third N-type epitaxial layer 33, a fourth N-type epitaxial layer 34 and a fifth N-type epitaxial layer 35, and finally growing a top N-type epitaxial layer 36 to finish the manufacture of the N-type epitaxial layer 3;
in the embodiment, 6 times of epitaxial growth are continuously performed, 5 times of general injection of P-type impurities and selective injection of N-type impurities are performed, and finally an N-type epitaxial layer 3 is formed;
as shown in fig. 5, the fifth step: carrying out high-temperature annealing on the impurity ions injected into the N-type epitaxial layer 3, and forming P-type columns 4 and N-type columns 5 which are alternately distributed in the N-type epitaxial layer 3 to finish the manufacture of the super junction structure;
as shown in fig. 6, the sixth step: thermally growing an oxide layer on the N-type epitaxial layer 3, depositing conductive polycrystalline silicon on the oxide layer, and selectively etching the conductive polycrystalline silicon and the oxide layer in sequence to obtain a gate oxide layer 6 and gate polycrystalline silicon 7 on the gate oxide layer 6;
as shown in fig. 7, the seventh step: under the shielding of the grid polysilicon 7, injecting P-type impurities in a self-alignment manner, annealing at high temperature, forming a P-type body region 8 above the P-type column 4, and then selectively injecting N-type impurities to form an N-type source region 9 positioned in the P-type body region 8;
as shown in fig. 8, the eighth step: depositing an insulating medium layer 10 on the surface of the device, selectively etching the insulating medium layer 10 to form a metal contact through hole;
as shown in fig. 9, the ninth step: and depositing metal in the metal contact through hole to obtain source metal 11, and forming drain metal 1 on the lower surface of the N-type substrate 2 to finish the manufacture of the super junction device unit.
In the embodiments, the super junction structure of the termination region and the super junction structure of the active region have the same manufacturing process, and details are not repeated here.
In embodiment 1 of the present invention, the general implantation of P-type impurities and the selective implantation of N-type impurities may be performed each time by performing epitaxial growth continuously for 6 times, and then the super junction structure and the N-type epitaxial layer 3 are formed by well pushing, and a small amount of P-type impurities may be implanted when the P-type body region 8 is formed subsequently.
The traditional manufacturing process of the multi-time epitaxial super-junction structure is formed by performing deposition epitaxy, N-type ion common injection and selective injection of P-type ions, repeating the steps for a plurality of times continuously, and then performing high-temperature well pushing, and is followed by a common VDMOS (vertical double-diffused metal oxide semiconductor) process; compared with the traditional manufacturing process of the super-junction structure, the super-junction structure is formed by depositing epitaxy, P-type ion common injection and selectively injecting N-type ions, repeating the steps for a plurality of times, then forming the super-junction structure by high-temperature well pushing, and replacing the existing multi-time epitaxy super-junction process, wherein the distance between P-type columns 4 formed by the super-junction structure is increased (namely the width of the N-type column 5 is increased), and under the condition of ensuring that BV and Rdson are not changed, the injection dosage of the P-type ions (such as boron ions) is increased, so that the concentration of majority carriers which can be stored in the N-type epitaxial layer 3 is higher when the positive direction is conducted, the time is longer when the reverse direction is recovered, the reverse recovery softness is increased, and the dynamic parameter characteristics of di/dt and dv/dt are improved; meanwhile, the manufacturing method is compatible with the existing process, and extra development cost is not required to be added.
The present invention and its embodiments have been described above, and the description is not intended to be limiting, and the embodiments shown in the drawings are only one embodiment of the present invention, and the actual structure is not limited thereto. In summary, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. A method for manufacturing a super junction device with multiple epitaxy comprises a plurality of super junction device units which are connected in parallel, and is characterized in that the method for manufacturing the super junction device units comprises the following steps:
the first step is as follows: selecting a first conductive type silicon substrate as a first conductive type substrate (2), and growing a first conductive type epitaxial layer (31) on the upper surface of the first conductive type substrate (2) by adopting an epitaxial process;
the second step is that: generally injecting second conductive type impurities into the surface of the first conductive type epitaxial layer (31) to form an un-diffused second conductive type layer (12), and then selectively injecting first conductive type impurities to form an un-diffused first conductive type region (13);
the third step: continuously growing a second first conductive type epitaxial layer (32) on the first conductive type epitaxial layer, continuously and generally injecting second conductive type impurities on the surface of the second first conductive type epitaxial layer (32), and then selectively injecting the first conductive type impurities;
the fourth step: repeating the steps, sequentially forming a third first conduction type epitaxial layer (33), a fourth first conduction type epitaxial layer (34) and a fifth first conduction type epitaxial layer (35), and finally growing a top first conduction type epitaxial layer (36) to finish the manufacture of the first conduction type epitaxial layer (3);
carrying out 6 times of epitaxial growth continuously, carrying out 5 times of common injection of second conductivity type impurities and selective injection of first conductivity type impurities, and finally forming a first conductivity type epitaxial layer (3);
the fifth step: carrying out high-temperature annealing on the impurity ions injected into the first conductive type epitaxial layer (3), and forming second conductive type columns (4) and first conductive type columns (5) which are alternately distributed in the first conductive type epitaxial layer (3);
and a sixth step: thermally growing an oxide layer on the first conductive type epitaxial layer (3), depositing conductive polycrystalline silicon on the oxide layer, and selectively etching the conductive polycrystalline silicon and the oxide layer in sequence to obtain a gate oxide layer (6) and gate polycrystalline silicon (7) positioned on the gate oxide layer (6);
the seventh step: under the shielding of the grid polysilicon (7), injecting second conductive type impurities in a self-alignment manner, annealing at high temperature, forming a second conductive type body region (8) above the second conductive type column (4), and then selectively injecting first conductive type impurities to form a first conductive type source region (9) positioned in the second conductive type body region (8);
eighth step: depositing an insulating medium layer (10) on the surface of the device, selectively etching the insulating medium layer (10) to form a metal contact through hole;
the ninth step: and depositing metal in the metal contact through hole to obtain source metal (11), and forming drain metal (1) on the lower surface of the first conduction type substrate (2).
2. The method of claim 1, wherein in the second and third steps, the selective implantation of the first conductivity type impurities is performed under the shielding of a mask layer, the mask layer is etched to obtain a plurality of mask windows for the implantation of the first conductivity type impurities, and the mask windows have the same width and spacing.
3. The method for manufacturing a multi-epitaxy super junction device according to claim 1, wherein in the fourth step, the number of times of repeating the third step is determined according to the size of a device withstand voltage.
4. The method of manufacturing a multi-epitaxial superjunction device of claim 1, wherein the superjunction device unit comprises a superjunction device unit of an N-type power semiconductor device and a superjunction device unit of a P-type power semiconductor device, and for the superjunction structure of the N-type power semiconductor device, the first conductivity type is N-type, the second conductivity type is P-type, and for the superjunction structure of the P-type power semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
5. The method of manufacturing a multi-epitaxial superjunction device of claim 1, wherein the multi-epitaxial superjunction device comprises an IGBT device and a MOSFET device.
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| CN110010693B (en) * | 2019-05-07 | 2024-03-12 | 无锡紫光微电子有限公司 | Structure of high-voltage deep trench type super-junction MOSFET and manufacturing method thereof |
| CN110299402A (en) * | 2019-07-25 | 2019-10-01 | 无锡昌德微电子股份有限公司 | A kind of VDMOS and its manufacturing method |
| CN112038236B (en) * | 2020-09-10 | 2022-03-15 | 深圳市芯电元科技有限公司 | Manufacturing method of trench MOSFET |
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| JP2001119022A (en) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| JP5659558B2 (en) * | 2010-05-20 | 2015-01-28 | 富士電機株式会社 | Manufacturing method of super junction semiconductor device |
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| JP6375743B2 (en) * | 2014-07-15 | 2018-08-22 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| CN107799419A (en) * | 2016-08-31 | 2018-03-13 | 无锡华润华晶微电子有限公司 | Super junction power device and preparation method thereof |
| CN207587736U (en) * | 2017-09-14 | 2018-07-06 | 中航（重庆）微电子有限公司 | A kind of superjunction devices |
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