CN104637821A - Manufacturing method of super junction device - Google Patents
Manufacturing method of super junction device Download PDFInfo
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- CN104637821A CN104637821A CN201510024006.7A CN201510024006A CN104637821A CN 104637821 A CN104637821 A CN 104637821A CN 201510024006 A CN201510024006 A CN 201510024006A CN 104637821 A CN104637821 A CN 104637821A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 239000010703 silicon Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000002347 injection Methods 0.000 claims abstract description 9
- 239000007924 injection Substances 0.000 claims abstract description 9
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 72
- 238000000407 epitaxy Methods 0.000 claims description 37
- 230000015572 biosynthetic process Effects 0.000 claims description 21
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 6
- 230000001105 regulatory effect Effects 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 239000002800 charge carrier Substances 0.000 claims description 4
- 238000006396 nitration reaction Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 239000000428 dust Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 238000006386 neutralization reaction Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention discloses a manufacturing method of a super junction device. The method comprises the following steps that 1, a silicon epitaxial substrate is provided, and in addition, a hard mask layer is formed; 2, a plurality of grooves are formed through photoetching; 3, N type ions with angles are injected onto the surfaces of the bottom and the silicon epitaxial substrate arranged at the bottom and the side wall of the grooves for forming an N type ion injection layer; 4, P type epitaxial layer growth is carried out, and in addition, the grooves are filled to form P type columns. The manufacturing method has the advantage that the source drain conduction resistance of the device can be reduced.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of manufacture method of super-junction device.
Background technology
Super junction (Super Junction) is made up of the P type post be alternately arranged and N-type post, charge carrier between P type post and N-type post easily exhausts mutually thus improves the puncture voltage of device, in prior art, the operational method of the super junction generally adopted is two kinds:
A kind of to arrange in pairs or groups repeatedly ion implantation for repeatedly extension, then by the method for propelling (Drive in) of once annealing, the P type trap (Well) repeatedly injected is linked to be a P type post.
Another kind of way is the extension first growing one deck or bilayer, hollowing out formation groove, then inserting P type extension in the trench and forming P type post by the method for digging groove by needing the epitaxial loayer of filling P type post.
No matter be which kind of method, capital causes a problem, that is exactly after formation P type post, due to the inevitable thermal process existed in technique, the p type impurity of P type post generally all adopts boron (B) element simultaneously, thermal process can make the B element of P district and P type post can spread to N district, thus causes concentration partially light region in P district to become large, and N district and N-type post situation less than normal occur; Simultaneously in order to obtain the higher device performance of puncture voltage, can select the extension that RS is comparatively large, finally result in device source leakage conducting resistance (RDSON) can be larger than expection.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method of super-junction device, can reduce the source and drain conducting resistance of device.
For solving the problems of the technologies described above, the manufacture method of super-junction device provided by the invention comprises following manufacturing step:
Step one, provide a N-type lightly doped silicon epitaxy substrate, form hard mask layer at described silicon epitaxy substrate surface.
Step 2, employing photoetching process define trench region, are removed by the described hard mask layer of described trench region; Multiple groove is formed for mask carries out etching to the silicon of described trench region with described hard mask layer; Each described groove and the N-type post be made up of the described silicon epitaxy substrate between each adjacent described groove are arranged alternately structure.
Step 3, with described hard mask layer for mask carry out be with angle N-type ion implantation and form a N-type implanted layer at the described silicon epitaxy substrate surface of the bottom of described groove and sidewall; The doping content of described N-type implanted layer is greater than the doping content of described silicon epitaxy substrate.
Step 4, carry out P type outer layer growth, described P type epitaxial loayer is filled described groove completely and is formed P type post by the described P type epitaxial loayer be filled in described groove, the super-junction structures that the described N-type post that each described P type post and side are formed with described N-type implanted layer is arranged alternately, the charge carrier of described P type post and side are formed with the carrier balance of the described N-type post of described N-type implanted layer; In subsequent thermal process, described N-type implanted layer forms the p type impurity of coming is spread in neutralization region from described P type post, makes the width value of described P type post and described N-type post keep stable.
Further improvement is, the resistivity of described silicon epitaxy substrate is 1 ohmcm ~ 30 ohmcm, and thickness is more than 700 microns.
Further improvement is, the technique forming the selection area being also included in described silicon epitaxy substrate before described hard mask layer and carry out injecting in P type tagma, the P type tagma of formation is arranged in the top of each described P type post and extends to the described N-type post of described P type post both sides.
Further improvement is, the threshold voltage regulating super device is injected in the threshold voltage adjustment of injecting by regulating described P type tagma.
Further improvement is, the selection area being also included in described silicon epitaxy substrate before forming described hard mask layer carries out the technique of JFET injection, and the JFET injection region of formation is positioned at the top of each described N-type post.
Further improvement is, described hard mask layer is ONO structure, comprises the first oxide layer, the second nitration case and the 3rd oxide layer that are superimposed on described silicon epitaxy substrate surface successively.
Further improvement is, the degree of depth of the described groove that step 2 is formed is 1 micron ~ 50 microns, and width is 2 microns ~ 10 microns, and the spacing of described groove and width are than being more than 1:1.
Further improvement is, the angle of the ion implantation of N-type described in step 3 is 7 degree and evenly injects respectively with 4 directions, and implanted dopant is phosphorus or arsenic, and the degree of depth being injected into described silicon epitaxy substrate surface from the sidewall of described groove is 100 dust ~ 1000 dusts.
Further improvement is, is also included in the bottom of described groove and sidewall surfaces and forms sacrificial oxide layer and again by step that described sacrificial oxide layer is removed before the described N-type ion implantation of step 3.
Further improvement is, adopts chemical mechanical milling tech to be removed by the described P type epitaxial loayer outside described groove in step 4.
Further improvement also comprises the steps:
Step 5, the field oxygen layer of the terminal of super-junction device of being formed on described super-junction structures surface.
Step 6, form gate dielectric layer and polysilicon gate successively on described super-junction structures surface.
Step 7, carry out source injection.
Step 8, formation interlayer film and the contact hole through described interlayer film.
Step 9, formation front metal layer, carry out chemical wet etching to described front metal layer and form source electrode and grid.
Further improvement is, super-junction device is super junction N-type MOSFET element, also comprises the steps:
Step 10, grinding back surface is carried out to described silicon epitaxy substrate.
Step 11, form N+ impure drain region at described silicon epitaxy substrate back.
Step 12, formation metal layer on back draw drain electrode.
Further improvement is, the p type impurity of described P type post comprises boron element.
The present invention is by after groove is formed, before carrying out extension filling groove, carry out the N-type ion implantation being with angle, the N-type implanted layer that N-type ion implantation is formed can improve the N-type doping content of N-type post side, the N-type implanted layer of this higher-doped concentration can neutralize and spread the p type impurity of coming as the region of boron from P type post, also can prevent the p type impurity of P type post from diffusing in N-type post, avoid occurring that P type post width broadens, to adulterate narrowed width that is thin out and N-type post, the situation of adulterating thin out occurs, the width value of P type post and N-type post is made to keep stable, doping content also can keep stable, this can reduce the source and drain conducting resistance of device greatly.
In addition, N-type implanted layer itself has the doping content of high-pressure N-shaped post inside, and the resistivity of N-type implanted layer localized positions also can be made to reduce, thus further reduces the source and drain conducting resistance of device.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is embodiment of the present invention method flow diagram;
Fig. 2 A-Fig. 2 C is the device architecture figure in each step of embodiment of the present invention method;
Fig. 3 is the composition schematic diagram of the source and drain conducting resistance (RDSON) of super junction N-type MOSFET element;
Fig. 4 is that the test result of the super junction N-type MOSFET element of embodiment of the present invention method formation and the super junction N-type MOSFET element RDSON of existing method formation compares.
Embodiment
As shown in Figure 1, be embodiment of the present invention method flow diagram; As shown in Fig. 2 A to Fig. 2 C, be the device architecture figure in each step of embodiment of the present invention method; The super junction N-type MOSFET element that super-junction device in the embodiment of the present invention take operating voltage as 600V, electric current is 5 peaces illustrates for example, and the manufacture method of embodiment of the present invention super-junction device comprises following manufacturing step:
Step one, as shown in Figure 2 A, provide a N-type lightly doped silicon epitaxy substrate 1.In the embodiment of the present invention, described silicon epitaxy substrate 1 is zone melting and refining silicon epitaxial substrate.The resistivity of described silicon epitaxy substrate 1 is 1 ohmcm ~ 30 ohmcm, and thickness is more than 700 microns.
Carry out the technique of JFET injection at the selection area of described silicon epitaxy substrate 1, the JFET injection region 6 of formation is positioned at the top of each described N-type post formed.
Carry out P type tagma 7 at the selection area of described silicon epitaxy substrate 1 to inject, the P type tagma 7 of formation is arranged in the top of each P type post 9 of follow-up formation and extends to the N-type post of P type post 9 both sides.
The threshold voltage regulating super device is injected in the threshold voltage adjustment of injecting by regulating described P type tagma 7.
Hard mask layer is formed on described silicon epitaxy substrate 1 surface.Described hard mask layer is ONO structure, comprises the first oxide layer 2, second nitration case 3 and the 3rd oxide layer 4 that are superimposed on described silicon epitaxy substrate 1 surface successively.Wherein the Thickness Design demand fulfillment of the first oxide layer 2 and the second nitration case 3 stops the minimum thickness of the energy of the N-type ion implantation of subsequent step three.
Step 2, as shown in Figure 2 A, adopts photoetching process to define trench region, is removed by the described hard mask layer of described trench region; Multiple groove is formed for mask carries out etching to the silicon of described trench region with described hard mask layer; Each described groove and the N-type post be made up of the described silicon epitaxy substrate 1 between each adjacent described groove are arranged alternately structure.
In the embodiment of the present invention, the degree of depth of the described groove of formation is 1 micron ~ 50 microns, and width is 2 microns ~ 10 microns, and the spacing of described groove and width are than being more than 1:1.
Step 3, as shown in Figure 2 A, forms sacrificial oxide layer 5 in the bottom of described groove and sidewall surfaces, is removed by described sacrificial oxide layer 5 more afterwards, can eliminate the bottom of groove and the defect of sidewall surfaces like this, make the bottom of groove and sidewall surfaces smooth.
As shown in Figure 2 B, carry out being with the N-type ion implantation of angle for mask with described hard mask layer and form a N-type implanted layer 8 on described silicon epitaxy substrate 1 surface of the bottom of described groove and sidewall; The doping content of described N-type implanted layer 8 is greater than the doping content of described silicon epitaxy substrate 1.
Be preferably, further improvement is, the angle of the ion implantation of N-type described in step 3 is 7 degree and evenly injects respectively with 4 directions, and implanted dopant is phosphorus or arsenic, and the degree of depth being injected into described silicon epitaxy substrate surface from the sidewall of described groove is 100 dust ~ 1000 dusts.
Step 4, as shown in Figure 2 B, carry out P type outer layer growth, described P type epitaxial loayer fills described groove completely; Chemical mechanical milling tech is adopted to be removed by the described P type epitaxial loayer outside described groove.P type post 9 is formed by the described P type epitaxial loayer be filled in described groove.The p type impurity of described P type post 9 comprises boron element.
The super-junction structures that the described N-type post that each described P type post 9 and side are formed with described N-type implanted layer 8 is arranged alternately, the charge carrier of described P type post 9 and side are formed with the carrier balance of the described N-type post of described N-type implanted layer 8; In subsequent thermal process, described N-type implanted layer 8 forms the p type impurity of coming is spread in neutralization region from described P type post 9, makes the width value of described P type post 9 and described N-type post keep stable.
Step 5, the field oxygen layer of the terminal of super-junction device of being formed on described super-junction structures surface.
Step 6, form gate dielectric layer successively as gate oxide 10 and polysilicon gate 11 on described super-junction structures surface.
Step 7, carry out source inject formed source region 12.
Step 8, formation interlayer film and the contact hole through described interlayer film.
Step 9, formation front metal layer, carry out chemical wet etching to described front metal layer and form source electrode and grid.
Step 10, grinding back surface is carried out to described silicon epitaxy substrate 1.
Step 11, form N+ impure drain region at described silicon epitaxy substrate 1 back side.
Step 12, formation metal layer on back draw drain electrode.
Except the super junction N-type MOSFET element described by the embodiment of the present invention, embodiment of the present invention method also can be applied to other super-junction device, as super junction insulated gate bipolar transistor (IGBT) device, and super junction diode etc.
As shown in Figure 3, be the composition schematic diagram of RDSON of super junction N-type MOSFET element; The substrate 101 adulterated by N+ form drain region and from the back side draw drain electrode, N-layer 101 and P-layer 102 form the super-junction structures be alternately arranged, N-layer 101 when conducting as drift region; P trap 104 forms tagma, and N+ district 105 forms source region and draws source electrode from front, is formed with gate oxide and polysilicon gate 106 above body surface.RDSON refers to that super junction N-type MOSFET element forms to the resistance draining from source electrode when conducting, can represent with following formula:
RDSON＝Rs+Rn+Rch+Rj+Rd+Rsub。
Wherein Rs is the contact resistance of source electrode, and Rn is the source region resistance in N+ district 105, and Rch is channel resistance, and Rj is JFET resistance, and Rd is drift zone resistance, and Rsub is the resistance in resistance substrate also i.e. drain region.
Reducing RDSON can from six resistance consideration above.
The present invention by after groove is formed, carry out extension filling groove before, carry out the N-type ion implantation being with angle, the width value of P type post and N-type post can be made to keep stable, and doping content also can keep stable, thus the Rd resistance that can fall in above-mentioned formula, so greatly can reduce the RDSON of device.
As shown in Figure 4, be that the test result of super junction N-type MOSFET element RDSON that the super junction N-type MOSFET element that formed of embodiment of the present invention method and existing method are formed compares.The test value of the RDSON in dotted line frame 201 region is all the test result of the super junction N-type MOSFET element RDSON that existing method is formed, the test value of the RDSON in dotted line frame 202 region is all the test result of the super junction N-type MOSFET element RDSON that embodiment of the present invention method is formed, and in Fig. 4, a test point at each position place represents the test value being formed at same on-chip identity unit.Can find out, RDSON is decreased to 0.263 ohm from 0.343 ohm, less by about 25% than originally.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (13)
1. a manufacture method for super-junction device, is characterized in that, comprises following manufacturing step:
Step one, provide a N-type lightly doped silicon epitaxy substrate, form hard mask layer at described silicon epitaxy substrate surface;
Step 2, employing photoetching process define trench region, are removed by the described hard mask layer of described trench region; Multiple groove is formed for mask carries out etching to the silicon of described trench region with described hard mask layer; Each described groove and the N-type post be made up of the described silicon epitaxy substrate between each adjacent described groove are arranged alternately structure;
Step 3, with described hard mask layer for mask carry out be with angle N-type ion implantation and form a N-type implanted layer at the described silicon epitaxy substrate surface of the bottom of described groove and sidewall; The doping content of described N-type implanted layer is greater than the doping content of described silicon epitaxy substrate;
Step 4, carry out P type outer layer growth, described P type epitaxial loayer is filled described groove completely and is formed P type post by the described P type epitaxial loayer be filled in described groove, the super-junction structures that the described N-type post that each described P type post and side are formed with described N-type implanted layer is arranged alternately, the charge carrier of described P type post and side are formed with the carrier balance of the described N-type post of described N-type implanted layer; In subsequent thermal process, described N-type implanted layer forms the p type impurity of coming is spread in neutralization region from described P type post, makes the width value of described P type post and described N-type post keep stable.
2. the manufacture method of super-junction device as claimed in claim 1, is characterized in that: the resistivity of described silicon epitaxy substrate is 1 ohmcm ~ 30 ohmcm, and thickness is more than 700 microns.
3. the manufacture method of super-junction device as claimed in claim 1, it is characterized in that: the technique forming the selection area being also included in described silicon epitaxy substrate before described hard mask layer and carry out injecting in P type tagma, the P type tagma of formation is arranged in the top of each described P type post and extends to the described N-type post of described P type post both sides.
4. the manufacture method of super-junction device as claimed in claim 3, is characterized in that: the threshold voltage regulating super device is injected in the threshold voltage adjustment of injecting by regulating described P type tagma.
5. the manufacture method of super-junction device as claimed in claim 1, it is characterized in that: the selection area being also included in described silicon epitaxy substrate before forming described hard mask layer carries out the technique of JFET injection, and the JFET injection region of formation is positioned at the top of each described N-type post.
6. the manufacture method of super-junction device as claimed in claim 1, is characterized in that: described hard mask layer is ONO structure, comprises the first oxide layer, the second nitration case and the 3rd oxide layer that are superimposed on described silicon epitaxy substrate surface successively.
7. the manufacture method of super-junction device as claimed in claim 1, is characterized in that: the degree of depth of the described groove that step 2 is formed is 1 micron ~ 50 microns, and width is 2 microns ~ 10 microns, and the spacing of described groove and width are than being more than 1:1.
8. the manufacture method of super-junction device as claimed in claim 1, it is characterized in that: the angle of the ion implantation of N-type described in step 3 is 7 degree and evenly injects respectively with 4 directions, implanted dopant is phosphorus or arsenic, and the degree of depth being injected into described silicon epitaxy substrate surface from the sidewall of described groove is 100 dust ~ 2000 dusts.
9. the manufacture method of super-junction device as claimed in claim 1, is characterized in that: be also included in the bottom of described groove and sidewall surfaces before the described N-type ion implantation of step 3 and form sacrificial oxide layer and again by step that described sacrificial oxide layer is removed.
10. the manufacture method of super-junction device as claimed in claim 1, is characterized in that: adopt chemical mechanical milling tech to be removed by the described P type epitaxial loayer outside described groove in step 4.
The manufacture method of 11. super-junction devices as claimed in claim 1, is characterized in that, also comprise the steps:
Step 5, the field oxygen layer of the terminal of super-junction device of being formed on described super-junction structures surface;
Step 6, form gate dielectric layer and polysilicon gate successively on described super-junction structures surface;
Step 7, carry out source injection;
Step 8, formation interlayer film and the contact hole through described interlayer film;
Step 9, formation front metal layer, carry out chemical wet etching to described front metal layer and form source electrode and grid.
The manufacture method of 12. super-junction devices as claimed in claim 11, is characterized in that: super-junction device is super junction N-type MOSFET element, also comprises the steps:
Step 10, grinding back surface is carried out to described silicon epitaxy substrate;
Step 11, form N+ impure drain region at described silicon epitaxy substrate back;
Step 12, formation metal layer on back draw drain electrode.
The manufacture method of 13. super-junction devices as claimed in claim 1, is characterized in that: the p type impurity of described P type post comprises boron element.
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Cited By (10)
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| CN105575781A (en) * | 2016-01-29 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for trench type super junction |
| CN105957896A (en) * | 2016-06-24 | 2016-09-21 | 上海华虹宏力半导体制造有限公司 | Super-junction power device and manufacturing method thereof |
| CN106847886A (en) * | 2017-03-16 | 2017-06-13 | 上海华虹宏力半导体制造有限公司 | The manufacture method of groove-shaped super junction |
| CN107134492A (en) * | 2016-02-26 | 2017-09-05 | 苏州东微半导体有限公司 | Super junction power device and its manufacture method |
| CN107919399A (en) * | 2017-12-13 | 2018-04-17 | 深圳市晶特智造科技有限公司 | Half superjunction devices and its manufacture method |
| CN108122756A (en) * | 2016-11-29 | 2018-06-05 | 深圳尚阳通科技有限公司 | The manufacturing method and device architecture of superjunction devices |
| CN109841515A (en) * | 2017-11-24 | 2019-06-04 | 帅群微电子股份有限公司 | The method for making semiconductor element |
| CN111370297A (en) * | 2020-04-02 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction |
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| CN105575781A (en) * | 2016-01-29 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for trench type super junction |
| CN105575781B (en) * | 2016-01-29 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of groove-shaped super junction |
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| CN107134492B (en) * | 2016-02-26 | 2020-01-14 | 苏州东微半导体有限公司 | Super junction power device and manufacturing method thereof |
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| CN105957896B (en) * | 2016-06-24 | 2019-02-05 | 上海华虹宏力半导体制造有限公司 | Super junction power device and its manufacturing method |
| CN108122756A (en) * | 2016-11-29 | 2018-06-05 | 深圳尚阳通科技有限公司 | The manufacturing method and device architecture of superjunction devices |
| CN106847886A (en) * | 2017-03-16 | 2017-06-13 | 上海华虹宏力半导体制造有限公司 | The manufacture method of groove-shaped super junction |
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| CN109841515B (en) * | 2017-11-24 | 2022-04-15 | 帅群微电子股份有限公司 | Method for manufacturing semiconductor element |
| CN107919399A (en) * | 2017-12-13 | 2018-04-17 | 深圳市晶特智造科技有限公司 | Half superjunction devices and its manufacture method |
| CN111370297A (en) * | 2020-04-02 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction |
| CN111883422A (en) * | 2020-07-16 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of super junction device |
| CN112909075A (en) * | 2021-01-28 | 2021-06-04 | 滁州华瑞微电子科技有限公司 | Trench MOSFET with charge balance structure and manufacturing method thereof |
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