CN104637821B - The manufacturing method of super-junction device - Google Patents
The manufacturing method of super-junction device Download PDFInfo
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- CN104637821B CN104637821B CN201510024006.7A CN201510024006A CN104637821B CN 104637821 B CN104637821 B CN 104637821B CN 201510024006 A CN201510024006 A CN 201510024006A CN 104637821 B CN104637821 B CN 104637821B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000000407 epitaxy Methods 0.000 claims abstract description 39
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 7
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 84
- 238000000034 method Methods 0.000 claims description 26
- 238000002347 injection Methods 0.000 claims description 17
- 239000007924 injection Substances 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000000203 mixture Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 4
- 238000006396 nitration reaction Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention discloses a kind of manufacturing methods of super-junction device, including step：Step 1: providing a silicon epitaxy substrate and forming hard mask layer；Step 2: chemical wet etching forms multiple grooves；Step 3: carry out the N-type ion implanting with angle forms a N-type implanted layer in the silicon epitaxy substrate surface of the bottom and side wall of groove；Step 4: carrying out p-type outer layer growth and filling groove formation p-type column.The present invention can reduce the source and drain conducting resistance of device.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, more particularly to a kind of system of super-junction device
Make method.
Background technology
Super junction (Super Junction) is made of alternately arranged p-type column and N-type column, between p-type column and N-type column
Carrier is easy to exhaust to improve the breakdown voltage of device, in the prior art, the operator of the super junction generally used mutually
Method is two kinds：
One kind is the multiple ion implanting of multiple extension collocation, then will by the method for propulsion of once annealing (Drive in)
The p-type trap (Well) repeatedly injected is linked to be a p-type column.
Another way is first to grow one layer or double-deck extension, will need to fill p-type column by the method for digging groove
Epitaxial layer hollow out to form groove, then in the trench filling p-type be epitaxially formed p-type column.
Either which kind of method can all lead to a problem, that is, after forming p-type column, due to existing in technique
Inevitable thermal process, while the p type impurity of p-type column is generally used boron (B) element, and thermal process can make the areas P i.e. p-type
The B element of column can be spread to the areas N, be become larger so as to cause the partially light region of the areas P concentration, and the areas N, that is, N-type column situation less than normal occurs；Together
When in order to obtain the higher device performance of breakdown voltage, the more big extensions of RS can be selected, eventually led to the conducting of device source and drain
Resistance (RDSON) can be more larger than expected.
Invention content
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of super-junction device, can reduce the source of device
Leak conducting resistance.
In order to solve the above technical problems, the manufacturing method of super-junction device provided by the invention includes following manufacturing step：
Step 1: providing the silicon epitaxy substrate that a N-type is lightly doped, hard mask layer is formed in the silicon epitaxy substrate surface.
Step 2: defining trench region using photoetching process, the hard mask layer of the trench region is removed；With
The hard mask layer is that mask performs etching the silicon of the trench region to form multiple grooves；Each groove and by each adjacent
The N-type column of silicon epitaxy substrate composition between the groove is arranged alternately structure.
Step 3: carrying out the N-type ion implanting with angle using the hard mask layer as mask and in the bottom of the groove
A N-type implanted layer is formed with the silicon epitaxy substrate surface of side wall；The doping concentration of the N-type implanted layer is more than outside the silicon
The doping concentration of epitaxial substrate.
Step 4: carrying out p-type outer layer growth, the p-type epitaxial layer is filled up completely the groove and described in being filled in
The p-type epitaxial layer in groove forms p-type column, and each p-type column and side are formed with the N-type of the N-type implanted layer
The super-junction structures that column is arranged alternately, the carrier of the p-type column and side are formed with the N-type of the N-type implanted layer
The carrier balance of column；During subsequent thermal, the N-type implanted layer forms a neutralization and diffuses through the p-type come from the p-type column
The region of impurity makes the width value of the p-type column and the N-type column keep stablizing.
A further improvement is that the resistivity of the silicon epitaxy substrate is the ohmcm of 1 ohmcm~30, thickness
It is 700 microns or more.
A further improvement is that further including the selection area in the silicon epitaxy substrate before forming the hard mask layer
The technique for carrying out PXing Ti area's injections, the areas PXing Ti of formation are located at the top of each p-type column and extend to p-type column both sides
The N-type column in.
A further improvement is that super to adjust by adjusting the threshold voltage adjustment injection in the areas the PXing Ti injection
The threshold voltage of device.
A further improvement is that further including the selection area in the silicon epitaxy substrate before forming the hard mask layer
The technique for carrying out JFET injections, the injection regions JFET of formation are located at the top of each N-type column.
A further improvement is that the hard mask layer is ONO structure, including it is sequentially overlapped in the silicon epitaxy substrate surface
The first oxide layer, the second nitration case and third oxide layer.
A further improvement is that the depth for the groove that step 2 is formed is 1 micron~50 microns, width is 2 microns
~10 microns, spacing and the width ratio of the groove are 1:1 or more.
A further improvement is that the angle of N-type ion implanting described in step 3 is 7 degree and is distinguished with 4 directions uniform
Injection, implanted dopant is phosphorus or arsenic, from the side wall of the groove be injected into the silicon epitaxy substrate surface depth be 100 angstroms~
1000 angstroms.
A further improvement is that further including the bottom and side wall in the groove before the N-type ion implanting of step 3
The step of surface forms sacrificial oxide layer and again removes the sacrificial oxide layer.
A further improvement is that using chemical mechanical milling tech by the p-type extension outside the groove in step 4
Layer removal.
A further improvement is that further including following steps：
Step 5: forming the field oxygen layer of the terminal of super-junction device on the super-junction structures surface.
Step 6: sequentially forming gate dielectric layer and polysilicon gate on the super-junction structures surface.
Step 7: carrying out source injection.
Step 8: forming interlayer film and the contact hole across the interlayer film.
Step 9: forming front metal layer, carrying out chemical wet etching to the front metal layer forms source electrode and grid.
A further improvement is that super-junction device is super junction N-type MOSFET element, further include following steps：
Step 10: carrying out grinding back surface to the silicon epitaxy substrate.
Step 11: forming N+ impure drain regions in the silicon epitaxy substrate back.
Step 12: forming metal layer on back draws drain electrode.
A further improvement is that the p type impurity of the p-type column includes boron element.
The present invention is by after groove is formed, before carrying out extension filling groove, carrying out the N-type ion implanting with angle, N-type
The N-type implanted layer that ion implanting is formed can improve the n-type doping concentration of N-type column side, the N-type implanted layer of the higher-doped concentration
The region for diffusing through the p type impurity such as boron come from p-type column can be neutralized, also can prevent the p type impurity of p-type column from diffusing into
In N-type column, avoids the occurrence of p-type column width and broadens, adulterates thin out and N-type column width and narrow, adulterate thin out situation and occur,
The width value of p-type column and N-type column is set to keep stablizing, doping concentration can also keep stable, this source and drain that can substantially reduce device is led
Be powered resistance.
In addition, N-type implanted layer itself has the doping concentration inside high-pressure N-shaped column, it can also make N-type implanted layer part position
Setting the resistivity at place reduces, to further reduce the source and drain conducting resistance of device.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is flow chart of the embodiment of the present invention；
Fig. 2A-Fig. 2 C are the device junction compositions in each step of present invention method；
Fig. 3 is the composition schematic diagram of the source and drain conducting resistance (RDSON) of super junction N-type MOSFET element；
Fig. 4 is the super junction N that the super junction N-type MOSFET element that present invention method is formed and existing method are formed
The test result of type MOSFET element RDSON compares.
Specific implementation mode
As shown in Figure 1, being flow chart of the embodiment of the present invention；As shown in Fig. 2A to Fig. 2 C, it is embodiment of the present invention side
Device junction composition in each step of method；Super-junction device in the embodiment of the present invention with operating voltage is 600V, electric current is 5 peaces
Illustrate for super junction N-type MOSFET element, the manufacturing method of super-junction device of the embodiment of the present invention includes following manufacturing step：
Step 1: as shown in Figure 2 A, providing the silicon epitaxy substrate 1 that a N-type is lightly doped.In the embodiment of the present invention, the silicon
Epitaxial substrate 1 is zone melting and refining silicon epitaxial substrate.The resistivity of the silicon epitaxy substrate 1 is the ohmcm of 1 ohmcm~30,
Thickness is 700 microns or more.
The technique of JFET injections is carried out in the selection area of the silicon epitaxy substrate 1, the injection regions JFET 7 of formation are located at shape
The top for each N-type column being shaped as.
The areas PXing Ti 6 are carried out in the selection area of the silicon epitaxy substrate 1 to inject, the areas PXing Ti 6 of formation are located at follow-up shape
At each p-type column 9 top and extend in the N-type column of 9 both sides of p-type column.
The threshold voltage of super device is adjusted by adjusting the threshold voltage adjustment injection in the injection of the areas PXing Ti 6.
Hard mask layer is formed on 1 surface of silicon epitaxy substrate.The hard mask layer is ONO structure, including is sequentially overlapped
In first oxide layer 2 on 1 surface of silicon epitaxy substrate, the second nitration case 3 and third oxide layer 4.2 He of wherein the first oxide layer
The thickness design of second nitration case 3 needs the minimum thickness for meeting the energy for the N-type ion implanting for stopping subsequent step three.
Step 2: as shown in Figure 2 A, defining trench region using photoetching process, described by the trench region is covered firmly
Film layer removes；The silicon of the trench region is performed etching to form multiple grooves using the hard mask layer as mask；Each ditch
Slot and the N-type column being made of the silicon epitaxy substrate 1 between each adjacent groove are arranged alternately structure.
In the embodiment of the present invention, the depth of the groove of formation is 1 micron~50 microns, and width is 2 microns~10 micro-
Spacing and the width ratio of rice, the groove are 1:1 or more.
Step 3: as shown in Figure 2 A, forming sacrificial oxide layer 5 on the bottom and side wall surface of the groove, again later
The sacrificial oxide layer 5 removes, and can eliminate the defect on the bottom and side wall surface of groove in this way, make the bottom and side wall table of groove
Face is smooth.
As shown in Figure 2 B, using the hard mask layer as mask N-type ion implanting of the progress with angle and in the groove
1 surface of silicon epitaxy substrate of bottom and side wall forms a N-type implanted layer 8；The doping concentration of the N-type implanted layer 8 is more than
The doping concentration of the silicon epitaxy substrate 1.
Preferably, a further improvement is that, the angle of N-type ion implanting described in step 3 is 7 degree and with 4 directions point
It is not uniformly injected into, implanted dopant is phosphorus or arsenic, and the depth that the silicon epitaxy substrate surface is injected into from the side wall of the groove is
100 angstroms~1000 angstroms.
Step 4: as shown in Figure 2 B, carrying out p-type outer layer growth, the p-type epitaxial layer is filled up completely the groove；It adopts
The p-type epitaxial layer outside the groove is removed with chemical mechanical milling tech.By the p-type being filled in the groove
Epitaxial layer forms p-type column 9.The p type impurity of the p-type column 9 includes boron element.
Each p-type column 9 and side are formed with the super junction that the N-type column of the N-type implanted layer 8 is arranged alternately
Structure, the carrier of the p-type column 9 and side are formed with the carrier balance of the N-type column of the N-type implanted layer 8；Follow-up
In thermal process, the N-type implanted layer 8 forms one and neutralizes the region for diffusing through the p type impurity come from the p-type column 9, makes the P
The width value of type column 9 and the N-type column keeps stablizing.
Step 5: forming the field oxygen layer of the terminal of super-junction device on the super-junction structures surface.
Step 6: sequentially forming gate dielectric layer such as gate oxide 10 and polysilicon gate 11 on the super-junction structures surface.
Step 7: the source of progress is injected to form source region 12.
Step 8: forming interlayer film and the contact hole across the interlayer film.
Step 9: forming front metal layer, carrying out chemical wet etching to the front metal layer forms source electrode and grid.
Step 10: carrying out grinding back surface to the silicon epitaxy substrate 1.
Step 11: forming N+ impure drain regions at 1 back side of silicon epitaxy substrate.
Step 12: forming metal layer on back draws drain electrode.
In addition to super junction N-type MOSFET element described in the embodiment of the present invention, present invention method can also be applied
In other super-junction devices, such as super junction insulated gate bipolar transistor (IGBT) device, super junction diode etc..
As shown in figure 3, being the composition schematic diagram of the RDSON of super junction N-type MOSFET element；The substrate 101 adulterated by N+
It forms drain region and is drawn from the back side and drained, N- layers 102 and P- layers 103 form alternately arranged super-junction structures, and N- layers 102 are being led
As drift region when logical；P-well 104 forms body area, and the areas N+ 105 form source region and draw source electrode from front, above body surface
It is formed with gate oxide and polysilicon gate 106.RDSON refers to super junction N-type MOSFET element in conducting from source electrode to drain electrode
Between resistance composition, can be indicated with following formula：
RDSON=Rs+Rn+Rch+Rj+Rd+Rsub.
Wherein Rs is the contact resistance of source electrode, and Rn is the source region resistance in the areas N+ 105, and Rch is channel resistance, and Rj is JFET electricity
Resistance, Rd are drift zone resistance, and Rsub is resistance substrate namely the resistance in drain region.
Reducing RDSON can consider from six resistance above.
The present invention is by after groove is formed, before carrying out extension filling groove, carrying out the N-type ion implanting with angle, energy
The width value of p-type column and N-type column is set to keep stablizing, doping concentration can also keep stable, so as to drop the electricity of the Rd in above-mentioned formula
Resistance, so the RDSON of device can be substantially reduced.
As shown in figure 4, being the super junction N-type MOSFET element and existing method formation that present invention method is formed
The test result of super junction N-type MOSFET element RDSON compares.The test value of RDSON in 201 region of dotted line frame is all existing
The test result for the super junction N-type MOSFET element RDSON that method is formed, the test value of the RDSON in 202 region of dotted line frame is all
For the test result for the super junction N-type MOSFET element RDSON that present invention method is formed, in Fig. 4 at each position
One test point indicates the test value for the identity unit being formed on same substrate.As can be seen that RDSON subtracts from 0.343 ohm
It is as low as 0.263 ohm, smaller by about 25% than original.
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (12)
1. a kind of manufacturing method of super-junction device, which is characterized in that including following manufacturing step：
Step 1: providing the silicon epitaxy substrate that a N-type is lightly doped, hard mask layer is formed in the silicon epitaxy substrate surface；
Step 2: defining trench region using photoetching process, the hard mask layer of the trench region is removed；With described
Hard mask layer is that mask performs etching the silicon of the trench region to form multiple grooves；Each groove and by each adjacent described
The N-type column of silicon epitaxy substrate composition between groove is arranged alternately structure；
Step 3: carrying out the N-type ion implanting with angle using the hard mask layer as mask and in the bottom and side of the groove
The silicon epitaxy substrate surface of wall forms a N-type implanted layer；The doping concentration of the N-type implanted layer is more than the silicon epitaxy base
The doping concentration of piece；
Step 4: carrying out p-type outer layer growth, the p-type epitaxial layer is filled up completely the groove and by being filled in the groove
The interior p-type epitaxial layer forms p-type column, and the N-type column that each p-type column and side are formed with the N-type implanted layer is in
Alternately arranged super-junction structures, the carrier of the p-type column and side are formed with the N-type column of the N-type implanted layer
Carrier balance；
Further include carrying out the works of PXing Ti area's injections in the selection area of the silicon epitaxy substrate before forming the hard mask layer
Skill, the areas PXing Ti inject corresponding selection area and are located at the top for each p-type column being subsequently formed and extend to the P
In the N-type column of type column both sides and the extension terminal in the areas PXing Ti is located at the silicon epitaxy substrate in the N-type column
In；During subsequent thermal, the N-type implanted layer forms one and neutralizes the region for diffusing through the p type impurity come from the p-type column,
The position of the impurity of the p-type column diffusion is set to be fixed in the thickness range of the N-type implanted layer, to make in the N-type column
The silicon epitaxy substrate width value and doping concentration all keep stable, to reduce the source and drain conducting resistance of device.
2. the manufacturing method of super-junction device as described in claim 1, it is characterised in that：The resistivity of the silicon epitaxy substrate is
The ohmcm of 1 ohmcm~30, thickness are 700 microns or more.
3. the manufacturing method of super-junction device as described in claim 1, it is characterised in that：By adjusting the areas the PXing Ti injection
In threshold voltage adjustment injection adjust the threshold voltage of super device.
4. the manufacturing method of super-junction device as described in claim 1, it is characterised in that：Before forming the hard mask layer also
The selection area for being included in the silicon epitaxy substrate carries out the technique of JFET injections, and the injection regions JFET of formation are located at each N
The top of type column.
5. the manufacturing method of super-junction device as described in claim 1, it is characterised in that：The hard mask layer is ONO structure, packet
It includes and is sequentially overlapped the first oxide layer in the silicon epitaxy substrate surface, the second nitration case and third oxide layer.
6. the manufacturing method of super-junction device as described in claim 1, it is characterised in that：The depth for the groove that step 2 is formed
Degree is 1 micron~50 microns, and width is 2 microns~10 microns, and spacing and the width ratio of the groove are 1:1 or more.
7. the manufacturing method of super-junction device as described in claim 1, it is characterised in that：N-type ion implanting described in step 3
Angle be 7 degree and to be uniformly injected into respectively with 4 directions, implanted dopant is phosphorus or arsenic, and institute is injected into from the side wall of the groove
The depth for stating silicon epitaxy substrate surface is 100 angstroms~2000 angstroms.
8. the manufacturing method of super-junction device as described in claim 1, it is characterised in that：The N-type ion implanting of step 3
Before further include being formed sacrificial oxide layer and again to remove the sacrificial oxide layer on the bottom and side wall surface of the groove
Step.
9. the manufacturing method of super-junction device as described in claim 1, it is characterised in that：Chemical mechanical grinding is used in step 4
Technique removes the p-type epitaxial layer outside the groove.
10. the manufacturing method of super-junction device as described in claim 1, which is characterized in that further include following steps：
Step 5: forming the field oxygen layer of the terminal of super-junction device on the super-junction structures surface；
Step 6: sequentially forming gate dielectric layer and polysilicon gate on the super-junction structures surface；
Step 7: carrying out source injection；
Step 8: forming interlayer film and the contact hole across the interlayer film；
Step 9: forming front metal layer, carrying out chemical wet etching to the front metal layer forms source electrode and grid.
11. the manufacturing method of super-junction device as claimed in claim 10, it is characterised in that：Super-junction device is super junction N-type
MOSFET element further includes following steps：
Step 10: carrying out grinding back surface to the silicon epitaxy substrate；
Step 11: forming N+ impure drain regions in the silicon epitaxy substrate back；
Step 12: forming metal layer on back draws drain electrode.
12. the manufacturing method of super-junction device as described in claim 1, it is characterised in that：The p type impurity of the p-type column includes
Boron element.
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|---|---|---|---|---|
| CN105575781B (en) * | 2016-01-29 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of groove-shaped super junction |
| CN107134492B (en) * | 2016-02-26 | 2020-01-14 | 苏州东微半导体有限公司 | Super junction power device and manufacturing method thereof |
| CN105957896B (en) * | 2016-06-24 | 2019-02-05 | 上海华虹宏力半导体制造有限公司 | Super junction power device and its manufacturing method |
| CN108122756B (en) * | 2016-11-29 | 2020-04-24 | 深圳尚阳通科技有限公司 | Super junction device manufacturing method and device structure |
| CN106847886A (en) * | 2017-03-16 | 2017-06-13 | 上海华虹宏力半导体制造有限公司 | The manufacture method of groove-shaped super junction |
| CN109841515B (en) * | 2017-11-24 | 2022-04-15 | 帅群微电子股份有限公司 | Method for manufacturing semiconductor element |
| CN107919399A (en) * | 2017-12-13 | 2018-04-17 | 深圳市晶特智造科技有限公司 | Half superjunction devices and its manufacture method |
| CN111370297A (en) * | 2020-04-02 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction |
| CN111883422A (en) * | 2020-07-16 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of super junction device |
| CN112909075A (en) * | 2021-01-28 | 2021-06-04 | 滁州华瑞微电子科技有限公司 | Trench MOSFET with charge balance structure and manufacturing method thereof |
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| US20050242411A1 (en) * | 2004-04-29 | 2005-11-03 | Hsuan Tso | [superjunction schottky device and fabrication thereof] |
| JP5011881B2 (en) * | 2006-08-11 | 2012-08-29 | 株式会社デンソー | Manufacturing method of semiconductor device |
| JP2008182054A (en) * | 2007-01-25 | 2008-08-07 | Toshiba Corp | Semiconductor device |
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