KR20130119873A - Power device and method for fabricating the same - Google Patents

Abstract

A power device and a method for manufacturing the same according to the technical concept of the present invention are provided to have a field stop layer based on a semiconductor substrate between a collector region and a drift region in the structure of FS-IGBT, easily control the thickness of the field stop layer, and impurity concentrations in the collector region, and improve the function of the field stop layer. The power device comprises: a field stop layer which is formed on the basis of a first conductive semiconductor substrate; an implanted field stop layer which is formed on the field stop layer through a first conductive ion implant and has a part having concentration higher than that of the field stop layer; a drift region which is formed on the implanted field stop layer by growing a first conductive epitaxial layer and has concentration lower than that of the field stop layer; a base region of a second conductive type which is formed on the upper part of the drift region; an emitter region of a first conductive type which is formed on a surface part in a base region; a gate electrode which is formed by interposing a gate insulating layer on the drift region, the base region, and the emitter region; and a collector region of a second conductive type which is formed on the lower part of the field stop layer.

Description

Power device and method for manufacturing the same {Power device and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power device, and more particularly, to a power device using a semiconductor substrate as a field stop layer, and growing a epitaxial layer on the substrate to form a drift region, and a manufacturing method thereof.

BACKGROUND ART [0002] Insulated gate bipolar transistors (IGBTs) have been attracting attention as power semiconductor devices that combine high-speed switching characteristics of high-power MOSFETs and high power characteristics of bipolar junction transistors (BJTs). Among various types of IGBT structures, a field stop (FS) type IGBT can be understood as a soft punch through type or a shallow punch through type IGBT. This FS-IGBT can be understood as a combination of Non-Punch Through (NPT) IGBT and PT IGBT technologies and thus benefits of these technologies, such as low saturation collector voltage (Vce, sat), easy parallel operation, robustness. It can be understood that it may have advantages such as ruggedness.

Nonetheless, fabrication of FS-IGBTs requires flat wafers that are thinner than in the fabrication of NPT IGBTs and require collector regions and N-drifts to prevent expansion of the depletion region to the collector region. type field stop layer between the drift regions.

A problem to be solved by the technical idea of the present invention is to provide a power device, for example, a field stop layer based on a semiconductor substrate between a collector region and a drift region in a structure of an FS-IGBT, And the function of the field stop layer is improved while facilitating the control of the impurity concentration in the region, and a method of manufacturing the same.

In order to solve the above problems, the technical idea of the present invention is a field stop layer formed based on the first conductivity type semiconductor substrate; An implanted field stop layer formed on the field stop layer via a first conductivity type ion implant and having a higher concentration portion than the field stop layer; A drift region formed by growing a first conductivity type epitaxial layer on the implant field stop layer and having a lower concentration than the field stop layer; A base region of a second conductivity type formed in an upper portion of the drift region; An emitter region of a first conductivity type formed in a surface portion in the base region; A gate electrode formed on the drift region, the base region, and the emitter region via a gate insulating layer; And a collector region of a second conductivity type formed under the field stop layer.

In one embodiment of the present invention, the implant field stop layer, the impurity concentration is increased from the field stop layer has a maximum impurity concentration in the first portion, the impurity concentration from the first portion to the drift region is to be reduced Can be.

In one embodiment of the present invention, the implant field stop layer may have at least two layers formed with different impurities or different doping energies. In addition, a layer adjacent to the field stop layer among the at least two layers may have a higher impurity concentration than other layers.

In one embodiment of the present invention, each of the field stop layer and the drift region has a constant concentration profile in the depth direction, wherein the field stop layer has a higher concentration than the drift region, and the implant field stop layer is the field stop. The concentration difference between the layer and the drift region may be canceled, but a higher concentration region than the field stop layer may be provided.

In addition, the technical idea of the present invention, to solve the above problems, preparing a semiconductor substrate of the first conductivity type; Implanting a first conductivity type impurity ion on the entire surface of the semiconductor substrate to form an implanted field stop layer; Growing a epitaxial layer having a lower concentration than that of the semiconductor substrate on the implant field stop layer to form a drift region; Forming a base region of a second conductivity type in a surface constant region of the drift region; Forming an emitter region of a first conductivity type in a predetermined region of the base region surface; Forming a gate electrode on the drift region, the base region, and the emitter region through a gate insulating layer; Forming an emitter electrode on the base region and the emitter region; Polishing a rear surface opposite to the front surface of the semiconductor substrate to form a field stop layer; And forming a collector region of a second conductivity type in a lower portion of the field stop layer.

In an embodiment of the present invention, in the forming of the implant field stop layer, the impurity ions may be implanted and then diffused through heat treatment.

In one embodiment of the present invention, the base region and the emitter region are formed by selectively implanting the corresponding ions in a predetermined portion and diffused by heat treatment, the collector region corresponds to the back surface of the polished semiconductor substrate It can be formed by implanting ions and diffusing through heat treatment.

Furthermore, the technical idea of the present invention is a field stop layer formed on the basis of the first conductivity-type semiconductor substrate and having a constant impurity concentration in the depth direction to solve the above problems; An implant field stop layer formed on the field stop layer through a first conductivity type ion implant and having an impurity concentration varying in a depth direction, the implant field stop layer having a peak region higher than that of the field stop layer; And a drift region formed by growing a first conductivity type epitaxial layer on the implant field stop layer.

In the power device and the method of manufacturing the same, an implant field stop layer is formed by implantation of impurity ions, so that the impurity concentration of the implant field stop layer can be precisely and easily controlled. In addition, due to such fine control of impurity concentration, the thickness and concentration profile of the implant field stop layer can be variously adjusted. Accordingly, the power device of this embodiment can significantly improve the electrical characteristics, e.g., on-off switching waveform, to achieve high speed switching characteristics.

According to an embodiment of the inventive concept, a power device and a method of manufacturing the same may be formed separately from a field stop layer based on a semiconductor substrate, thereby making it easier to control the concentration of impurities in the collector region formed under the field stop layer. Can be. In addition, since the field stop layer 110a is formed by backside polishing based on the semiconductor substrate, a high energy ion implantation process and accompanying annealing diffusion process for the field stop layer are unnecessary.

1A and 1B are cross-sectional views of power devices according to example embodiments.
2A and 2B are graphs showing concentration profiles for the power devices of FIGS. 1A and 1B.
3 is a graph showing a concentration profile according to each impurity ion when the implant field stop layer is formed by changing impurity ions.
4 through 11 are cross-sectional views illustrating a process of manufacturing the power device of FIG. 1A.
12 is a cross-sectional view of power devices according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, when an element is described as being present on top of another element, it may be directly on top of the other element, and a third element may be interposed therebetween. In addition, in the drawings, the thickness or size of each component is exaggerated for convenience and clarity of description, and parts irrelevant to the description are omitted. Wherein like reference numerals refer to like elements throughout. It is to be understood that the terminology used is for the purpose of describing the present invention only and is not used to limit the scope of the present invention.

1A and 1B are cross-sectional views of power devices according to example embodiments.

Referring to FIG. 1A, the power device 1000 according to the present embodiment includes a field stop layer 110, an implant field stop layer 120, a drift region 130, a base region 140, and an emitter region. 150 and collector region 160.

The field stop layer 110 may be formed based on a semiconductor substrate. For example, the field stop layer 110 may be formed using an N ⁰ semiconductor substrate doped with N-type impurities. In this case, the depletion region extends to an impurity concentration sufficient to form a field stop layer in the field stop-insulated gate bipolar transistor (FS-IGBT), that is, a P-type collector region formed on the surface of the semiconductor substrate opposite to the drift region. It may be a substrate doped with an N-type impurity at a concentration sufficient to prevent it from becoming. The impurity concentration of the N ⁰ semiconductor substrate for forming the field stop layer 110 may be, for example, about 1E14 to 1E16 / cm ³ .

As such, the field stop layer 110 based on the N ⁰ semiconductor substrate may have a substantially constant concentration profile in the depth direction. That is, the field stop layer 110 may have the same impurity concentration as a whole. This can be confirmed in FIG. 2A or 2B.

On the other hand, the field stop layer 110 does not use the first semiconductor substrate as it is, the implant field stop layer 120 is formed on the upper surface of the semiconductor substrate, and remains after the collector region is formed on the rear surface of the semiconductor substrate after backside polishing. The portion may constitute the field stop layer 110. As such, it may be more clearly understood in the description of the power device fabrication in FIGS. 4 to 11.

In addition, the semiconductor substrate constituting the field stop layer 110 may be a substrate produced by a Czochralski (CZ) technique, which is generally advantageous for large-diameter wafer production. In the case of the semiconductor substrate by the CZ method, since it is more economical than the substrate produced by the float zone (FZ) technique, it can contribute to the economical implementation of a power device.

The implant field stop layer 120 may be formed by implanting N-type impurity ions on the field stop layer 110. Specifically, N ⁰ implant by the N-type impurity ions to the upper region of a semiconductor substrate and diffusing the impurity ions through heat treatment, the implant field stop layer 120 may be formed. The impurity concentration of the implant field stop layer 120 may gradually increase from the impurity concentration of the field stop layer 110 to the maximum impurity concentration, and may gradually decrease from the maximum impurity concentration to the impurity concentration of the upper drift region. For example, the maximum impurity concentration of the implant field stop layer 120 is 1E15 / cm ³ to 1E17 / cm ³ . Of course, the maximum impurity concentration is not limited thereto. The concentration profile of the implant field stop layer 120 can be seen in FIGS. 2A and 2B.

The thickness of the field stop layer 110 may be reduced due to the presence of the implant field stop layer 120. That is, when the field stop layer 110 is implemented only with the conventional N ⁰ semiconductor substrate, since the collector region is formed on the opposite side of the substrate, increasing the concentration of the field stop layer 110 is limited, and thus the field stop layer 110 is limited. In order to function as a field stop layer 110 was formed with a fairly large thickness. However, in the case of the power device of the present embodiment, since the implant field stop layer 120 is separately formed, the concentration increase may not be limited. Accordingly, the thickness of the field stop layer 110 may be sufficiently reduced, and as a result, the entire thickness of the implant field stop layer 120 and the field stop layer 110 may be smaller than the thickness of the previous field stop layer. For example, when there is no conventional implant field stop layer, the field stop layer is formed to be 10 μm or more, but in the power device of the present embodiment, the field stop layer 110 is formed to be several μm and the number of implant field stop layers 120 is also increased. Since the thickness of the field stop layer 110 and the implant field stop layer 120 can be formed to about 10 μm or less.

On the other hand, the implant field stop layer 120 may serve as a barrier to prevent holes from flowing in the drift region in the P-type collector region.

The drift region 130 may be formed by growing an N-type epitaxial layer on the implant field stop layer 120. The drift region 130 may be formed at a concentration lower than that of the field stop layer 110. Specifically, the drift region 130 may be formed by growing an N-type epitaxial layer having a concentration suitable for the breakdown voltage of the N-type power device on the implant field stop layer 120. For example, the drift region 130 may have a low impurity concentration of 1E14 / cm ³ or less. The thickness of the drift region 130 may vary depending on the breakdown voltage required by the FS-IGBT. For example, when a breakdown voltage of approximately 600 V is required, the drift region 130 may be formed to a thickness of approximately 60 μm.

On the other hand, the drift region 130 may have a different concentration of the dopant to be doped when the epitaxial growth is performed. Accordingly, the drift region 130 may have a constant or varying concentration profile of impurities in the depth (or thickness) direction. That is, the impurity concentration profile in the drift region 130 may be changed by adjusting the type of impurity ions, implant energy, diffusion time, and the like in the drift region 130. In the power device of this embodiment, the concentration profile of the drift region 130 may be constant along the depth direction. The concentration profile of the drift region 130 can be seen in FIGS. 2A and 2B.

The base region 140 and the emitter region 150 may be formed in the upper surface portion of the drift region 130. In more detail, the base region 140 may be formed by selectively implanting P-type impurity ions on the upper surface of the drift region 130 and diffusing them through heat treatment. The base region 140 may be a P-type high concentration (P ⁺ ) impurity region. The base region 140 may form a drift region 130 and a PN junction region. The base region 140 may be configured of a first base region P ++ formed above and a second base region P− formed below the first base region P ++ according to the concentration (not shown). ). Here, the first base region P ++ may have an impurity concentration of about 1E19 / cm ³ , and the second base region P− may have an impurity concentration of about 1E17 / cm ³ .

Meanwhile, the emitter region 150 may be formed by selectively implanting N-type impurity ions in a predetermined region of the upper surface of the base region 140 and diffusing them through heat treatment. The emitter region 150 may be an N-type high concentration (N ⁺ ) impurity region. For example, the emitter region 150 may have a dopant concentration of about 1E18 / cm ³ to 1E20 / cm ^3.

The emitter electrode 200 may be formed over the base region 140 and the emitter region 150. The gate electrode 300 may be formed on the drift region 130, the base region 140, and the emitter region 150 with the gate insulating layer 310 interposed therebetween. The gate electrode 300 may establish a channel in a portion of the base region 140 existing between the drift region 130 and the emitter region 150 through the application of a voltage.

Although not shown, an insulating layer and / or a passivation layer covering the emitter electrode 200 and the gate electrode 300 may be formed.

The collector region 160 may be formed below the field stop layer 110. That is, after the back surface of the semiconductor substrate is polished, P-type impurity ions may be implanted in the back surface of the semiconductor substrate and diffused through heat treatment to form the collector region 160. Collector region 160 may be formed to a very thin thickness. For example, the collector region 160 may be formed to a thickness of 1 μm or less. The collector region 160 may be a P-type high concentration (P ⁺ ) impurity region.

The collector electrode 400 may be formed on the lower surface of the collector region 160.

Although the N-type power device has been exemplified so far, it is needless to say that the P-type power device can be implemented by changing the conductivity type of the impurity in the corresponding regions.

In the power device of this embodiment, the implant field stop layer is formed by implantation of impurity ions, so that the impurity concentration of the implant field stop layer can be precisely and easily controlled. In addition, due to such fine control of impurity concentration, the thickness and concentration profile of the implant field stop layer can be variously adjusted. Accordingly, the power device of this embodiment can significantly improve the electrical characteristics, e.g., on-off switching waveform, to achieve high speed switching characteristics.

On the other hand, since the implant field stop layer is formed separately from the field stop layer based on the semiconductor substrate, it is possible to easily control the impurity concentration of the collector region formed under the field stop layer. In addition, since the field stop layer 110a is formed by backside polishing based on the semiconductor substrate, a high energy ion implantation process and accompanying annealing diffusion process for the field stop layer are unnecessary.

Referring to FIG. 1B, the power device 1000a according to the present exemplary embodiment may be similar to the power device 1000 of FIG. 1A except for an implant field stop layer 120a. That is, in the power device 1000a of the present embodiment, the implant field stop layer 120a may be formed of at least two layers. For example, the implant field stop layer 120a may include a lower implant field stop layer 122 and an upper implant field stop layer 124. The implant field stop layer 120a may be formed of at least two layers with different impurities and / or different doping energies. In addition, the thickness or impurity concentration of each layer constituting the implant field stop layer 120a may vary depending on the characteristics of the power device.

In the implant field stop layer 120a formed in multiple layers, the impurity concentration of the layer adjacent to the field stop layer 110 may be higher than that of other layers. For example, the impurity concentration of the lower implant field stop layer 122 may be generally higher than the impurity concentration of the upper implant field stop layer 124. In addition, the impurity concentration of the layer adjacent to the drift region 130 among the layers constituting the implant field stop layer 120a may be lower than that of the field stop layer 110. For example, the impurity concentration of the upper implant field stop layer 124 may be lower than the field stop layer 110. However, the impurity concentration of the multilayer implant field stop layer 120a is not limited to the above contents.

In the present embodiment, the implant field stop layer 120a is composed of two layers, but may of course be composed of more layers. By forming the implant field stop layer 120a in a plurality of layers and at various concentrations, the function as the field stop layer can be improved. In addition, it is possible to reduce the thickness of the field stop layer 110 based on the semiconductor substrate, thereby contributing to reducing the size of the entire power device.

2A and 2B are graphs showing concentration profiles for the power devices of FIGS. 1A and 1B.

FIG. 2A is a graph showing a concentration profile along the depth direction of the power device 1000 of FIG. 1A, where the x axis represents depth and the y axis represents impurity concentration. On the other hand, the depth of the x-axis means the depth from the upper surface of the drift region 130 to the collector region 160, the portion of the base region 140 or emitter region 150 formed in the drift region 130 is excluded.

Referring to FIG. 2A, it can be seen that the drift region 130 (N-drift) grown as the N-type epitaxial layer has a constant impurity concentration along the depth direction. Of course, as described above, the drift region 130 may be formed such that the impurity concentration changes with depth.

The impurity concentration of the implant field stop layer 120 (Im-FS) gradually increases from the portion in contact with the drift region 130 to the maximum impurity concentration portion A, and then gradually decreases to decrease the impurity concentration of the field stop layer 110 (N ⁰ -Sub). Impurity concentrations. The implant field stop layer 120 has the function of preventing the depletion region expansion together with the field stop layer 110 as described above. In addition, since the implant field stop layer 120 may be formed at a high concentration by the ion implant separately from the field stop layer 110, the implant field stop layer 110 may be more effective in preventing the depletion region expansion, and thus the lower field stop layer 110 may be used. It can contribute to minimize the thickness of.

The field stop layer 110 (N ⁰ -Sub) based on the semiconductor substrate has a constant concentration according to the depth, and the concentration rapidly decreases at a portion in contact with the collector regions 160 and Col. On the other hand, the concentration of the collector region 160 (Col) is rapidly increased from the portion in contact with the field stop layer (110, N ⁰ -Sub) it can be seen that the P-type high concentration (P ⁺ ) impurity region.

FIG. 2B is a graph showing a concentration profile along the depth direction of the power device 1000a of FIG. 1B, where the x axis represents depth and the y axis represents impurity concentration. The depth of the x axis is as described above with reference to FIG. 2A.

Referring to FIG. 2B, it can be seen that the drift region 130 (N-drift) has a constant impurity concentration along the depth direction as shown in FIG. 2A. Of course, the impurity concentration of the drift region 130 may vary depending on the depth.

Implant field stop layer 120 (Im-FS) may be divided into two layers based on the central dashed line. The upper implant field stop layer 124 (Up) on the left side is in contact with the drift region 130, and the impurity concentration gradually increases from the impurity concentration of the drift region 130. On the other hand, the lower implant field stop layer 122 (Down) on the right side further increases the impurity concentration up to the maximum impurity concentration portion B and gradually decreases from the maximum impurity concentration portion B to reach the impurity concentration of the field stop layer 110. do. As such, since the implant field stop layer 120 is composed of two layers, the depletion region expansion prevention function together with the field stop layer 110 may be more efficiently performed. How many layers the implant field stop layer 120 is formed, and what concentration profile is to be determined in consideration of the characteristics of the power device required, the cost and time required to form the implant field stop layer 120, etc. Can be.

The field stop layer 110 (N ⁰ -Sub) based on the semiconductor substrate and the collector regions 160 and Col below it are the same as described with reference to FIG. 2A.

3 is a graph showing a concentration profile according to each impurity ion when the implant field stop layer is formed by changing impurity ions.

Referring to FIG. 3, the graph shows the concentration profile for the implant field stop layer by two different impurity ions. For example, A is a graph of forming an implant field stop layer using arsenic (As) as an impurity ion, and B is a graph of forming an implant field stop layer using phosphorus (P) as an impurity ion. to be. In general, in the case of phosphorus diffusion occurs quickly due to the heat treatment is advantageous for the formation of a wide implant field stop layer, in the case of arsenic may be advantageous for the formation of a narrow implant field stop layer because of the slow diffusion.

When forming the implant field stop layer, the determination of which impurity ions to use may be determined according to the characteristics of the power device and the size of the power device required. For example, in order to form an implant field stop layer with a thin thickness while maintaining a relatively high impurity concentration, impurity ions which do not easily diffuse may be used.

4 through 11 are cross-sectional views illustrating a process of manufacturing the power device of FIG. 1A.

Referring to FIG. 4, a first conductive semiconductor substrate 100 is prepared. For example, an N ⁰ semiconductor substrate 100 doped with N type impurity ions is prepared. At this time, the semiconductor substrate 100 has the impurity concentration required for the field stop layer in the FS-IGBT, that is, sufficient concentration of N-type impurity ions to prevent the depletion region from expanding to the P- May be a doped substrate. For example, an N ⁰ semiconductor substrate 100 having an impurity concentration of about 1E14 to 1E16 / cm ³ is prepared. The impurity concentration profile in the semiconductor substrate 100 may have a constant profile with respect to the depth (or thickness) direction of the semiconductor substrate 100 as shown in FIG. 2A or 6B.

On the other hand, the semiconductor substrate 100 may be a substrate produced by a Czochralski (CZ) technique, which is generally advantageous for large diameter wafer production. Of course, the substrate produced by the plot zone (FZ) technique is not excluded.

Referring to FIG. 5, an implant field stop layer 120 is formed by implanting N-type impurity ions in an upper region of the semiconductor substrate 100. When the implant field stop layer 120 is formed, a diffusion process through heat treatment may be performed after implanting the N-type impurity ions. In some cases, the diffusion process may be omitted. The impurity concentration of the implant field stop layer 120 may vary depending on the depth direction and may include concentration portions of 1E15 to 1E17 / cm ³ . The implant field stop layer 120 may be thinly formed to a thickness of about several μm. In some cases, it may be formed to a thickness of several tens of micrometers.

On the other hand, the implant field stop layer may be formed in multiple layers as shown in Figure 1b. When formed in multiple layers, the impurity ions and / or impurity concentrations of each layer constituting the implant field stop layer may be different. In addition, each layer of the implant field stop layer may be formed with different impurity ions and / or different doping energies, and may be formed with the same or different thicknesses.

Referring to FIG. 6A, a drift region 130a is formed on the implant field stop layer 120 by growing the same conductive type as that of the first conductive type, that is, an N-type epitaxial layer. The drift region 130a may have a lower concentration than the impurity concentration of the semiconductor substrate 100a. The drift region 130a may be formed by growing an N-type epitaxial layer having a concentration suitable for the breakdown voltage of an N-type power device, such as FS-IGBT. The thickness may vary depending on the breakdown voltage required in the drift region 130a FS-IGBT. For example, when a breakdown voltage of approximately 600 V is required, the drift region 130a may be formed to a thickness of approximately 60 μm.

Meanwhile, when the drift region 130a is epitaxially grown, the concentration of the doped impurities may be controlled. Accordingly, the drift region 130a may cause the impurity concentration profile in the depth (or thickness) direction to be constant or changed. That is, the impurity concentration profile of the drift region 130a may vary according to the designer's intention. In the power device of the present embodiment, the drift region 130a may be constant depending on the depth as shown in FIG. 6B.

Referring to FIG. 6B, the graph shows an approximate impurity concentration from the semiconductor substrate 100a to the drift region after the drift region 130a is formed. It can be seen that the semiconductor substrate 100a and the drift region 130a maintain a constant impurity concentration according to the height. Of course, as described above, the drift region 130a may have an impurity concentration changed in some cases.

Meanwhile, the implant field stop layer 120 (Im-FS) increases from the concentration of the semiconductor substrate 100a to the maximum ion concentration portion C, and gradually increases from the maximum ion concentration portion C to the concentration of the drift region 130a. Decreases. The implant field stop layer 120 (Im-FS) may function to cancel the difference in concentration between the drift region 130a and the semiconductor substrate 100a and may form a high concentration ion barrier. As a result, it is possible to prevent diffusion of the depletion region and to prevent holes from flowing from the collector region.

Referring to FIG. 7, the P-type base region 140 may be selectively implanted and diffused into a second conductive type, for example, P-type impurity ions, which are different from the first conductivity type, on a predetermined surface of the upper portion of the drift region 130a. Form. The base region 140 may be a P-type high concentration (P ⁺ ) impurity region, and may form a drift region 130a and a PN junction region.

An N-type emitter region 150 is formed by selectively implanting and diffusing a first conductivity type, that is, N-type impurity ions, into a predetermined region on the upper surface of the base region 140. The emitter region 150 may be an N-type high concentration (N ⁺ ) impurity region. At this time, the diffusion processes described above can be performed together in the heat treatment process performed after implanting the impurity ions.

Referring to FIG. 8, after the emitter region 150 is formed, the emitter electrode 200 contacting the base region 140 and the emitter region 150 is formed. A gate insulating layer 310 is formed on the surface region of the drift region 130, the base region 140 and a part of the upper surface of the emitter region 150, and a gate electrode 300 is formed on the gate insulating layer 310 do. The gate electrode 300 may set a portion of the base region 140 between the drift region 130 and the emitter region 150 as a channel through an applied voltage.

Although not shown, after the emitter electrode 200 and the gate electrode 300 are formed, an insulating layer and / or a passivation layer covering the emitter electrode, the gate electrode 400, and the like may be further formed.

The above process may be performed by a DMOS fabrication process or a trench gate type MOSFET process.

Referring to FIG. 9, the semiconductor substrate 100a is formed as a substantially field stop layer 110a. That is, in a power device such as an FS-IGBT structure, the field stop layer is formed to be substantially smaller than the drift region, but the current semiconductor substrate 100a is in a very thick state. Accordingly, a process of reducing the thickness of the back surface of the semiconductor substrate 100a is performed.

On the other hand, since the collector region is formed in the lower portion of the field stop layer, the remaining thickness of the semiconductor substrate 100a after polishing is set in consideration of the thickness of the collector region. For example, when the drift region 130 is set to a thickness of about 110 μm, the remaining thickness of the semiconductor substrate 100a for the field stop layer may be considered to be about 5-15 μm thick. At this time, the collector region may be considered to be a very thin thickness, for example, about 0.3 to 1 mu m thick. Of course, the remaining thickness of the semiconductor substrate 100a and the thickness of the collector region are not limited to the above-mentioned thickness.

In consideration of the remaining thickness, the back surface of the semiconductor substrate 100a is polished to form a substantial field stop layer 110a. As such, since the field stop layer 110a is formed by polishing the rear surface of the semiconductor substrate 100a, a high energy ion implantation process and accompanying annealing diffusion process for the field stop layer may be excluded. In addition, since the implant field stop layer 120 by the ion implant is already formed in the upper region of the semiconductor substrate, the field stop layer 110a based on the semiconductor substrate may be formed to a sufficiently small thickness.

In addition, since the semiconductor substrate 100a maintains a sufficient thickness until the polishing process, the base region 140, the emitter region 150, the emitter electrode 200, the gate electrode 300, the subsequent insulating layer, and the like. In the process of forming M can sufficiently serve as a supporting substrate. Therefore, it is possible to solve the process limitations that may occur in the case of using a thin substrate, for example, problems such as substrate curling and restriction of the thermal process for eliminating such curling.

Referring to FIG. 10, a second conductive type, for example, P-type impurity ions, which are opposite to the first conductive type, is implanted and annealed on the polished surface of the field stop layer 110a to diffuse, thereby forming the field stop layer 110. The collector region 160 is formed on the rear surface. In this case, the impurity concentration of the collector region 160 may be determined according to the switching-off characteristic of the device. The collector region 160 may be a P-type high concentration (P +) impurity region and may be formed to have a thin thickness of 1 μm or less as described above.

In the power device of this embodiment, the implant field stop layer 120 is formed separately from the field stop layer 110 based on the semiconductor substrate. Accordingly, the impurity concentration of the collector region formed on the bottom surface of the field stop layer 110 based on the semiconductor substrate may be freely adjusted to some extent. That is, in order to improve the function of the conventional field stop layer 110, there is a demand that the field stop layer 110 should be formed at a high concentration, and that the field stop layer 110 should be formed at a low concentration to form a lower collector region. Although conflicted, in the power device of the present embodiment, the implant field stop layer 120 is separately formed on the field stop layer 110, thereby solving the above problem.

Referring to FIG. 11, a collector electrode 400 is formed on the bottom surface of the collector region 160 to form a power device such as FS-IGBT as shown in FIG. 1A.

12 is a cross-sectional view of power devices according to an embodiment of the present invention. In the power device 1000b according to the present exemplary embodiment of FIG. 12, all configurations except for the base region 140, the emitter region 150, the gate electrode 300a, and the gate insulating layer 310a are the same as those of FIG. 1A. For convenience of description, the contents already described with reference to FIG. 1A will be simply described or omitted.

Meanwhile, the power device 1000b according to the present exemplary embodiment has a trench-gate structure. The power device 1000b is recessed to a predetermined depth from the surface of the drift region 130 at an upper side of the drift region 130 to form an accommodation space therein. Trench T having is formed. Here, the gate insulating layer 310a is formed on the surface of the trench T.

The trench T may have a first side wall adjacent to one side of the base region 140 and the emitter region 150. In addition, due to the symmetrical structure, the trench T naturally has a second side wall adjacent to the other side (not shown) of the other base region and the emitter region. In FIG. 12, the gate insulating layer 310a is formed to cover the upper surface of the emitter region 150, but in some cases, the gate insulating layer 310a may not be formed on the upper surface of the emitter region 150.

The gate electrode 300a is formed in an inner space of the trench T where the gate insulating layer 310a is formed. In this case, the upper end of the gate electrode 300a may be coplanar with the upper end of the drift region 130 as shown in FIG. It may be formed.

As illustrated, the base region 140 and the emitter region 150 may be disposed adjacent to the first side wall of the trench T including the gate electrode 300a and the gate insulating layer 310a. The base region 140 may be configured of a first base region P ++ formed above and a second base region P− formed below the first base region P ++ according to the concentration (not shown). . Here, the first base region P ++ may have an impurity concentration of about 1E19 / cm ³ , and the second base region P− may have an impurity concentration of about 1E17 / cm ³ .

Meanwhile, although the implant field stop layer 120 is illustrated as a single layer in FIG. 12, the implant field stop layer 120 may be formed of at least two layers having different concentrations as shown in FIG. 1B.

While the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. will be. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100, 100a: semiconductor substrate, 110, 110a: field stop layer, 120, 120a: implant field stop layer, 122: lower implant field stop layer, 124: upper implant field stop layer, 130: drift region, 140: base region, 150: emitter region, 160: collector region, 200: emitter electrode, 300: gate electrode, 310: gate insulating layer, 400: collector electrode, 1000, 1000a: power element

Claims (25)

A field stop layer formed on the first conductive semiconductor substrate;
An implanted field stop layer formed on the field stop layer via a first conductivity type ion implant and having a higher concentration portion than the field stop layer;
A drift region formed by growing a first conductivity type epitaxial layer on the implant field stop layer and having a lower concentration than the field stop layer;
A base region of a second conductivity type formed in an upper portion of the drift region;
An emitter region of a first conductivity type formed in a surface portion in the base region;
A gate electrode formed on the drift region, the base region, and the emitter region via a gate insulating layer; And
And a second conductivity type collector region formed under the field stop layer. The method according to claim 1,
The implant field stop layer,
And the impurity concentration increases from the field stop layer to have a maximum impurity concentration in the first portion, and the impurity concentration decreases from the first portion to the drift region. The method of claim 2,
And the impurity concentration is sharply reduced in the portion of the implant field stop layer in contact with the drift region. The method according to claim 1,
And the implant field stop layer comprises at least two layers formed with different impurities or different doping energies. 5. The method of claim 4,
And wherein the layer adjacent to the field stop layer among the at least two layers has a higher impurity concentration than the other layers. 5. The method of claim 4,
A layer adjacent to the drift region of the at least two layers has a lower impurity concentration than the field stop layer. The method according to claim 1,
Each of the field stop layer and the drift region has a constant concentration profile in the depth direction, wherein the field stop layer has a higher concentration than the drift region,
And the implant field stop layer cancels the difference in concentration between the field stop layer and the drift region and has a higher concentration region than the field stop layer. The method according to claim 1,
The field stop layer has an impurity concentration of 1E14 / cm ³ to 1E16 / cm ³ ,
And the implant stop layer comprises an impurity concentration portion of 1E15 / cm ³ to 1E17 / cm ³ . The method according to claim 1,
An emitter electrode electrically connected to the emitter region; And
And a collector electrode electrically connected to the collector region. The method according to claim 1,
And the field stop layer is formed by backside polishing of a Czochralski (CZ) single crystal substrate. Preparing a semiconductor substrate of a first conductivity type;
Forming an implanted field stop layer by implanting a first conductivity type impurity ion on the entire surface of the semiconductor substrate;
Growing a epitaxial layer having a lower concentration than that of the semiconductor substrate on the implant field stop layer to form a drift region;
Forming a base region of a second conductivity type in a surface constant region of the drift region;
Forming an emitter region of a first conductivity type in a predetermined region of the base region surface;
Forming a gate electrode on the drift region, the base region, and the emitter region through a gate insulating layer;
Forming an emitter electrode on the base region and the emitter region;
Polishing a rear surface opposite to the front surface of the semiconductor substrate to form a field stop layer; And
And forming a collector region of a second conductivity type in a lower portion of the field stop layer. 12. The method of claim 11,
The sum of the thicknesses of the implant field stop layer and the field stop layer is smaller than the thickness of the field stop layer when the implant field stop layer is not formed. 12. The method of claim 11,
In the step of forming the implant field stop layer,
And implanting the impurity ion and then diffusing it through heat treatment. 12. The method of claim 11,
And the implant field stop layer is formed of at least two layers with different impurities or different doping energy. 15. The method of claim 14,
And forming a layer adjacent to the field stop layer among the at least two layers with a higher impurity concentration than the other layers. 12. The method of claim 11,
Each of the field stop layer and the drift region is formed to have a constant concentration profile in the depth direction, and the field stop layer is formed to have a higher concentration than the drift region,
The implant field stop layer has a higher concentration region than the field stop layer, and the concentration increases and decreases so as to cancel the difference in concentration between the field stop layer and the drift region. 12. The method of claim 11,
The field stop layer is formed to have an impurity concentration of 1E14 / cm ³ to 1E16 / cm ³ ,
And the implant stop layer is formed to have an impurity concentration portion of 1E15 / cm ³ to 1E17 / cm ³ . 12. The method of claim 11,
The base area and the emitter area,
The ions are selectively implanted in a predetermined portion and formed by diffusion through heat treatment,
The collector region,
And implanting the corresponding ions in the back surface of the polished semiconductor substrate and diffusing them through heat treatment. A field stop layer formed based on the first conductivity type semiconductor substrate and having a constant impurity concentration in the depth direction;
An implant field stop layer formed on the field stop layer through a first conductivity type ion implant and having an impurity concentration varying in a depth direction, the implant field stop layer having a peak region higher than that of the field stop layer; And
And a drift region formed by growing a first conductivity type epitaxial layer on the implant field stop layer. 20. The method of claim 19,
And the drift region has a constant impurity concentration in a depth direction and has a first impurity concentration lower than that of the field stop layer. A first conductivity type semiconductor substrate;
A field stop layer disposed on the substrate and having a first conductivity type and having a higher concentration portion than the substrate;
A drift region disposed on the field stop layer and formed of a first conductivity type epitaxial layer and having a lower concentration than the field stop layer;
A base region of a second conductivity type disposed in an upper portion of the drift region;
An emitter region of a first conductivity type disposed in a surface portion in the base region;
A gate electrode disposed on one side of the base region and the emitter region and buried in the drift region; And
And a second conductivity type collector region disposed below the field stop layer. 22. The method of claim 21,
And a gate insulating layer disposed between the base region, the emitter region and the drift region, and the gate electrode. 22. The method of claim 21,
The field stop layer,
And the impurity concentration increases from the semiconductor substrate to have a maximum impurity concentration in the first portion, and the impurity concentration decreases from the first portion to the drift region. 22. The method of claim 21,
And the field stop layer comprises at least two layers. 22. The method of claim 21,
Each of the semiconductor substrate and the drift region has a constant concentration profile in a depth direction, wherein the semiconductor substrate has a higher concentration than the drift region,
And the field stop layer cancels the difference in concentration between the semiconductor substrate and the drift region, and has a higher concentration region than the semiconductor substrate.

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