CN107919399A - Half superjunction devices and its manufacture method - Google Patents
Half superjunction devices and its manufacture method Download PDFInfo
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- CN107919399A CN107919399A CN201711327511.4A CN201711327511A CN107919399A CN 107919399 A CN107919399 A CN 107919399A CN 201711327511 A CN201711327511 A CN 201711327511A CN 107919399 A CN107919399 A CN 107919399A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000002347 injection Methods 0.000 claims abstract description 63
- 239000007924 injection Substances 0.000 claims abstract description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000000407 epitaxy Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 230000001737 promoting effect Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241001270131 Agaricus moelleri Species 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The present invention provides a kind of half superjunction devices and its manufacture method.Half superjunction devices includes N-type substrate,First layer,The second layer,Third layer N-type extension,N-type extension and the first groove and second groove of Yanzhong outside first layer N-type are extended to through the 3rd and second,It is formed at first,The p-type injection zone of second groove inner wall,It is formed at first,The p-type epitaxial layer on p-type injection zone in second groove,The 3rd groove being formed in the p-type epitaxial layer of first groove,The 4th groove being formed in the p-type epitaxial layer of second groove,It is formed at the PXing Ti areas of the third layer N-type epitaxial surface of first and second groove both sides,It is formed at the N-type injection region of p-type body surface,It is formed at the 3rd,4th channel bottom and side wall,Third layer N-type epitaxial surface,Thermal oxide layer above p-type injection region,It is formed at the polysilicon on thermal oxide layer surface,It is formed at third layer N-type extension,Dielectric layer in PXing Ti areas,And the through hole through dielectric layer and corresponding PXing Ti areas.
Description
【Technical field】
The present invention relates to technical field of semiconductor device, especially, is related to a kind of half superjunction devices and its manufacture method.
【Background technology】
The superjunction devices of superjunction/half, as drain-source the two poles of the earth of trench vertical bilateral diffusion field-effect tranisistor (VDMOS) exist respectively
The both sides of device, make electric current vertically circulate in device inside, add current density, improve rated current, unit area
Conducting resistance is also smaller, is a kind of very extensive power device of purposes.
Conventional power MOSFET generally use VDMOS structures, in order to bear high voltage, need to reduce drift doping concentration or
Person increases drift region thickness, this direct result brought is that conducting resistance increased dramatically.The conducting of general conventional power MOSFET
Resistance and breakdown voltage are in 2.5 power relations, this relation is referred to as " the silicon limit ".It is former that " superjunction " VDMOS is based on charge compensation
Reason, the conducting resistance and breakdown voltage for making device are in 1.32 power relations, solve well conducting resistance and breakdown voltage it
Between contradiction.Compared with conventional power VDMOS structures, super node MOSFET substitutes conventional power devices using alternate P-N- structures
In low-doped drift layer as voltage sustaining layer.The essence of super node MOSFET is (to N ditches using the P areas being inserted into drift region
For device) caused by electric field charge compensation is carried out to N areas, achieve the purpose that to improve breakdown voltage and reduce conducting resistance.
Super node MOSFET is to carry out charge compensation using alternate N columns and P columns inside compound buffer layer, makes P areas and N areas
Mutually exhaust, form preferable flat-top electric field distribution and uniform Potential Distributing, led so as to reach to improve breakdown voltage and reduce
Be powered the purpose hindered.Reach preferable effect, its precondition is exactly charge balance.Therefore, superjunction technology is since birth,
Its manufacturing process is exactly to be carried out around the N columns and P columns for how manufacturing charge balance.The manufacturing technology used at present is main
Have：Multiple extension and injection technique, deep etching and slot filling technique.However, how to reduce being manufactured into for the superjunction devices of superjunction/half
Originally it is an important topic of industry.
【The content of the invention】
One of purpose of the present invention is to provide a kind of half superjunction devices and its manufacturer to solve the above problems
Method.
A kind of half superjunction devices, it includes N-type substrate, the first layer N-type extension that is formed in the N-type substrate, is formed at
Second layer N-type extension in the first layer N-type extension, the third layer N-type extension being formed in the second layer N-type extension,
N-type extension and extend to the first groove of Yanzhong and second groove outside the first layer N-type through the described 3rd and second, formed
Injected in the p-type injection zone of the first groove and second groove inner wall, the p-type being formed in first, second groove
P-type epitaxial layer on region, be formed at the p-type epi-layer surface of the first groove and the 3rd ditch on p-type injection zone surface
Groove, the p-type epi-layer surface for being formed at the second groove and p-type injection zone surface the 4th groove, be formed at described the
One and second groove both sides third layer N-type epitaxial surface PXing Ti areas, be formed at the p-type body surface N-type injection
Area, be formed at the three, the 4th channel bottoms and side wall, p-type injection region top, the third layer N-type epitaxial surface
Thermal oxide layer, be formed at the polysilicon on the thermal oxide layer surface, be formed at the third layer N-type extension, the PXing Ti areas
On dielectric layer, be formed at the N-type injection region of the p-type body surface and through the dielectric layer and at least partly corresponding institute
State the through hole of N-type injection region.
In one embodiment, half superjunction devices further includes the front metal being formed on dielectric layer, it is described just
Face metal at least partly connects the N-type injection region by the through hole.
In one embodiment, half superjunction devices further includes back metal, and the back metal is formed at the N
Surface of the type substrate away from the first layer N-type extension.
In one embodiment, the PXing Ti areas include three GePXing Ti areas, and the first groove is positioned at middle p-type
Between body area and the PXing Ti areas of its side, the second groove is between middle PXing Ti areas and the PXing Ti areas of opposite side.
In one embodiment, each p-type body surface has at least one n-type doping area, and the front metal leads to
Corresponding through hole is crossed partly to be connected with each PXing Ti areas and its N-type injection region.
In one embodiment, the N-type injection region is N-type highly doped regions.
A kind of production method of half superjunction devices, it includes the following steps：
N-type substrate is provided, first layer N-type extension, second layer N-type extension, third layer are sequentially formed in the N-type substrate
The first silicon oxide layer is extended to outside N-type, is performed etching using the first photoresist as mask, formation runs through first silica
Layer, the third layer N-type extension, the second layer N-type extension and extend to the first groove of the outer Yanzhong of the first layer N-type with
Second groove；
Remove first photoresist, to first, second and third N-type of the first groove and second groove inner wall outside
Prolong surface and carry out p-type ion implanting formation p-type injection region；
Carry out thermal oxide and then form silica in the p-type injection region inner wall of first and second groove, etching removes
Silica in first silicon oxide layer and first, second groove, in the p-type injection region of the first groove and second groove
P-type epitaxial layer is formed on inner wall and the 3rd N-type epitaxy layer；
Remove the p-type epitaxial layer in the 3rd N-type epitaxy layer；
The second silicon oxide layer is formed in the 3rd N-type epitaxy layer, using the second photoresist as described in mask etching
P-type epitaxial layer in first, second groove, thus the first groove p-type epi-layer surface formed the 3rd groove and
The 4th groove is formed in the p-type epi-layer surface of the second groove；
Carry out thermal oxide and be respectively formed what is be connected with the p-type injection zone with bottom in the 3rd and the 4th trenched side-wall
Thermal oxide layer；
Thermal oxide layer and p-type epi-layer surface, second silicon oxide layer in the 3rd groove and the 4th groove
Upper formation polysilicon；
Remove the polysilicon above second silicon oxide layer；
Remove second silicon oxide layer, carry out thermal oxide the 3rd N-type epitaxial surface and it is described first, second,
Thermal oxide layer is formed on p-type injection region, thermal oxide layer and polysilicon in 3rd and the 4th groove, outside the third layer N-type
Polysilicon is formed on thermal oxide layer on prolonging；
Using the 3rd photoresist as mask, form two first through the polysilicon layer and the thermal oxide layer and open
Mouth and the second opening, described two first openings correspond in polysilicon and the second groove in the first groove respectively
Polysilicon, the third layer N-type extension between the corresponding first groove of second opening and the second groove；
P-type ion implanting, which is carried out, using the described second opening forms PXing Ti areas；
Progress thermal annealing is to the p-type ion into line activating with promoting；
Using the 4th photoresist as mask, N-type ion implanting is carried out to the p-type body surface and forms N-type injection region；
Dielectric layer is formed on the PXing Ti areas, the polysilicon；
Form the through hole through the dielectric layer and the corresponding PXing Ti areas.
In one embodiment, the method is further comprising the steps of：Front metal, institute are formed on the dielectric layer
State at least part that front metal connects the N-type injection region by the through hole.
In one embodiment, the method is further comprising the steps of：In the N-type substrate away from the first layer N
The surface of type extension forms back metal.
In one embodiment, the resistivity of the second layer N-type extension is more than first layer N-type extension and third layer N
The resistivity of type extension.
The present invention proposes a kind of half superjunction devices of small capacitances, using two-layer epitaxial piece, carries out injection and forms p-type injection region
Buried regions, carries out second of extension, carries out an etching groove, forms P post region domain in lower trench, then carries out thermal oxide, shape
Into oxide layer as isolating, on groove top, filling polysilicon forms raceway groove, and technique is simple, reduces device manufacture cost.
【Brief description of the drawings】
To describe the technical solutions in the embodiments of the present invention more clearly, used in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure, wherein：
Fig. 1 is the cross-sectional view of half superjunction devices of a better embodiment of the invention.
Fig. 2 to Figure 15 is the structure diagram of each step of the manufacture method of half superjunction devices shown in Fig. 1.
【Embodiment】
The technical solution in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only the part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this area is common
All other embodiment that technical staff is obtained without making creative work, belongs to the model that the present invention protects
Enclose.
Referring to Fig. 1, Fig. 1 is the structure diagram of half superjunction devices of a better embodiment of the invention.Described half is super
Junction device can be power MOSTFET, it includes N-type substrate, the first layer N-type extension that is formed in the N-type substrate,
The second layer N-type extension being formed in the first layer N-type extension, the third layer N-type being formed in the second layer N-type extension
Extension, through the described 3rd and second N-type extension and extend to the first groove of Yanzhong and the second ditch outside the first layer N-type
Groove, the p-type injection zone for being formed at first groove and the second groove inner wall, the P being formed in first, second groove
P-type epitaxial layer on type injection zone, the p-type epi-layer surface for being formed at the first groove and p-type injection zone surface
3rd groove, the p-type epi-layer surface for being formed at the second groove and p-type injection zone surface the 4th groove, be formed at
The PXing Ti areas of the third layer N-type epitaxial surface of first and second groove both sides, the N-type for being formed at the p-type body surface
Injection region, be formed at the three, the 4th channel bottoms and side wall, p-type injection region top, the third layer N-type extension
The thermal oxide layer on surface, the polysilicon for being formed at the thermal oxide layer surface, be formed at the third layer N-type extension, the p-type
Dielectric layer in body area, the N-type injection region for being formed at the p-type body surface and through the dielectric layer and at least partly right
Answer through hole, front metal and the back metal of the N-type injection region.
The front metal is formed on dielectric layer, and the front metal at least partly connects the N by the through hole
Type injection region.The back metal is formed at surface of the N-type substrate away from the first layer N-type extension.
Further, the PXing Ti areas include three GePXing Ti areas, and the first groove is positioned at middle PXing Ti areas and its
Between the PXing Ti areas of side, the second groove is between middle PXing Ti areas and the PXing Ti areas of opposite side.Each p-type
Body surface has at least one n-type doping area, and the front metal passes through corresponding through hole and each PXing Ti areas and its N-type
Injection region partly connects.Further, the N-type injection region is N-type highly doped regions.The thermal oxide layer is gate oxidation
Layer.
Fig. 2 to Figure 15 is referred to, it is the structure diagram of each step of the manufacture method of half superjunction devices shown in Fig. 1.
The manufacture method following steps S1 to S17 of half superjunction devices.
Step S1, referring to Fig. 2, providing N-type substrate, sequentially forms first layer N-type extension, the in the N-type substrate
The first silicon oxide layer is extended to outside two layers of N-type extension, third layer N-type, is performed etching using the first photoresist as mask, formation is passed through
Wear first silicon oxide layer, the third layer N-type extension, the second layer N-type extension and extend to outside the first layer N-type
The first groove and second groove of Yanzhong.Wherein, the etching can be dry etching.The resistance of the second layer N-type extension
Rate is more than the resistivity of first layer N-type extension and third layer N-type extension.
Step S2, referring to Fig. 3, remove first photoresist, to the of the first groove and second groove inner wall
First, second and third layer of N-type epitaxial surface carries out p-type ion implanting and forms p-type injection region.
Step S3, referring to Fig. 4, carrying out thermal oxide and then in the p-type injection region inner wall shape of first and second groove
Into silica, etching removes first silicon oxide layer and the silica in first, second groove, in the first groove and the
P-type epitaxial layer is formed on the p-type injection region inner wall of two grooves and the third layer N-type extension.In the step S3, the etching
It can be wet etching.
Step S4, referring to Fig. 5, removing the p-type epitaxial layer in the third layer N-type extension.
Step S5, referring to Fig. 6, forming the second silicon oxide layer in the 3rd N-type epitaxy layer, uses the second photoresist
As the p-type epitaxial layer in first, second groove described in mask etching, so that in the p-type epi-layer surface of the first groove
Form the 3rd groove and form the 4th groove in the p-type epi-layer surface of the second groove.
Step S6, referring to Fig. 7, carry out thermal oxide be respectively formed in the 3rd and the 4th trenched side-wall and bottom with it is described
The thermal oxide layer that p-type injection zone is connected.
Step S7, referring to Fig. 8, the 3rd groove and the thermal oxide layer in the 4th groove and p-type epi-layer surface, institute
State and form polysilicon on the second silicon oxide layer.
Step S8, referring to Fig. 9, removing the polysilicon above second silicon oxide layer.Specifically, etching can be used
Remove.
Step S9, referring to Fig. 10, removing second silicon oxide layer, carries out thermal oxide in the third layer N-type extension
Thermal oxide is formed on surface and described first, second, third and the 4th p-type injection region in groove, thermal oxide layer and polysilicon
Layer, form polysilicon on the thermal oxide layer in the third layer N-type extension.Specifically, wet etching can be used to remove institute
State the second silicon oxide layer.
Step S10, please refers to Fig.1 1, using the 3rd photoresist as mask, formed through the polysilicon layer with it is described
Two first openings of thermal oxide layer and the second opening, described two first openings correspond to the polycrystalline in the first groove respectively
Polysilicon in silicon and the second groove, the between the corresponding first groove of second opening and the second groove
Three layers of N-type extension.In step S10, the etching can be dry etching.
Step S11, please refers to Fig.1 2, and carrying out p-type ion implanting using the described second opening forms PXing Ti areas.
Step S12, please refers to Fig.1 3, progress thermal annealing is to the p-type ion into line activating with promoting.
Step S13, please refers to Fig.1 4, using the 4th photoresist as mask, to the p-type body surface carry out N-type from
Son injection forms N-type injection region.
Step S14, please refers to Fig.1 5, and dielectric layer is formed on the PXing Ti areas, the polysilicon.
Step S15, referring to Fig. 1, forming the through hole through the dielectric layer and the corresponding PXing Ti areas.The through hole
It can be formed by dry etching.
Step S16, referring to Fig. 1, forming front metal on the dielectric layer, the front metal passes through the through hole
Connect at least part of the N-type injection region.
Step S17, referring to Fig. 1, forming back-side gold on surface of the N-type substrate away from the first layer N-type extension
Belong to.
The present invention proposes a kind of half superjunction devices of small capacitances, using two-layer epitaxial piece, carries out injection and forms p-type injection region
Buried regions, carries out second of extension, carries out an etching groove, forms P post region domain in lower trench, then carries out thermal oxide, shape
Into oxide layer as isolating, on groove top, filling polysilicon forms raceway groove, and technique is simple, reduces device manufacture cost.
Above-described is only embodiments of the present invention, it should be noted here that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
Enclose.
Claims (10)
- A kind of 1. half superjunction devices, it is characterised in that：Half superjunction devices includes N-type substrate, is formed in the N-type substrate First layer N-type extension, be formed in the first layer N-type extension second layer N-type extension, be formed at the second layer N-type Third layer N-type extension in extension, through the described 3rd and second N-type extension and extend to Yanzhong outside the first layer N-type First groove and second groove, be formed at the p-type injection zone of first groove and the second groove inner wall, be formed at described the First, the p-type epitaxial layer on the p-type injection zone in second groove, be formed at the p-type epi-layer surface and P of the first groove 3rd groove on type injection zone surface, the p-type epi-layer surface for being formed at the second groove and p-type injection zone surface 4th groove, be formed at first and second groove both sides third layer N-type epitaxial surface PXing Ti areas, be formed at the P The N-type injection region of type body surface, be formed at the three, the 4th channel bottoms and side wall, p-type injection region top, institute The thermal oxide layer of third layer N-type epitaxial surface is stated, the polysilicon on the thermal oxide layer surface is formed at, is formed at the third layer N-type extension, the dielectric layer in the PXing Ti areas, the N-type injection region for being formed at the p-type body surface and through the medium Layer and the through hole of at least partly corresponding N-type injection region.
- 2. half superjunction devices as claimed in claim 1, it is characterised in that：Half superjunction devices, which further includes, is formed at dielectric layer On front metal, the front metal by the through hole at least partly connect the N-type injection region.
- 3. half superjunction devices as claimed in claim 2, it is characterised in that：Half superjunction devices further includes back metal, institute State back metal and be formed at surface of the N-type substrate away from the first layer N-type extension.
- 4. half superjunction devices as claimed in claim 1, it is characterised in that：The PXing Ti areas include three GePXing Ti areas, described First groove is between middle PXing Ti areas and the PXing Ti areas of its side, and the second groove is positioned at middle PXing Ti areas Between the PXing Ti areas of opposite side.
- 5. half superjunction devices as claimed in claim 1, it is characterised in that：There is each p-type body surface at least one N-type to mix Miscellaneous area, the front metal are partly connected by corresponding through hole with each PXing Ti areas and its N-type injection region.
- 6. half superjunction devices as claimed in claim 1, it is characterised in that：The N-type injection region is N-type highly doped regions.
- A kind of 7. production method of half superjunction devices, it is characterised in that：Described method includes following steps：N-type substrate is provided, first layer N-type extension, second layer N-type extension, third layer N-type are sequentially formed in the N-type substrate The first silicon oxide layer is extended to outside, is performed etching using the first photoresist as mask, is formed through first silicon oxide layer, institute State third layer N-type extension, the second layer N-type extension and the first groove and second for extending to the outer Yanzhong of the first layer N-type Groove；First photoresist is removed, to first, second and third N-type extension table of the first groove and second groove inner wall Face carries out p-type ion implanting and forms p-type injection region；Carry out thermal oxide and then form silica in the p-type injection region inner wall of first and second groove, etch described in removing Silica in first silicon oxide layer and first, second groove, in the p-type injection region inner wall of the first groove and second groove And p-type epitaxial layer is formed in the 3rd N-type epitaxy layer；Remove the p-type epitaxial layer in the 3rd N-type epitaxy layer；Form the second silicon oxide layer in the 3rd N-type epitaxy layer, using the second photoresist as first described in mask etching, P-type epitaxial layer in second groove, so that the p-type epi-layer surface in the first groove forms the 3rd groove and in institute The p-type epi-layer surface for stating second groove forms the 4th groove；Carry out thermal oxide and be respectively formed the hot oxygen being connected with the p-type injection zone with bottom in the 3rd and the 4th trenched side-wall Change layer；Polysilicon is formed on thermal oxide layer, second silicon oxide layer in the 3rd groove and the 4th groove；Remove the polysilicon above second silicon oxide layer；Second silicon oxide layer is removed, carries out thermal oxide in the 3rd N-type epitaxial surface and described first, second, third And thermal oxide layer is formed on the 4th p-type injection region in groove, thermal oxide layer and polysilicon, in the third layer N-type extension Thermal oxide layer on form polysilicon；Using the 3rd photoresist as mask, formed two first openings through the polysilicon layer and the thermal oxide layer with Second opening, described two first openings correspond to the polysilicon in the first groove and the polycrystalline in the second groove respectively Silicon, the third layer N-type extension between the corresponding first groove of second opening and the second groove；P-type ion implanting, which is carried out, using the described second opening forms PXing Ti areas；Progress thermal annealing is to the p-type ion into line activating with promoting；Using the 4th photoresist as mask, N-type ion implanting is carried out to the p-type body surface and forms N-type injection region；Dielectric layer is formed on the PXing Ti areas, the polysilicon；Form the through hole through the dielectric layer and the corresponding PXing Ti areas.
- 8. the production method of half superjunction devices as claimed in claim 7, it is characterised in that：The method further includes following step Suddenly：Front metal is formed on the dielectric layer, the front metal connects the N-type injection region at least by the through hole Part.
- 9. the production method of half superjunction devices as claimed in claim 8, it is characterised in that：The method further includes following step Suddenly：Back metal is formed on surface of the N-type substrate away from the first layer N-type extension.
- 10. the production method of half superjunction devices as claimed in claim 7, it is characterised in that：The electricity of the second layer N-type extension Resistance rate is more than the resistivity of first layer N-type extension and third layer N-type extension.
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Cited By (1)
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| CN113921401A (en) * | 2021-12-09 | 2022-01-11 | 南京华瑞微集成电路有限公司 | Super junction and SGT novel composite MOSFET and manufacturing method thereof |
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