CN101506956A

CN101506956A - A method for fabricating a semiconductor device

Info

Publication number: CN101506956A
Application number: CNA2006800366238A
Authority: CN
Inventors: 马凌
Original assignee: International Rectifier Corp USA
Current assignee: Infineon Technologies Americas Corp
Priority date: 2005-08-17
Filing date: 2006-08-16
Publication date: 2009-08-12
Also published as: CN101288175B; CN101288175A

Abstract

A process for fabricating a power semiconductor device is disclosed.

Description

The manufacture method of semiconductor equipment

Related application

The application number that the application submitted to on August 17th, 2005 is 60/709,020, the name U.S. Provisional Application that is called TrenchMOSFET Process Using Four Masks requires the priority of this provisional application and the disclosed content of this provisional application to be incorporated by reference thereto at this for the basis and require the interests of this provisional application.

Technical field

The present invention relates to semiconductor fabrication, relate more specifically to manufacture method as the power semiconductor device of power metal oxide layer semiconductcor field effect transistor (MOSFET).

Background technology

Photoetching process behave institute know and be as the semiconductor equipment making of power MOSFET etc. in the general technology of use.In general, photoetching process is included on the surface of semiconductor body deposition of mask material and optionally removes mask material to be formed on the mask that has opening on the mask.Be used to define the characteristic of semiconductor body after this mask.For example, alloy can be injected into semiconductor body, perhaps remove the part of semiconductor body so that this semiconductor body is undesirably recessed or " fluting " by opening by mask open.

Typical manufacturing process may need some masks.For example, may need mask to define gate trench, or need mask to define source area.

Expectation can reduce the quantity of mask, because generally speaking the increase of mask quantity can make manufacturing process more complicated, thereby cost is increased, and, more mask can have increased access to the chance of higher defectiveness parts percentage, has reduced output thus and has increased total cost.

Summary of the invention

An object of the present invention is to provide a kind of manufacturing process of the power semiconductor device as power MOSFET.

Process according to the present invention is included in mask film covering body on the surface of semiconductor body; A part of removing mask body extends to the opening of this semiconductor body with definition; Remove semiconductor from the bottom of opening to define a plurality of gate trenchs and to be arranged on this gate trench termination groove on every side, described gate trench is spaced from each other by mesa structure; Remove mask body; The sidewall of oxidation gate trench; The deposition gate material; The etch-gate electrode material so that gate electrode stay in the groove; Inject channel dopants to define the tagma of contiguous described gate trench; On this tagma, form source mask; Inject source dopant to form the source electrode injection region by source mask; On semiconductor body, deposit low density oxide; Deposition contact mask; By this contact mask etching low density oxide; At the top of semiconductor body depositing metal layers; The front metal mask is formed on the top at this metal level; And this metal level of etching is to form at least one source contact and gate runner.

Thus, in process according to the present invention, use four masks can obtain power semiconductor device, that is, and the trench mask that is used to define gate trench and stops groove; Source mask; Contact mask and the mask that is used to define source electrode and gate electrode.

Comprise also that according to process of the present invention forming oxidation at least on the sidewall of gate trench and termination groove suppresses body, and at the bottom of gate trench and the bottom grow thick oxysome of termination groove.Then, can remove oxidation and suppress body before gate trench sidewalls is carried out oxidation, this process can also comprise the oxidation mesa structure then; On mesa structure, deposit gate material; Etch away gate material from mesa structure; And before injecting, source electrode etches away oxide from mesa structure.

In another changes, in mask body, can define opening, and the part of semiconductor body can be removed to stop defining equipotential ring (EQR) groove around the groove.

Relate to from below and can know in the description of the invention of accompanying drawing and understand other characteristics of the present invention and advantage.

Description of drawings

Fig. 1 has schematically shown the cross-sectional view of the part of the equipment of making according to the preferred embodiment for the present invention;

Fig. 2 A-2H has shown the manufacturing process of power semiconductor device according to the preferred embodiment of the present invention.

Embodiment

With reference to Fig. 1, be power MOSFET according to evaluation method selecting optimal equipment of the present invention, this power MOSFET includes source region 10 and terminator 12.Active area 10 comprises that at least one extends to the gate trench 14 of drift region 18 by base 16.Gate oxide (for example, SiO ₂) 20 with suitable thickness (for example, 1000

) be formed on the sidewall of gate trench 14 thick oxysome (for example, SiO ₂) 22 (thicker than gate oxide 20) are formed on the bottom of gate trench 14, and gate electrode 24 (be preferably by conductive polycrystalline silicon and constitute) is formed on gate trench 14 the insides.

Active area also comprises adjacent trench 14 and is formed on source area 26 in the base 16, and is formed on the high conduction contact zone 28 in the base 16.Source contact is connected to source area 26 and high conduction contact zone 28 for 30 ohm.Notice that known as behaving, base 16 and high conduction contact zone 28 have the polarity opposite with source area 26 and drift region 18.Therefore, in the N channel device, base 16 and high conduction contact zone 28 are the P type, and drift region 18 and source area 26 are the N type.Also comprise the silicon chip 32 that has with drift region 18 identical polars according to equipment of the present invention, and drain contact 34, this drain contact is connected to substrate 32 for 34 ohm.Notice, as be usually known that drift region 18 and base 16 are parts of the epitaxially grown silicon body 31 of growth on substrate 32.

Terminator 12 comprises termination groove 36, this termination groove 36 be set at active area 10 around and extend to the degree of depth that is lower than base 16, first silicon dioxide body 38, this first silicon dioxide body 38 is positioned on the bottom surface and sidewall that stops groove 38, and is positioned at second silicon dioxide body 40 on first silicon dioxide body 38.First silicon dioxide body 38 is grow oxides, thereby promptly come growthing silica to form this grow oxide, and the low-density silicon dioxide body 40 of tetraethoxysilane (TEOS) form second silicon dioxide body 40 by for example depositing by oxidation epitaxially grown silicon body 31.First silicon dioxide body 38 and second silicon dioxide body 40 form field insulator together.Lying along on second silicon dioxide body 40 of source contact 30 forms field plate 42 thus.Preferably, terminator 12 also comprises and is arranged on equipotential ring (EQR) structure 44 that stops around the groove 36.EQR 44 comprises EQR groove 46, and the sidewall and the bottom of this EQR groove 46 have silicon dioxide, and are provided with polysilicon in EQR groove 46.

Fig. 2 A-2H has schematically illustrated the method according to this invention.

With reference to Fig. 2 A, from having the silicon chip 32 of the epitaxial silicon body 31 that is formed on the silicon chip 32, at first hard mask 50 is formed on the surface of N type epitaxially grown silicon 31 for example.By depositing by for example silicon nitride (Si ₃N ₄) the hard mask body that constitutes forms hard mask 50, definition opening 52 in this hard mask body, and remove from the bottom of opening 52 silicon with definition gate trench 14, stop groove 36 and EQR groove 44.

Next, on the sidewall of the sidewall of gate trench 14, the sidewall that stops groove 36 and EQR groove 44, form for example Si ₃N ₄Oxidation suppress body 54.Afterwards, the bottom of the bottom of gate trench 14, the bottom that stops groove 36 and EQR groove 44 is oxidized to form the thick oxysome 22 shown in Fig. 2 B.

Next with reference to figure 2C, mask 50 and oxidation suppress that body 54 is removed and the silicon that comes out is oxidized, on the sidewall of gate trench 14, form gate oxide 20 thus, and on all the other silicon that come out, form oxide liners 56, described all the other silicon that come out comprise the sidewall that stops groove 36, the sidewall of EQR groove 44 and the mesa structure between

groove

14,36 and 44.Notice that the oxide liners 56 that stops on groove 36 sidewalls forms first oxysome 38 with the thick oxysome 22 that stops groove 36 bottoms.Afterwards, shown in Fig. 2 D, polysilicon 58 is deposited.By after polysilicon 58 is deposited, injecting alloy or, can making polysilicon 58 show conductivity by in-situ doped.Then, shown in Fig. 2 E, polysilicon 58 is removed and makes gate electrode 24 stay in the gate trench 14 and make polysilicon body 48 stay in the EQR groove 44.Replacedly, shown in Fig. 2 E ', can use anisotropic etching that polysilicon partition 59 is stayed on the sidewall that stops groove 36.Polysilicon partition 59 can be that electricity is floating.

Below with reference to Fig. 2 F, remove oxide 58 from the top of the mesa structure between

groove

14,36 and 44, and inject the alloy that is used to form base 16.Note, in the following silicon in the bottom that the thick oxysome 22 that stops groove 34 bottoms stops alloys to penetrate into to stop groove 36.After the base injects, source mask is provided and injects source dopant.Activate source electrode infusion and base stage infusion then to form base region 16 and source area 28.After this, shown in Fig. 2 G, for example the low-density oxide layer 60 of TEOS is deposited.Shown in Fig. 2 H, the part that low density oxide is formed figure and this low density oxide in the mask stage is removed to form contact openings 62 in this low density oxide then.Notice and form second oxysome 40 and oxidation plug 25 (oxide plug) thus.By each opening 62, thereby a part of silicon is removed and forms groove, and the alloy with conductivity identical with base 16 (for example, P type) is injected into and is activated to form high conduction contact zone 28.

Afterwards, at the upside depositing metal layers (for example, aluminium) of silicon and in another mask stage, this metal level is formed source contact 30 and the gate contact of figure to obtain described equipment.Thereby on substrate 32, form drain contact 34 then and obtain equipment according to Fig. 1.

Though the present invention is described by specific execution mode, many other variation and modification and other application are obviously for a person skilled in the art.Therefore, preferably, the invention is not restricted to specific disclosure here, and only have claims to limit.

Claims

1, a kind of manufacture method of power semiconductor device, this method comprises:

Mask film covering body on the surface of semiconductor body;

A part of removing described mask body extends to the opening of described semiconductor body with definition;

Remove semiconductor from the bottom of described opening to define a plurality of gate trenchs and to be arranged on this gate trench termination groove on every side, described gate trench is spaced from each other by mesa structure;

Remove described mask body;

The sidewall of the described gate trench of oxidation;

The deposition gate material;

The described gate material of etching so that gate electrode stay in the described gate trench;

Inject channel dopants to define the tagma of contiguous described gate trench;

On described tagma, form source mask;

Inject source dopant to form the source electrode injection region by described source mask;

On described semiconductor body, deposit low density oxide;

Deposition contact mask;

By the described low density oxide of described contact mask etching;

At the top of described semiconductor body depositing metal layers;

The front metal mask is formed on the top at described metal level; And

The described metal level of etching is to form at least one source contact and gate runner.

2, method according to claim 1, this method also comprises:

At least on the sidewall of the sidewall of described gate trench and described termination groove, form oxidation and suppress body;

At the bottom of described gate trench and the bottom grow thick oxysome of described termination groove.

3, method according to claim 1, this method also comprises:

Before the sidewall of the described gate trench of oxidation, remove described oxidation and suppress body;

The described mesa structure of oxidation;

On described mesa structure, deposit gate material;

Etch away gate material from described mesa structure; And

Before injecting, source electrode etches away oxide from described mesa structure.

4, method according to claim 1, wherein said semiconductor body is an epitaxially grown silicon.

5, method according to claim 1, wherein said mask body are the hard masks that comprises silicon nitride.

6, method according to claim 1, wherein said oxidation suppress body and are made of silicon nitride.

7, method according to claim 1, wherein said low density oxide is made of tetraethoxysilane.

8, method according to claim 1, wherein said grid material is made of polysilicon.

9, method according to claim 1, this method also are included in definition equipotential ring opening in the described mask body; And a part of removing described semiconductor body is to be defined in the equipotential ring around the described termination groove.

10, method according to claim 1, wherein said power semiconductor device are the metal oxide layer semiconductor field-effect transistor.

11, method according to claim 1, wherein said semiconductor body are arranged on the semiconductor chip and this method also is included on the described substrate and forms metal layer on back.