CN110957351A - Super-junction MOSFET device and preparation method thereof - Google Patents
Super-junction MOSFET device and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a super junction type MOSFET device and a preparation method thereof, and relates to the field of semiconductor power devices. The method is used for solving the problem that the resistance of a JFET (junction field effect transistor) region is high due to the limitation of the width of a P-body region when the distance between the existing P columns is reduced. The device includes: a P-type column deep groove, a first epitaxial layer, a second epitaxial layer, a P-body region and N+A source region; the P-type column deep groove is positioned in the first epitaxial layer, and the second epitaxial layer is positioned on the P-type column deep groove and the upper layer of the first epitaxial layer; the P-body region is positioned in the second epitaxial layer, the P-type column deep groove is positioned right below the P-body region, and the width of the P-body region is smaller than that of the P-type column deep groove; two of N+The source regions are respectively positioned at two sides of the P-body region.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a super junction type MOSFET device and a preparation method thereof.
Background
A Metal-Oxide-Semiconductor Field effect transistor (MOSFET), referred to as a MOSFET for short, is a Field effect transistor that can be widely used in analog circuits and digital circuits.
In order to reduce the power loss of power components used in a DC-DC (direct current to direct current) converter, in MOSFET power components, the power loss generated during the operation of MOS (metal oxide semiconductor) devices can be effectively reduced by reducing the on-resistance of the components. In practical applications, the breakdown voltage of the MOS device is inversely proportional to the on-resistance, so that when the on-resistance is reduced, the breakdown voltage is adversely affected. The traditional super-junction device has the problem of thermal diffusion, so that the phenomenon of uneven charge distribution caused by mutual diffusion of a P-type column and an N-type column in a body area of the super-junction structure can be caused, and the problem of low breakdown voltage generated when the device works can be influenced. Meanwhile, with the continuous reduction of the design size of components, cost control is the largest bottleneck of each current process platform, so that on the premise of consistent device characteristics, the cost control becomes a key factor for improving the main competitiveness of the components in the market.
The manufacturing process of the conventional super junction type power device is shown in fig. 1A to 1D, and specifically comprises the following steps: 1) forming a P-type columnar junction by etching the deep trench and growing an epitaxial process; 2) forming a gate oxide layer and a polysilicon gate of the device, and finishing etching the polysilicon gate; 3) forming the P-body region of the device, and N+A source region; 4) and forming an insulating medium layer, a contact hole and a metal contact of the device.
In the above manufacturing process, since the concentration of the P-type pillar structure is high, the P-body region must be wider than the P-type pillar, as shown in fig. 1D as L1> L2, otherwise the channel concentration is too dense and the turn-on voltage is difficult to control. However, as the feature size of the device is reduced, the L1 cannot be reduced without limit because the L2 in the JFET (field-effect transistor) region of the device must be ensured to have a certain width, and the resistance of the JFET region is reduced, thereby reducing the on-resistance of the whole device.
In summary, since the concentration of P + pillars is higher than the body region concentration in the conventional MOSFET process, the distance between P pillars is limited by the width of P-body region when the distance between P pillars is reduced, resulting in a problem of relatively high resistance of the JFET region.
Disclosure of Invention
The embodiment of the invention provides a super junction type MOSFET device and a preparation method thereof, which are used for solving the problem that the resistance of a JFET (junction field effect transistor) area is high due to the limitation of the width of a P-body area when the distance between existing P columns is shortened.
The embodiment of the invention provides a super junction type MOSFET device, which comprises: a P-type column deep trench, a first epitaxial layer, a second epitaxial layer, a P-body region and an N+A source region;
the P-type column deep groove is positioned in the first epitaxial layer, and the second epitaxial layer is positioned on the P-type column deep groove and the upper layer of the first epitaxial layer;
the P-body region is positioned in the second epitaxial layer, the P-type column deep groove is positioned right below the P-body region, and the width of the P-body region is smaller than that of the P-type column deep groove;
two of N+The source regions are respectively positioned at two sides of the P-body region.
Preferably, the device also comprises a polysilicon grid and a grid oxide layer;
the gate oxide layer and the polysilicon gate are sequentially arranged on the second epitaxial layer and extend to the P-body region and the N+An upper layer of the source region.
Preferably, the device further comprises an insulating oxide layer and a metal layer;
the insulation oxide layer is positioned on the upper layer of the polysilicon gate, and part of the insulation oxide layer extends out of the polysilicon gate and is positioned on part of the N+An upper layer of the source region;
the metal layer is arranged on the upper layer of the insulating oxide layer, and part of the metal layer extends out of the insulating oxide layer and is arranged on part of the N+Source region and portionAnd the upper layer of the P-body region is divided.
Preferably, the epitaxial wafer further comprises a substrate layer, and the substrate layer is located right below the first epitaxial layer.
The embodiment of the invention also provides a preparation method of the super junction type MOSFET device, which comprises the following steps:
forming a P-type column deep groove in the first epitaxial layer by an etching method, and forming a second epitaxial layer on the upper surface of the P-type column deep groove and above the first epitaxial layer;
forming a gate oxide layer and a polysilicon gate above the second epitaxial layer;
forming a P-body region in the second epitaxial layer above the P-type column deep groove by an ion implantation method;
forming two N in the P-body region by ion implantation+A source region;
and sequentially forming an insulating oxide layer and a metal layer on the upper layer of the polysilicon gate.
Preferably, the forming of the gate oxide layer and the polysilicon gate above the second epitaxial layer specifically includes:
and depositing an oxide layer and a polysilicon layer above the second epitaxial layer in sequence, etching the oxide layer and the polysilicon layer above the P-type column deep groove, wherein the width of the etched oxide layer and the etched polysilicon layer is smaller than the width of the groove of the P-type column deep groove.
Preferably, the forming a P-body region in the second epitaxial layer above the P-type pillar deep trench by an ion implantation method specifically includes:
and carrying out first ion implantation on the second epitaxial layer positioned above the P-type column deep groove to form the P-body region.
Preferably, the two N-regions are formed in the P-body region by ion implantation+The source region specifically includes:
performing second ion implantation on the P-body region on the second epitaxial layer, and forming the N on two sides of the P-body region respectively+And a source region.
Preferably, the sequentially forming an insulating oxide layer and a metal layer on the polysilicon gate upper layer specifically includes:
forming an insulating oxide layer on the upper layer of the polysilicon gate and the upper layer of the second epitaxial layer, etching the insulating oxide layer on the second epitaxial layer by an etching method, wherein the width of the etched insulating oxide layer is smaller than the width between two adjacent polysilicon gates;
and forming a metal layer on the insulating oxide layer and the second epitaxial layer by a metal precipitation method.
The embodiment of the invention provides a super junction type MOSFET device and a preparation method thereof, wherein the device comprises: a P-type column deep groove, a first epitaxial layer, a second epitaxial layer, a P-body region and N+A source region; the P-type column deep groove is positioned in the first epitaxial layer, and the second epitaxial layer is positioned on the P-type column deep groove and the upper layer of the first epitaxial layer; the P-body region is positioned in the second epitaxial layer, the P-type column deep groove is positioned right below the P-body region, and the width of the P-body region is smaller than that of the P-type column deep groove; two of N+The source regions are respectively positioned at two sides of the P-body region. In the super junction type MOSFET device, a first epitaxial layer and a second epitaxial layer are sequentially formed in a multi-epitaxial layer injection mode, a P-type column deep groove is formed in the first epitaxial layer, a P-body area is formed in the second epitaxial layer, the P-body area in the second epitaxial layer can be completely positioned on the upper layer of the P-type column deep groove, the width of the P-body area is smaller than that of the P-type column deep groove, the distance between every two adjacent P-body areas is larger than that between every two adjacent P-type column deep grooves, and the structure can effectively reduce the size of a unit cell; further, if the distance between the P-type pillar deep grooves in the first epitaxial layer can be small enough, the distance between the P-body regions in the second epitaxial layer can also be adjusted through the process, so that the JFET region with low enough resistance can be obtained. The super junction type MOSFET device provided by the embodiment of the invention solves the problem that the resistance of a JFET (junction field effect transistor) area is high due to the limitation of the width of a P-body area when the distance between the existing P-type column deep grooves is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without any creative effort.
Fig. 1A is a schematic diagram illustrating an epitaxial layer and a P-type columnar junction prepared in the prior art;
FIG. 1B is a schematic diagram of a gate oxide and polysilicon gate fabrication provided in the prior art;
FIG. 1C shows a P-body region and N provided in the prior art+Preparing a schematic diagram of a source region;
FIG. 1D is a schematic diagram illustrating the fabrication of an insulating dielectric layer, a contact hole and a metal contact provided in the prior art;
fig. 2 is a schematic diagram of a super junction MOSFET device according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of a super junction MOSFET device manufacturing process according to an embodiment of the present invention;
FIG. 4A is a schematic diagram illustrating the fabrication of an epitaxial layer and P-type columnar junctions according to an embodiment of the present invention;
FIG. 4B is a schematic view of a second epitaxial layer fabrication according to an embodiment of the present invention;
FIG. 4C is a schematic diagram of the gate oxide layer and polysilicon gate fabrication provided by the embodiment of the invention
FIG. 4D is a schematic illustration of the fabrication of a P-body region according to an embodiment of the present invention;
FIG. 4E shows a diagram of N according to an embodiment of the present invention+Preparing a schematic diagram of a source region;
FIG. 4F is a schematic diagram illustrating the preparation of an insulating dielectric layer according to an embodiment of the present invention;
fig. 4G is a schematic diagram illustrating the preparation of a contact hole and a metal contact according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1A to fig. 1D are schematic diagrams of a super junction type power device manufacturing structure provided in the prior art, and a manufacturing process of the super junction type power device mainly includes the following steps:
step 11, as shown in fig. 1A, forming an N-type lightly doped epitaxial layer 102 on an N-type heavily doped substrate 101 on the provided N-type heavily doped substrate 101, etching the N-type lightly doped epitaxial layer 102, and forming a P-type columnar junction 103 in the N-type lightly doped epitaxial layer 102.
Step 12, as shown in fig. 1B, a gate oxide layer 104 is formed on the surface of the N-type lightly doped epitaxial layer 102 between the P-type columnar junctions 103, and a polysilicon gate 105 is formed on the surface of the gate oxide layer 104.
Step 13, As shown in fig. 1C, B implantation and diffusion are performed on the upper portion of the N-type lightly doped epitaxial layer 102 to form a P-type body region 106, As implantation and diffusion are performed on the upper portion of the N-type lightly doped epitaxial layer 102 to form an N-type body region 106+A source region 107.
Step 14, as shown in fig. 1D, a growth thickening process is performed on the upper portion of the N-type lightly doped epitaxial layer 102 and the upper portion of the polysilicon gate 105 to form an oxide insulation layer 108.
As shown in fig. 1D, since the concentration of the P-type column junctions 103 is higher than that of the P-type body regions 106 in the conventional MOSFET process, the distance between the P-type column junctions 103 must not be too close to leave enough diffusion space for the P-type body regions 106 in consideration of the turn-on voltage of the device. Therefore, the width of the P-body 106 must be larger than that of the P-type pillar 103, otherwise the channel concentration is too dense and the turn-on voltage is difficult to control. In order to solve the above problem, embodiments of the present invention provide a super junction MOSFET device in which the distance between P-type columnar junctions 103 is smaller than the distance between P-body regions 106, which can effectively reduce the cell size and increase the resistance of the JFET region. The manufacturing cost of the device is not increased on the premise of ensuring that the performance of the device can be improved.
Fig. 2 schematically illustrates a structure of a super junction MOSFET device provided by an embodiment of the present invention, as shown in fig. 2, the super junction MOSFET device mainly includes a P-type deep pillar trench 203, a first epitaxial layer 202, a second epitaxial layer 204, a P-body region 207, and an N-body region+A source region 208.
As shown in fig. 2, the epitaxial layers of the super junction MOSFET device provided by the embodiment of the present invention include a first epitaxial layer 202 and a second epitaxial layer 204, wherein a P-type column deep trench 203 is located in the first epitaxial layer 202, and a P-body region 207 is located in the second epitaxial layer 204.
Specifically, the first epitaxial layer 202 is located above the substrate layer 201, the P-type pillar deep groove 203 is located in the first epitaxial layer 202, a notch of the P-type pillar deep groove 203 is located on the upper surface of the first epitaxial layer 202, the P-type pillar deep groove 203 vertically extends downwards from the upper surface of the first epitaxial layer 202, and the depth of the P-type pillar deep groove 203 is smaller than the thickness of the first epitaxial layer 202. Accordingly, the second epitaxial layer 204 is located on the upper surfaces of the P-type pillar deep trench 203 and the first epitaxial layer 202, i.e., the upper surface of the P-type pillar deep trench 203 is in contact with the lower surface of the second epitaxial layer 204.
Further, P-body region 207 is located within second epitaxial layer 204, the notch of P-body region 207 is located on the upper surface of second epitaxial layer 204, the depth of P-body region 207 is consistent with the thickness of second epitaxial layer 204, and P-body region 207 is located just above P-pillar deep trench 203. In the prior art, since the P-type deep trenches 203 and the P-body regions 207 are both located in the first epitaxial layer 202, and since the concentration of the P-type deep trenches 203 is higher than that of the P-body regions 207, the distance between the P-type deep trenches 203 is relatively large, i.e., the width of the P-body regions 207 must be larger than that of the P-type deep trenches 203, otherwise the channel concentration is too strong, and the turn-on voltage is difficult to control. In the embodiment of the present invention, since the P-type pillar deep trench 203 and the P-body region 207 are respectively located in two different epitaxial layers, after the second epitaxial layer 204 is subjected to the body region implantation and drive-in process, the drive-in width of the body region of the second epitaxial layer 204 is smaller than the width of the P-type pillar deep trench 203, that is, the width of the P-body region 207 located right above the P-type pillar deep trench 203 is smaller than the width of the P-type pillar deep trench 203, and the distance between the two P-body regions 207 is greater than the distance between the two P-type pillar deep trenches 203.
Further, N is distributed on two sides above the P-body region 207+A source region 208.
As shown in fig. 2, a gate oxide layer 205 and a polysilicon gate 206 are further included and disposed above the second epitaxial layer 204, and both ends of the gate oxide layer 205 and the polysilicon gate 206 extend to the P-body region 207 and the N-body region 207+Above the source region 208, further, an insulating oxide layer 209 is disposed above and beside the gate oxide layer 205 and the polysilicon gate 206, that is, the gate oxide layer 205 and the polysilicon gate 206 are wrapped by the insulating oxide layer, and the metal layer 210 is disposed above the insulating oxide layer and the second epitaxial layer 204, where it should be noted that the second epitaxial layer 204 refers to a region not covered by the gate oxide layer 205, the polysilicon gate 206 and the insulating oxide layer. As shown in fig. 2, the region of the metal layer 210 overlying the second epitaxial layer 204 is located just above the P-body region 207, i.e., the metal layer 210 is disposed on the oxide insulating layer and part of the P-body region 207 and part of the N+An upper layer of source region 208.
In order to more clearly introduce the super junction MOSFET device provided by the embodiment of the present invention, a method for manufacturing the super junction MOSFET device is described below.
Fig. 3 is a schematic flow chart of a method for manufacturing a super junction MOSFET device according to an embodiment of the present invention, and fig. 4A is a schematic diagram of an epitaxial layer and a P-type columnar junction according to an embodiment of the present invention; FIG. 4B is a schematic view of a second epitaxial layer fabrication according to an embodiment of the present invention; fig. 4C is a schematic diagram illustrating the preparation of a gate oxide layer and a polysilicon gate according to an embodiment of the invention; FIG. 4D is a schematic illustration of the fabrication of a P-body region according to an embodiment of the present invention; FIG. 4E shows a diagram of N according to an embodiment of the present invention+Preparing a schematic diagram of a source region; FIG. 4F is a schematic diagram illustrating the preparation of an insulating dielectric layer according to an embodiment of the present invention; fig. 4G is a schematic diagram illustrating the contact hole and metal contact preparation according to an embodiment of the invention.
The following describes in detail a method for manufacturing a super junction MOSFET device with reference to a schematic flow diagram of the manufacturing method provided in fig. 3 and the schematic diagrams provided in fig. 4A to 4G, and specifically, as shown in fig. 3, the method mainly includes the following steps:
in step 25, an insulating oxide layer 209 and a metal layer 210 are sequentially formed on the polysilicon gate 206.
In step 21, as shown in fig. 4A, a first epitaxial layer 202 of N type of the first conductivity type with low doping concentration is grown on the semiconductor substrate of N type of the first conductivity type with high doping concentration. Further, the first epitaxial layer 202 of the first conductivity type is selectively masked and etched to obtain a desired P-type pillar deep trench 203 in the first epitaxial layer 202 of the first conductivity type, a notch of the P-type pillar deep trench 203 is located on an upper surface of the first epitaxial layer 202 of the first conductivity type, the P-type pillar deep trench 203 vertically extends downward from an upper end surface of the first epitaxial layer 202 of the first conductivity type, and a depth of the P-type pillar deep trench 203 is smaller than a thickness of the first epitaxial layer 202 of the first conductivity type. The material of the semiconductor substrate includes silicon.
Further, as shown in fig. 4B, an N-type second epitaxial layer 204 with a low doping concentration of the first conductivity type is grown on the first conductivity type first epitaxial layer 202 provided with the P-type pillar deep trench 203, wherein the thickness of the first conductivity type second epitaxial layer 204 is smaller than that of the first conductivity type first epitaxial layer 202.
In step 22, as shown in fig. 4C, an oxide layer is grown on the surface of the first conductivity type second epitaxial layer 204 by an oxidation process, and a polysilicon layer is deposited on the oxide layer by an LPCVD process, wherein the oxide layer may also be referred to as a gate oxide layer 205.
Further, the polysilicon layer is exposed through a photolithography process, a region of the gate polycrystalline layer is defined, then the polysilicon layer and the gate oxide layer 205 on the top of the first conductive type second epitaxial layer 204 are removed through dry etching, the polysilicon layer and the gate oxide layer 205 which are not protected by the photoresist are removed, the first conductive type second epitaxial layer 204 corresponding to the source region is exposed, and then the photoresist is removed, so that the region of the gate polycrystalline layer is formed.
In step 23 and step 24, as shown in fig. 4D and 4E, a first P-type well implantation region is defined by a photolithography process, a first ion implantation doping element is performed on the first conductive type second epitaxial layer 204 to form a P-body region 207, and the doping element is activated by an annealing process; defining N by photolithography+ A source region 208 implantation region for forming a second conductivity type N on both sides of the P-body region 207 by performing a second ion implantation into the first conductivity type second epitaxial layer 204+ Source region 208, which is activated by an annealing process.
It should be noted that the P-body region 207 formed by performing the first ion implantation is located right above the P-type pillar deep trench 203, and the width of the P-body region 207 is smaller than the width of the P-type pillar deep trench 203, that is, the distance between two adjacent P-body regions 207 is smaller than the distance between the P-type pillar deep trenches 203. Through the above process, the problem that in the prior art, the distance between the P-type pillar deep grooves 203 is relatively large due to the fact that the concentration of the P-type pillar deep grooves 203 is higher than that of the P-body region 207, namely the width of the P-body region 207 must be larger than that of the P-type pillar deep grooves 203, otherwise, the channel concentration is too high, and the starting voltage is difficult to control can be solved.
In step 25, as shown in fig. 4F, an insulating dielectric layer is formed by depositing an oxide layer over the polysilicon gate 206, wherein an insulating oxide layer 209 extends from over the polysilicon gate 206 to the top surface of the first conductivity type second epitaxial layer 204, wherein the first conductivity type second epitaxial layer is shownThe upper surface of layer 204 represents portion N+ A source region 208. And contact holes are formed in the regions of the upper surface of the first conductive-type second epitaxial layer 204 not covered by the insulating oxide layer 209.
Further, as shown in fig. 4G, metal filling is performed over the contact hole and the insulating oxide layer 209, forming a metal layer 210.
In summary, the embodiments of the present invention provide a super junction MOSFET device and a manufacturing method thereof, where the device includes: a P-type column deep groove, a first epitaxial layer, a second epitaxial layer, a P-body region and N+A source region; the P-type column deep groove is positioned in the first epitaxial layer, and the second epitaxial layer is positioned on the P-type column deep groove and the upper layer of the first epitaxial layer; the P-body region is positioned in the second epitaxial layer, the P-type column deep groove is positioned right below the P-body region, and the width of the P-body region is smaller than that of the P-type column deep groove; two of N+The source regions are respectively positioned at two sides of the P-body region. In the super junction type MOSFET device, a first epitaxial layer and a second epitaxial layer are sequentially formed in a multi-epitaxial layer injection mode, a P-type column deep groove is formed in the first epitaxial layer, a P-body area is formed in the second epitaxial layer, the P-body area in the second epitaxial layer can be completely positioned on the upper layer of the P-type column deep groove, the width of the P-body area is smaller than that of the P-type column deep groove, the distance between two adjacent P-body areas is larger than that between two adjacent P-type column deep grooves, and the structure can effectively reduce the size of a unit cell; further, if the distance between the P-type pillar deep grooves in the first epitaxial layer can be small enough, the distance between the P-body regions in the second epitaxial layer can also be adjusted by the process, so that the JFET region with low enough resistance can be obtained. The super junction type MOSFET device provided by the embodiment of the invention solves the problem that the resistance of a JFET (junction field effect transistor) area is higher due to the limitation of the width of a P-body area when the distance between the existing P-type column deep grooves is reduced.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (9)
1. A super junction type MOSFET device, comprising: a P-type column deep groove, a first epitaxial layer, a second epitaxial layer, a P-body region and N+A source region;
the P-type column deep groove is positioned in the first epitaxial layer, and the second epitaxial layer is positioned on the P-type column deep groove and the upper layer of the first epitaxial layer;
the P-body region is positioned in the second epitaxial layer, the P-type column deep groove is positioned right below the P-body region, and the width of the P-body region is smaller than that of the P-type column deep groove;
two of N+The source regions are respectively positioned at two sides of the P-body region.
2. The device of claim 1, further comprising a polysilicon gate and a gate oxide;
the gate oxide layer and the polysilicon gate are sequentially arranged on the second epitaxial layer and extend to the P-body region and the N+An upper layer of the source region.
3. The device of claim 2, further comprising an insulating oxide layer and a metal layer;
the insulation oxide layer is positioned on the upper layer of the polysilicon gate, and part of the insulation oxide layer extends out of the polysilicon gate and is positioned on part of the N+An upper layer of the source region;
the metal layer is arranged on the upper layer of the insulating oxide layer, and part of the metal layer extends out of the insulating oxide layer and is arranged on part of the N+A source region and a portion of the upper layer of the P-body region.
4. The device of claim 1, further comprising a substrate layer directly below the first epitaxial layer.
5. A method for manufacturing a super junction type MOSFET device is characterized by comprising the following steps:
forming a P-type column deep groove in the first epitaxial layer by an etching method, and forming a second epitaxial layer on the upper surface of the P-type column deep groove and above the first epitaxial layer;
forming a gate oxide layer and a polysilicon gate above the second epitaxial layer;
forming a P-body region in the second epitaxial layer above the P-type column deep groove by an ion implantation method;
forming two N in the P-body region by ion implantation+A source region;
and sequentially forming an insulating oxide layer and a metal layer on the upper layer of the polysilicon gate.
6. The method of claim 5, wherein forming a gate oxide layer and a polysilicon gate over the second epitaxial layer comprises:
and depositing an oxide layer and a polysilicon layer above the second epitaxial layer in sequence, etching the oxide layer and the polysilicon layer above the P-type column deep groove, wherein the width of the etched oxide layer and the etched polysilicon layer is smaller than the width of the groove of the P-type column deep groove.
7. The method of claim 5, wherein said forming a P-body region in said second epitaxial layer above said P-pillar deep trench by ion implantation comprises:
and carrying out first ion implantation on the second epitaxial layer positioned above the P-type column deep groove to form the P-body region.
8. The method of claim 5, wherein said forming two N's in said P-body region by ion implantation+The source region specifically includes:
performing second ion implantation on the P-body region on the second epitaxial layer, and forming the N on two sides of the P-body region respectively+And a source region.
9. The method of claim 5, wherein sequentially forming an insulating oxide layer and a metal layer on the polysilicon gate comprises:
forming an insulating oxide layer on the upper layer of the polysilicon gate and the upper layer of the second epitaxial layer, etching the insulating oxide layer on the second epitaxial layer by an etching method, wherein the width of the etched insulating oxide layer is smaller than the width between two adjacent polysilicon gates;
and forming a metal layer on the insulating oxide layer and the second epitaxial layer by a metal precipitation method.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10008570A1 (en) * | 2000-02-24 | 2001-09-13 | Infineon Technologies Ag | Semiconductor device with compensation structure e.g. vertical FET |
| JP2002373987A (en) * | 2001-06-13 | 2002-12-26 | Sanken Electric Co Ltd | Insulated gate field effect transistor |
| DE10245049A1 (en) * | 2002-09-26 | 2004-04-08 | Infineon Technologies Ag | Semiconductor component to be controlled by field effect subject to charged particle compensation fits in a semiconductor body |
| US6849880B1 (en) * | 2003-09-09 | 2005-02-01 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| CN101258582A (en) * | 2005-07-08 | 2008-09-03 | 意法半导体股份有限公司 | Power field effect transistor and manufacturing method thereof |
| US20090267174A1 (en) * | 2008-04-29 | 2009-10-29 | Infineon Technologies Austria Ag | Semiconductor device with a charge carrier compensation structure in a semiconductor body and method for its production |
| US20090315070A1 (en) * | 2008-05-15 | 2009-12-24 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device |
| US20100096692A1 (en) * | 2008-10-16 | 2010-04-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN103311279A (en) * | 2012-03-14 | 2013-09-18 | 英飞凌科技股份有限公司 | Semiconductor device and method for manufacturing the semiconductor device |
| CN105529262A (en) * | 2014-09-29 | 2016-04-27 | 无锡华润华晶微电子有限公司 | Vertical double diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN105845713A (en) * | 2015-01-29 | 2016-08-10 | 富士电机株式会社 | Semiconductor device |
| US20190148484A1 (en) * | 2017-11-15 | 2019-05-16 | Infineon Technologies Dresden GmbH & Co. KG | Semiconductor Device with Buffer Region |
| JP2019165217A (en) * | 2018-03-20 | 2019-09-26 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| CN211017082U (en) * | 2019-12-17 | 2020-07-14 | 华羿微电子股份有限公司 | Super junction type MOSFET device |
-
2019
- 2019-12-17 CN CN201911298717.8A patent/CN110957351A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10008570A1 (en) * | 2000-02-24 | 2001-09-13 | Infineon Technologies Ag | Semiconductor device with compensation structure e.g. vertical FET |
| JP2002373987A (en) * | 2001-06-13 | 2002-12-26 | Sanken Electric Co Ltd | Insulated gate field effect transistor |
| DE10245049A1 (en) * | 2002-09-26 | 2004-04-08 | Infineon Technologies Ag | Semiconductor component to be controlled by field effect subject to charged particle compensation fits in a semiconductor body |
| US6849880B1 (en) * | 2003-09-09 | 2005-02-01 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| CN101258582A (en) * | 2005-07-08 | 2008-09-03 | 意法半导体股份有限公司 | Power field effect transistor and manufacturing method thereof |
| US20090267174A1 (en) * | 2008-04-29 | 2009-10-29 | Infineon Technologies Austria Ag | Semiconductor device with a charge carrier compensation structure in a semiconductor body and method for its production |
| US20090315070A1 (en) * | 2008-05-15 | 2009-12-24 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device |
| US20100096692A1 (en) * | 2008-10-16 | 2010-04-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN103311279A (en) * | 2012-03-14 | 2013-09-18 | 英飞凌科技股份有限公司 | Semiconductor device and method for manufacturing the semiconductor device |
| CN105529262A (en) * | 2014-09-29 | 2016-04-27 | 无锡华润华晶微电子有限公司 | Vertical double diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN105845713A (en) * | 2015-01-29 | 2016-08-10 | 富士电机株式会社 | Semiconductor device |
| US20190148484A1 (en) * | 2017-11-15 | 2019-05-16 | Infineon Technologies Dresden GmbH & Co. KG | Semiconductor Device with Buffer Region |
| JP2019165217A (en) * | 2018-03-20 | 2019-09-26 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| CN211017082U (en) * | 2019-12-17 | 2020-07-14 | 华羿微电子股份有限公司 | Super junction type MOSFET device |
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