JP2002373987A - Insulated gate field effect transistor - Google Patents
Insulated gate field effect transistorInfo
- Publication number
- JP2002373987A JP2002373987A JP2001179249A JP2001179249A JP2002373987A JP 2002373987 A JP2002373987 A JP 2002373987A JP 2001179249 A JP2001179249 A JP 2001179249A JP 2001179249 A JP2001179249 A JP 2001179249A JP 2002373987 A JP2002373987 A JP 2002373987A
- Authority
- JP
- Japan
- Prior art keywords
- region
- field effect
- insulated gate
- electrode layer
- effect transistor
- Prior art date
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- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、動作効率の高い絶
縁ゲート型電界効果トランジスタに関する。The present invention relates to an insulated gate field effect transistor having high operation efficiency.
【０００２】[0002]
【従来の技術】産業用パワースイッチ等に用いられるパ
ワーデバイスとして、絶縁ゲート型電界効果トランジス
タ（Field Effect Transistor：ＦＥＴ）等が使用され
ている。このような絶縁ゲート型ＦＥＴは、一般に高電
圧下で使用され、高耐圧特性が要求されるとともに、高
速のスイッチング速度が要求される。2. Description of the Related Art As a power device used for an industrial power switch, an insulated gate field effect transistor (FET) is used. Such an insulated gate FET is generally used under a high voltage, and is required to have a high withstand voltage characteristic and a high switching speed.
【０００３】絶縁ゲート型ＦＥＴは、例えば、Ｎ形のド
リフト領域と、Ｎ＋型のドレイン領域と、Ｐ形の複数の
ベース領域と、Ｎ＋型の複数のソース領域と、を備える
半導体基板と、ドレイン領域に接続するドレイン電極
と、ソース領域に接続するソース電極と、ドリフト領域
とソース領域との間のベース領域（チャネル領域）の上
方に絶縁膜を介して設けられたゲート電極と、を備え
る。An insulated gate FET includes, for example, a semiconductor substrate including an N-type drift region, an N + -type drain region, a plurality of P-type base regions, and a plurality of N + -type source regions. A drain electrode connected to the drain region, a source electrode connected to the source region, and a gate electrode provided via an insulating film above a base region (channel region) between the drift region and the source region. Prepare.
【０００４】高い耐圧特性を得るため、ベース領域を柱
状に形成した絶縁ゲート型ＦＥＴが開発されている。こ
の絶縁ゲート型ＦＥＴは、ベース領域が、ドリフト領域
中をドレイン電極側に柱状に延伸し、その底面がドレイ
ン領域とドリフト領域との界面近くにまで達した構造を
有する。In order to obtain high withstand voltage characteristics, insulated gate FETs having a base region formed in a columnar shape have been developed. This insulated gate FET has a structure in which a base region extends in a columnar shape in a drift region toward a drain electrode, and a bottom surface thereof reaches near an interface between the drain region and the drift region.
【０００５】上記した柱状のベース領域を複数備える絶
縁ゲート型ＦＥＴでは、ベース領域とドリフト領域との
間に形成されるＰＮ接合に逆バイアスが印加されたとき
には、ＰＮ接合により形成される空乏層が、ベース領域
間のドリフト領域全体に拡がる。これにより、電界の集
中は緩和され、高い耐圧が得られる。また、高耐圧が得
られることにより、ドリフト領域の不純物濃度を高く設
定して低抵抗とすることができる。In an insulated gate FET having a plurality of columnar base regions, when a reverse bias is applied to a PN junction formed between the base region and the drift region, a depletion layer formed by the PN junction is formed. , Spread over the entire drift region between the base regions. Thereby, the concentration of the electric field is reduced, and a high withstand voltage is obtained. Further, since a high withstand voltage can be obtained, the impurity concentration of the drift region can be set high to reduce the resistance.
【０００６】例えば、柱状のベース領域でなく、浅いベ
ース領域を用いた場合と比べ、ドリフト領域の比抵抗を
１／３〜１／５に設定しても、浅いベース領域を用いた
構造と同等の耐圧が得られる。For example, as compared with the case where a shallow base region is used instead of a columnar base region, even if the resistivity of the drift region is set to 1/3 to 1/5, the structure is equivalent to a structure using a shallow base region. Is obtained.
【０００７】[0007]
【発明が解決しようとする課題】上記絶縁ゲート型ＦＥ
Ｔの動作時には、ゲート−ドレイン間およびゲート−ソ
ース間に必然的に入力容量が発生する。ゲート−ドレイ
ン間容量およびゲート−ソース間容量が過大である場合
には、スイッチング速度が低下するなどの不具合が起こ
る。The above-mentioned insulated gate type FE
During the operation of T, an input capacitance is inevitably generated between the gate and the drain and between the gate and the source. If the gate-drain capacitance and the gate-source capacitance are excessive, problems such as a decrease in switching speed occur.
【０００８】入力容量のうち、ゲート−ドレイン間容量
を低減させるため、ドリフト領域の上面のゲート酸化膜
のうち、チャネル領域上の酸化膜を選択的に厚く形成す
る方法が知られている。しかしながら、ゲート−ドレイ
ン間容量に関しては、これを低減する効果的な方法は未
だ開発されていない。このように、従来の絶縁ゲート型
ＦＥＴは、十分に入力容量が低減された、高い動作効率
を有するものではなかった。In order to reduce the gate-drain capacitance of the input capacitance, a method of selectively forming a thick oxide film on a channel region among gate oxide films on the upper surface of a drift region is known. However, regarding the gate-drain capacitance, an effective method for reducing this has not yet been developed. As described above, the conventional insulated gate FET has not sufficiently reduced input capacitance and high operating efficiency.
【０００９】上記事情を鑑みて、本発明は、動作効率の
高い絶縁ゲート型電界効果トランジスタを提供すること
を目的とする。また、本発明は、入力容量の低減された
絶縁ゲート型電界効果トランジスタを提供することを目
的とする。In view of the above circumstances, an object of the present invention is to provide an insulated gate field effect transistor having high operation efficiency. Another object of the present invention is to provide an insulated gate field effect transistor with reduced input capacitance.
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するた
め、本発明の第１の観点にかかる絶縁ゲート型電界効果
トランジスタは、半導体基板上に設けられた第１導電型
のドレイン領域と、前記ドレイン領域上に設けられ、前
記ドレイン領域よりも不純物濃度の低い第１導電型のド
リフト領域と、前記ドリフト領域内に島状に設けられた
第２導電型のベース領域と、前記ベース領域内に島状に
設けられ、前記ドリフト領域よりも不純物濃度の高い第
１導電型のソース領域と、前記ドリフト領域と前記ソー
ス領域とに挟まれた前記ベース領域の露出面を、間欠的
に覆うように設けられたゲート電極層と、を備えること
を特徴とする。In order to achieve the above object, an insulated gate field effect transistor according to a first aspect of the present invention comprises: a first conductivity type drain region provided on a semiconductor substrate; A first conductivity type drift region provided on the drain region and having a lower impurity concentration than the drain region; a second conductivity type base region provided in the drift region in an island shape; A first conductivity type source region provided in an island shape and having a higher impurity concentration than the drift region, and an exposed surface of the base region interposed between the drift region and the source region is intermittently covered. And a gate electrode layer provided.
【００１１】上記構成によれば、絶縁ゲート型の電界効
果トランジスタにおいて、ゲート電極層はベース領域を
間欠的に覆うように構成されていることにより、ゲート
電極層とベース領域との対向面積は実質的に減少する。
これにより、ゲート−ソース間の寄生容量は低減され、
スイッチング特性等が高く、動作効率の高い絶縁ゲート
型電界効果トランジスタが提供される。According to the above configuration, in the insulated gate field effect transistor, since the gate electrode layer is configured to intermittently cover the base region, the facing area between the gate electrode layer and the base region is substantially reduced. Decrease.
Thereby, the parasitic capacitance between the gate and the source is reduced,
An insulated gate field effect transistor having high switching characteristics and the like and high operation efficiency is provided.
【００１２】上記構成において、前記ゲート電極層は、
例えば、前記露出面と重なる孔を有する。ゲート電極層
が、このような露出面と重なる孔を有することにより、
ゲート電極層は、ベース領域の露出面を間欠的に覆うこ
ととなる。[0012] In the above structure, the gate electrode layer comprises:
For example, it has a hole overlapping the exposed surface. When the gate electrode layer has a hole overlapping with such an exposed surface,
The gate electrode layer intermittently covers the exposed surface of the base region.
【００１３】上記構成において、前記露出面は環状に形
成され、前記孔は、例えば、前記環状の露出面の内径と
略同径を有する円形の第１の領域と、前記円形の第１の
領域から外側に切り込まれた第２の領域と、を備え、前
記第２の領域は前記環状の露出面の一部と重なる。In the above structure, the exposed surface is formed in an annular shape, and the hole has, for example, a circular first region having substantially the same diameter as the inner diameter of the annular exposed surface, and a circular first region. A second region cut out from the outside, and the second region overlaps a part of the annular exposed surface.
【００１４】上記構成によれば、ソース領域は第１の領
域を介して露出し、ソース電極と接続可能となる。ま
た、第２の領域を介してベース領域の露出面が露出する
ことにより、ゲート電極層と対向し、ゲート電圧印加時
にはチャネルとして機能する露出面をある程度確保しつ
つ、ゲート電極層とベース領域との対向面積を低減させ
ることができる。According to the above configuration, the source region is exposed through the first region and can be connected to the source electrode. Further, by exposing the exposed surface of the base region through the second region, the exposed surface of the base region is opposed to the gate electrode layer. Can be reduced.
【００１５】上記構成において、例えば、前記第２の領
域は前記環状の露出面の外径よりも大径の扇状に設けら
れている。また、前記第２の領域は、前記第１の領域の
周囲に略等間隔に複数設けられていることが好ましい。
例えば、前記第２の領域は、前記第１の領域の周囲に３
つ設けられている。In the above configuration, for example, the second region is provided in a fan shape having a diameter larger than the outer diameter of the annular exposed surface. Further, it is preferable that a plurality of the second regions are provided at substantially equal intervals around the first region.
For example, the second area may be surrounded by 3 around the first area.
One is provided.
【００１６】上記目的を達成するため、本発明の第２の
観点にかかる絶縁ゲート型電界効果トランジスタは、半
導体基板上に設けられた第１導電型のドレイン領域と、
前記ドレイン領域上に設けられ、前記ドレイン領域より
も不純物濃度の低い第１導電型のドリフト領域と、前記
ドリフト領域内に島状に設けられた第２導電型のベース
領域と、前記ベース領域内に島状に設けられ、前記ドリ
フト領域よりも不純物濃度の高い第１導電型のソース領
域と、前記ドリフト領域と前記ソース領域とに挟まれた
前記ベース領域の露出面を、絶縁膜を介して覆うように
設けられたゲート電極層と、を備え、前記ベース領域の
露出面は、前記ゲート電極層に覆われた第１の表面領域
と、前記ゲート電極層に覆われていない第２の表面領域
と、を備える、ことを特徴とする。To achieve the above object, an insulated gate field effect transistor according to a second aspect of the present invention comprises a first conductivity type drain region provided on a semiconductor substrate,
A first conductivity type drift region provided on the drain region and having a lower impurity concentration than the drain region; a second conductivity type base region provided in an island shape in the drift region; A source region of the first conductivity type having an impurity concentration higher than that of the drift region, and an exposed surface of the base region sandwiched between the drift region and the source region, with an insulating film interposed therebetween. A gate electrode layer provided so as to cover the first surface region covered with the gate electrode layer, and a second surface not covered with the gate electrode layer. And a region.
【００１７】上記構成において、ベース領域は、ゲート
電極層に覆われた第１の表面領域を有するとともに、ゲ
ート電極層に覆われていない第２の表面領域を備える。
このように、ゲート電極層に覆われていない第２の表面
領域を備えることにより、ゲート電極層とベース領域と
の対向面積は実質的に減少する。これにより、ゲート−
ソース間の寄生容量は低減され、スイッチング特性等が
高く、動作効率の高い絶縁ゲート型電界効果トランジス
タが提供される。In the above structure, the base region has a first surface region covered by the gate electrode layer and has a second surface region not covered by the gate electrode layer.
By providing the second surface region that is not covered with the gate electrode layer, the facing area between the gate electrode layer and the base region is substantially reduced. This allows the gate
A parasitic capacitance between sources is reduced, an insulated gate field effect transistor having high switching characteristics and the like and high operation efficiency is provided.
【００１８】前記第１の表面領域及び前記第２の表面領
域は、前記ベース領域の露出面に交互に配置されている
ことが好ましい。これにより、ゲート電圧の印加時に
は、ベース領域に等間隔にチャネルが形成される。従っ
て、バランスの良い電界が形成され、また、電流がバラ
ンス良く流れるので、高い信頼性が得られる。It is preferable that the first surface region and the second surface region are alternately arranged on an exposed surface of the base region. Thus, when a gate voltage is applied, channels are formed at equal intervals in the base region. Therefore, a well-balanced electric field is formed, and the current flows in a well-balanced manner, so that high reliability can be obtained.
【００１９】前記ベース領域は複数設けられ、前記ベー
ス領域の前記第１の表面領域は、隣接する他の前記ベー
ス領域の前記第２の表面領域と互いに対向するように配
置されていることが好ましい。これにより、バランスの
良い電界が形成され、また、電流がバランス良く流れる
ので、より高い信頼性が得られる。Preferably, a plurality of the base regions are provided, and the first surface region of the base region is arranged so as to be opposed to the second surface region of the adjacent base region. . Thereby, a well-balanced electric field is formed, and the current flows in a well-balanced manner, so that higher reliability can be obtained.
【００２０】上記構成において、前記ベース領域は、前
記ゲート電極層側から前記ドレイン領域に向かって延伸
する略円柱状に設けられていることが好ましい。In the above structure, it is preferable that the base region is provided in a substantially columnar shape extending from the gate electrode layer side toward the drain region.
【００２１】ゲート電極層と、ベース領域との対向面積
の減少は、オン抵抗の上昇につながるが、上記のよう
に、ベース領域を円柱状に形成することにより、オン抵
抗の上昇は補償される。A decrease in the area of the gate electrode layer facing the base region leads to an increase in the on-resistance. However, as described above, the increase in the on-resistance is compensated by forming the base region in a columnar shape. .
【００２２】[0022]
【発明の実施の形態】本発明の実施の形態にかかる絶縁
ゲート型電界効果トランジスタについて、以下図面を参
照して説明する。本実施の形態の絶縁ゲート型電界効果
トランジスタは、ＭＯＳ（Metal Oxide Semiconducto
r）型の電界効果トランジスタ（Field Effect Transist
or：ＦＥＴ）である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An insulated gate field effect transistor according to an embodiment of the present invention will be described below with reference to the drawings. The insulated gate field effect transistor of the present embodiment is a MOS (Metal Oxide Semiconductor).
r) Field Effect Transistor
or: FET).
【００２３】図１は、実施の形態の絶縁ゲート型電界効
果トランジスタ１１の断面構成図である。また、図２
は、その上面図であり、図１は、図２のＡ−Ａ’線矢視
断面を示す。FIG. 1 is a sectional view showing the configuration of an insulated gate field effect transistor 11 according to an embodiment. FIG.
1 is a top view, and FIG. 1 is a cross-sectional view taken along line AA ′ of FIG.
【００２４】図１に示す絶縁ゲート型電界効果トランジ
スタ１１は、ドレイン領域１２と、ドリフト領域１３
と、ベース領域１４と、ソース領域１５と、を備えたシ
リコン半導体基板１６から構成される。The insulated gate field effect transistor 11 shown in FIG.
, A base region 14 and a source region 15.
【００２５】ドレイン領域１２は、Ｎ形のシリコン半導
体基板として形成される。ドレイン領域１２は、シリコ
ン半導体基板１６の一面に露出しており、その表面上
（図１の下面側）には、アルミニウム等からなるドレイ
ン電極１７が設けられている。The drain region 12 is formed as an N-type silicon semiconductor substrate. The drain region 12 is exposed on one surface of the silicon semiconductor substrate 16, and a drain electrode 17 made of aluminum or the like is provided on the surface (the lower surface side in FIG. 1).
【００２６】ドリフト領域１３は、ドレイン領域１２の
上にＮ形のエピタキシャル成長層として形成されてい
る。ドリフト領域１３は、ドレイン領域１２よりも低い
不純物濃度で形成されている。ドリフト領域１３は、ド
レイン領域１２と同一導電型であり、ドレイン領域とし
ても機能する。The drift region 13 is formed on the drain region 12 as an N-type epitaxial growth layer. Drift region 13 is formed with a lower impurity concentration than drain region 12. Drift region 13 has the same conductivity type as drain region 12 and also functions as a drain region.
【００２７】ベース領域１４は、ドリフト領域１３に島
状に、その表面が露出するように設けられている。ベー
ス領域１４はＰ形の導電型に形成され、これを包囲する
Ｎ形のドリフト領域１３との界面でＰＮ接合を形成す
る。The base region 14 is provided in the drift region 13 in an island shape so that its surface is exposed. The base region 14 is formed of a P-type conductivity type, and forms a PN junction at an interface with the N-type drift region 13 surrounding the P-type conductivity region.
【００２８】ベース領域１４は、ドリフト領域１３内に
島状に設けられている。ベース領域１４は円形の断面を
有する柱状に形成されている。ベース領域１４は、ドリ
フト領域１３に複数設けられ、実質的に等間隔に設けら
れている。The base region 14 is provided in the drift region 13 in an island shape. The base region 14 is formed in a column shape having a circular cross section. A plurality of base regions 14 are provided in the drift region 13 and are provided at substantially equal intervals.
【００２９】ベース領域１４は柱状に設けられ、その底
部がドレイン領域１２近傍まで垂直に延伸するように形
成されている。ここで、ベース領域１４は、ドリフト領
域１３のエピタキシャル成長層に、以下のように形成さ
れる。The base region 14 is provided in a column shape, and is formed so that the bottom thereof extends vertically to the vicinity of the drain region 12. Here, the base region 14 is formed in the epitaxial growth layer of the drift region 13 as follows.
【００３０】まず、ドレイン領域１２の上に、薄いＮ形
半導体層（ドリフト領域１層分）をエピタキシャル成長
により形成し、この層にＰ形不純物を拡散してＰ形拡散
層（ベース領域１層分）を形成する。続いて、Ｎ形半導
体層の上にＮ形エピタキシャル成長層をさらに形成し、
下層のＰ形拡散層と重なるように、Ｐ形の不純物拡散を
行ってＰ形拡散層を形成する。このように、Ｎ形半導体
層の成長工程と、Ｐ形拡散層の拡散工程と、を繰り返す
ことにより、Ｎ形ドリフト領域１３と、これに包囲され
た柱状のＰ形ベース領域１４と、が形成される。上記成
長工程および拡散工程は、例えば、５回づつ繰り返され
る。First, a thin N-type semiconductor layer (for one drift region) is formed on the drain region 12 by epitaxial growth, and a P-type impurity is diffused into this layer to form a P-type diffusion layer (for one base region). ) Is formed. Subsequently, an N-type epitaxial growth layer is further formed on the N-type semiconductor layer,
P-type impurity diffusion is performed to overlap the lower P-type diffusion layer to form a P-type diffusion layer. As described above, by repeating the growth step of the N-type semiconductor layer and the diffusion step of the P-type diffusion layer, the N-type drift region 13 and the columnar P-type base region 14 surrounded by the N-type drift region 13 are formed. Is done. The growth step and the diffusion step are repeated, for example, five times.
【００３１】ベース領域１４の表面領域には、Ｎ＋型の
ソース領域１５が形成されている。ソース領域１５は、
ベース領域１４内に環状に設けられている。In the surface region of the base region 14, an N + type source region 15 is formed. The source region 15
It is provided annularly in the base region 14.
【００３２】図２に、図１に示す絶縁ゲート型電界効果
トランジスタ１１の上面図を示す。なお、理解を容易に
するため、図２中では、ベース領域１４、ソース領域１
５等が形成された半導体基板１６の表面と、その表面上
に設けられたゲート電極層１８のみを示す。FIG. 2 is a top view of the insulated gate field effect transistor 11 shown in FIG. In order to facilitate understanding, in FIG. 2, the base region 14, the source region 1
Only the surface of the semiconductor substrate 16 on which 5 and the like are formed and the gate electrode layer 18 provided on the surface are shown.
【００３３】図２に示すように、ベース領域１４は、ド
リフト領域１３にほぼ等間隔に、格子状に配置されてい
る。また、ベース領域１４の表面領域には、ソース領域
１５が環状に露出して設けられている。ベース領域１４
の表面領域は、環状のソース領域１５により、内周側の
円形の露出面１４ａと、外周側の環状の露出面１４ｂ
と、に分けられる。As shown in FIG. 2, the base regions 14 are arranged in the drift region 13 at substantially equal intervals in a lattice shape. In the surface region of the base region 14, a source region 15 is provided so as to be annularly exposed. Base area 14
Are formed by the annular source region 15 and a circular exposed surface 14a on the inner peripheral side and an annular exposed surface 14b on the outer peripheral side.
And, it is divided into.
【００３４】図１に戻り、ソース領域１５の外縁および
ベース領域１４の環状の露出面１４ｂ上方には、シリコ
ン酸化膜、シリコン窒化膜等からなる絶縁膜１９が設け
られている。言い換えると、絶縁膜１９は、ソース領域
１５に包囲されたベース領域１４の円形の露出面１４ａ
と、ソース領域１５の内縁を除いて、ベース領域１４の
環状の露出面１４ｂおよびドリフト領域１３の露出面を
覆うように形成されている。Returning to FIG. 1, an insulating film 19 made of a silicon oxide film, a silicon nitride film or the like is provided on the outer edge of the source region 15 and above the annular exposed surface 14b of the base region 14. In other words, the insulating film 19 is formed on the circular exposed surface 14 a of the base region 14 surrounded by the source region 15.
Except for the inner edge of the source region 15, it is formed so as to cover the annular exposed surface 14 b of the base region 14 and the exposed surface of the drift region 13.
【００３５】絶縁膜１９中には、ゲート電極１８層が埋
設されている。ゲート電極層１８は、不純物の導入され
たポリシリコン膜から構成されている。ゲート電極層１
８は、ソース領域１５の外縁およびソース領域１５の外
側に露出したベース領域１４の環状の露出面１４ｂを覆
うように設けられている。ゲート電極層１８の直下の環
状の露出面１４ｂは、絶縁膜１９をゲート絶縁膜とする
絶縁ゲート型ＦＥＴの、いわゆるチャネル領域（ｃｈ）
として機能する。A gate electrode 18 layer is buried in the insulating film 19. Gate electrode layer 18 is made of a polysilicon film into which impurities are introduced. Gate electrode layer 1
8 is provided so as to cover the outer edge of the source region 15 and the annular exposed surface 14b of the base region 14 exposed outside the source region 15. The annular exposed surface 14b immediately below the gate electrode layer 18 is a so-called channel region (ch) of an insulated gate FET using the insulating film 19 as a gate insulating film.
Function as
【００３６】図２を参照して、ゲート電極層１８は、半
導体基板１６のほぼ全面を覆うように設けられている。
ここで、ゲート電極層１８は孔２０を有する。ゲート電
極層１８の孔２０を介して、少なくとも、ベース領域１
４の円形の露出面１４ａと、ソース領域１５の内縁が露
出している。Referring to FIG. 2, gate electrode layer 18 is provided to cover substantially the entire surface of semiconductor substrate 16.
Here, the gate electrode layer 18 has a hole 20. Through the hole 20 of the gate electrode layer 18, at least the base region 1
4 and the inner edge of the source region 15 is exposed.
【００３７】図３に、孔２０の拡大図を示す。孔２０
は、中心の円形部２１と、３つの切り込み部２２と、か
ら構成されている。切り込み部２２は、円形部２１の外
側に切り込まれ、円形部２１よりも大きい半径を有する
扇状に形成されている。扇状の切り込み部２２は、円形
部２１と略同心を有し、円形部２１の周囲に実質的に等
間隔に３つ形成されている。切り込み部２２は、例え
ば、中心角が略６０°の扇形が、略１２０°毎に設けら
れて、形成されている。FIG. 3 shows an enlarged view of the hole 20. Hole 20
Is composed of a central circular portion 21 and three cut portions 22. The cut portion 22 is cut outside the circular portion 21 and is formed in a fan shape having a larger radius than the circular portion 21. The fan-shaped cut portions 22 are substantially concentric with the circular portion 21, and are formed at substantially equal intervals around the circular portion 21. The cut portion 22 is formed, for example, in such a manner that a sector having a central angle of approximately 60 ° is provided approximately every 120 °.
【００３８】図２に戻り、孔２０の円形部２１は、環状
のソース領域１５（およびベース領域１４の円形の露出
面１４ａ）と同心に形成され、ソース領域１５の外縁よ
りもわずかに小さい半径を有する。これにより、ゲート
電極層１８は、少なくとも、ベース領域１４の環状の露
出面１４ｂの一部に重なるように設けられている。Returning to FIG. 2, the circular portion 21 of the hole 20 is formed concentrically with the annular source region 15 (and the circular exposed surface 14a of the base region 14) and has a radius slightly smaller than the outer edge of the source region 15. Having. Thereby, the gate electrode layer 18 is provided so as to overlap at least a part of the annular exposed surface 14 b of the base region 14.
【００３９】しかし、ベース領域１４の環状の露出面１
４ｂのうち、切り込み部２２の下にの領域はゲート電極
層１８により覆われず、切り込み部２２を介して露出し
ている。このように、切り込み部２２があることによ
り、ベース領域１４の環状の露出面１４ｂは、ゲート電
極層１８と、は間欠的に（不連続に）対向している。However, the annular exposed surface 1 of the base region 14
4b, the region below the cutout 22 is not covered by the gate electrode layer 18 and is exposed through the cutout 22. As described above, due to the presence of the cut portion 22, the annular exposed surface 14b of the base region 14 intermittently (discontinuously) faces the gate electrode layer 18.
【００４０】図４は、図２とは異なり、ゲート電極層１
８を除いて、ドリフト領域１３、ベース領域１４および
ソース領域１５の表面露出領域を示した図である。な
お、点線にて、孔２０を示す。FIG. 4 is different from FIG. 2 in that the gate electrode layer 1
FIG. 8 is a diagram showing the surface exposed regions of the drift region 13, the base region 14, and the source region 15 excluding 8. In addition, the hole 20 is shown by a dotted line.
【００４１】図４に示すように、ベース領域１４の環状
の露出面１４ｂは、ゲート電極層１８に覆われた第１の
表面領域１４ｂａと、覆われていない第２の表面領域１
４ｂｂと、に分けられる。孔２０の形状に従い、第１の
表面領域１４ｂａと第２の表面領域１４ｂｂとは、交互
に、等間隔に配置されている。このように、ベース領域
１４が、ゲート電極層１８に覆われていない第２の表面
領域１４ｂｂを有することにより、ゲート電極層１８と
ベース領域１４との対向面積は実質的に減少する。As shown in FIG. 4, the annular exposed surface 14b of the base region 14 has a first surface region 14ba covered by the gate electrode layer 18 and a second surface region 1ba that is not covered.
4bb. According to the shape of the hole 20, the first surface regions 14ba and the second surface regions 14bb are alternately arranged at equal intervals. Since the base region 14 has the second surface region 14bb that is not covered with the gate electrode layer 18, the facing area between the gate electrode layer 18 and the base region 14 is substantially reduced.
【００４２】ゲート電極層１８にゲート電圧が印加され
た際には、切り込み部２２の直下の、ゲート電極層１８
に覆われたベース領域１４の第１の表面領域１４ｂａ
が、チャネル領域として機能する。従って、ゲート電極
層１８に覆われていない第２の表面領域１４ｂｂ分の対
向面積の減少は、チャネル領域の実質的な減少をもたら
す。When a gate voltage is applied to the gate electrode layer 18, the gate electrode layer 18 immediately below the cut portion 22 is formed.
Surface region 14ba of base region 14 covered with
Function as a channel region. Therefore, the decrease in the facing area of the second surface region 14bb not covered with the gate electrode layer 18 results in a substantial decrease in the channel region.
【００４３】図１を参照して、ゲート電極層１８を内包
する絶縁膜１９は、ゲート電極層１８の孔２０に対応す
る孔１９ａを有する。絶縁膜１９の孔１９ａは、ソース
領域１５と同心を有してより小径に設けられている。絶
縁膜１９の孔１９ａを介して、ソース領域１５の内縁、
および、その内側のベース領域１４の円形の露出面１４
ａが露出している。Referring to FIG. 1, insulating film 19 enclosing gate electrode layer 18 has holes 19a corresponding to holes 20 in gate electrode layer 18. The hole 19 a of the insulating film 19 is provided concentrically with the source region 15 and has a smaller diameter. The inner edge of the source region 15 through the hole 19a of the insulating film 19;
And a circular exposed surface 14 of the inner base region 14
a is exposed.
【００４４】ここで、絶縁膜１９の孔１９ａには、ゲー
ト電極層１８の孔２０の切り込み部２２に相当するもの
は形成されていない。従って、切り込み部２２の下のベ
ース領域１４は、ゲート電極層１８には覆われていない
が、絶縁膜１９には覆われている。Here, in the hole 19 a of the insulating film 19, the one corresponding to the cut portion 22 of the hole 20 of the gate electrode layer 18 is not formed. Therefore, the base region 14 below the cut portion 22 is not covered with the gate electrode layer 18 but is covered with the insulating film 19.
【００４５】半導体基板１６の上面には、ソース電極層
２３が設けられている。ソース電極層２３は、絶縁膜１
９の孔１９ａを介して、ソース領域１５の内縁と、ソー
ス領域１５の内側のベース領域１４と、に接触してい
る。ソース電極層２３はソース領域１５と接触し、絶縁
ゲート型電界効果トランジスタ１１のソース電極として
機能する。The source electrode layer 23 is provided on the upper surface of the semiconductor substrate 16. The source electrode layer 23 is formed of the insulating film 1
Nine holes 19a are in contact with the inner edge of the source region 15 and the base region 14 inside the source region 15. The source electrode layer 23 contacts the source region 15 and functions as a source electrode of the insulated gate field effect transistor 11.
【００４６】上記のようにドレイン電極１７、ゲート電
極層１８およびソース電極層２３を備える絶縁ゲート型
電界効果トランジスタ１１において、ソース−ドレイン
間に逆バイアスが印加されると、ベース領域１４とドリ
フト領域１３との間のＰＮ接合から空乏層が形成され
る。複数の柱状のベース領域１４の形成する空乏層は、
ドリフト領域１３のドレイン領域１２側に至る全体を覆
うように一体化する。これにより、高い耐圧が得られ
る。In the insulated gate field effect transistor 11 having the drain electrode 17, the gate electrode layer 18, and the source electrode layer 23 as described above, when a reverse bias is applied between the source and the drain, the base region 14 and the drift region 13, a depletion layer is formed from the PN junction. The depletion layer formed by the plurality of columnar base regions 14 is
The drift region 13 is integrated so as to cover the entire region extending to the drain region 12 side. Thereby, a high withstand voltage can be obtained.
【００４７】ここで、上記のような孔２０を有するゲー
ト電極層１８を備える構成では、ベース領域１４の環状
の露出面１４ｂは、ゲート電極層１８と間欠的に（不連
続に）対向する。これにより、ベース領域１４の環状の
露出面１４ｂには、ゲート電極層１８に覆われない第２
の表面領域１４ｂｂが形成され、ゲート電極層１８とベ
ース領域１４との対向面積は、実質的に低減される。従
って、ベース領域１４と、絶縁膜１９を挟んでこれに対
向するゲート電極層１８と、の間に誘起する寄生容量
は、切り込み部２２を有しない場合と比べ、小さいもの
となる。Here, in the configuration including the gate electrode layer 18 having the hole 20 as described above, the annular exposed surface 14b of the base region 14 intermittently (discontinuously) faces the gate electrode layer 18. As a result, the ring-shaped exposed surface 14b of the base region 14 has a second surface which is not covered with the gate electrode layer 18.
Is formed, and the facing area between gate electrode layer 18 and base region 14 is substantially reduced. Therefore, the parasitic capacitance induced between the base region 14 and the gate electrode layer 18 opposed thereto with the insulating film 19 interposed therebetween is smaller than that in the case where the cutout portion 22 is not provided.
【００４８】ゲート−ソース間容量を含む入力容量が大
きい場合、絶縁ゲート型ＦＥＴの特性、特に、スイッチ
ング特性は劣化する。しかし、上記のように、ゲート電
極層１８とベース領域１４との対向面積を低減させた構
成では、ゲート−ソース間の容量は低いものとなり、高
速なスイッチング動作の可能な、動作効率の高い絶縁ゲ
ート型ＦＥＴが得られる。When the input capacitance including the gate-source capacitance is large, the characteristics of the insulated gate FET, particularly the switching characteristics, deteriorate. However, as described above, in the configuration in which the opposing area between the gate electrode layer 18 and the base region 14 is reduced, the capacitance between the gate and the source is low, and a high-speed switching operation and high operating efficiency can be achieved. A gate type FET is obtained.
【００４９】一方で、ゲート電極層１８に切り込み部２
２を形成した構成では、ベース領域１４の環状の露出面
１４ｂのうち、ゲート電極層１８と対向する領域（チャ
ネル流域）は実質的に減少する。チャネル領域の減少は
動作抵抗（オン抵抗）の増大をもたらす。しかしなが
ら、柱状のベース領域１４を備える絶縁ゲート型電界効
果トランジスタ１１においては、ドリフト領域１３の不
純物濃度を高くしても高い耐圧が得られる。従って、チ
ャネル領域の減少による動作抵抗の上昇分は、ドリフト
領域１３の不純物濃度を上昇させることにより補償可能
である。従って、切り込み部２２によりチャネル領域が
実質的に減少した構成においても、高い耐圧および高い
動作効率を高水準に維持可能である。On the other hand, the cut portion 2 is formed in the gate electrode layer 18.
In the configuration in which No. 2 is formed, a region (channel flow region) of the annular exposed surface 14b of the base region 14 facing the gate electrode layer 18 is substantially reduced. The reduction in the channel region results in an increase in the operating resistance (ON resistance). However, in the insulated gate field effect transistor 11 including the columnar base region 14, a high breakdown voltage can be obtained even if the impurity concentration of the drift region 13 is increased. Therefore, the increase in the operating resistance due to the decrease in the channel region can be compensated by increasing the impurity concentration of the drift region 13. Therefore, even in a configuration in which the channel region is substantially reduced by the cutout portion 22, high breakdown voltage and high operation efficiency can be maintained at a high level.
【００５０】以上説明したように、ベース領域１４とゲ
ート電極層１８との対向面積を実質的に減少させた本発
明によれば、ゲート−ソース間に誘起される寄生容量は
低減される。これにより、動作時に絶縁ゲート型電界効
果トランジスタ１１に誘起する入力容量は低減され、ス
イッチング特性等の優れた、高い動作特性が得られる。As described above, according to the present invention in which the facing area between the base region 14 and the gate electrode layer 18 is substantially reduced, the parasitic capacitance induced between the gate and the source is reduced. As a result, the input capacitance induced in the insulated gate field effect transistor 11 during operation is reduced, and high operating characteristics such as excellent switching characteristics are obtained.
【００５１】また、ベース領域１４とゲート電極層１８
との対向面積の減少に伴うチャネル領域の実質的な減少
は、ドリフト領域１３の不純物濃度の上昇により補償可
能である。ドリフト領域１３の動作抵抗が低い場合で
も、柱状のベース領域１４を備える絶縁ゲート型電界効
果トランジスタ１１は、高い耐圧特性を維持可能であ
る。The base region 14 and the gate electrode layer 18
The substantial decrease in the channel region due to the decrease in the area facing the semiconductor device can be compensated for by increasing the impurity concentration of the drift region 13. Even when the operating resistance of the drift region 13 is low, the insulated gate field effect transistor 11 including the columnar base region 14 can maintain high withstand voltage characteristics.
【００５２】本発明は、上記実施の形態に限られず、種
々の変形、応用が可能である。以下、本発明に適用可能
な上記実施の形態の変形態様について、説明する。The present invention is not limited to the above embodiment, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.
【００５３】上記実施の形態では、本発明をベース領域
１４が柱状の絶縁ゲート型ＦＥＴに適用した構成とし
た。しかし、柱状のベース領域を有しない構造の絶縁ゲ
ート型ＦＥＴに適用することもできる。また、絶縁ゲー
ト型バイポーラトランジスタ等に適用してもよい。ただ
し、上記実施の形態で示したように、柱状のベース領域
を有する絶縁ゲート型ＦＥＴに適用した場合には、ドリ
フト領域の不純物濃度を比較的高く設定してオン抵抗を
小さくすることができる。In the above embodiment, the present invention is applied to an insulated gate FET in which the base region 14 has a columnar shape. However, the present invention can also be applied to an insulated gate FET having a structure having no columnar base region. Further, the present invention may be applied to an insulated gate bipolar transistor or the like. However, as described in the above embodiment, when applied to an insulated gate FET having a columnar base region, the on-resistance can be reduced by setting the impurity concentration of the drift region relatively high.
【００５４】上記実施の形態では、ゲート電極層１８の
孔２０は、３つの切り込み部２２を有するものとした。
しかし、切り込み部２２の数はこれに限らず、２つ以
下、あるいは、４つ以上であってもよい。また、切り込
み部２２の形状も扇状に限らず、方形、多角形等、ベー
ス領域１４と絶縁膜１９との対向面積を減少可能な構成
であればいかなる形状も可能である。逆に、孔２０の形
状に対応して、ベース領域１４の第１の表面領域１４ｂ
ａおよび第２の表面領域１４ｂｂも、等間隔に限らず、
どのように配置してもよい。In the above embodiment, the hole 20 in the gate electrode layer 18 has three cuts 22.
However, the number of cut portions 22 is not limited to this, and may be two or less, or four or more. Also, the shape of the cutout portion 22 is not limited to a fan shape, and any shape such as a square or a polygon can be used as long as the facing area between the base region 14 and the insulating film 19 can be reduced. Conversely, the first surface region 14b of the base region 14 corresponds to the shape of the hole 20.
a and the second surface region 14bb are not limited to equal intervals,
Any arrangement is possible.
【００５５】上記実施の形態では、円柱状のベース領域
１４を、ドリフト領域１３に島状に設ける構成とした。
しかし、これに限らず、ベース領域１４を四角柱等の多
角柱形状として、島状に設ける構成としてもよい。ま
た、ベース領域１４をストライプ形状や格子形状に形成
してもよい。この場合、ゲート電極層１８の孔２０をベ
ース領域１４の形状に合わせて形成すればよい。In the above embodiment, the columnar base region 14 is provided in the drift region 13 in an island shape.
However, the present invention is not limited to this, and the base region 14 may be formed in a polygonal pillar shape such as a square pillar and provided in an island shape. Further, the base region 14 may be formed in a stripe shape or a lattice shape. In this case, the hole 20 of the gate electrode layer 18 may be formed according to the shape of the base region 14.
【００５６】上記実施の形態では、ベース領域１４は、
ドリフト領域１３に格子状に配置されるものとした。し
かし、ベース領域１４の配置はこれに限られず、例え
ば、図５に示すようにしてもよい。図５において、ベー
ス領域１４は、隣接するもの同士の第１の表面領域１４
ｂａと、第２の表面領域１４ｂｂとが、互いに対向する
ように配置されている。この構成によれば、ゲート電圧
の印加時には、バランスのよい電界が形成され、また、
電流がバランス良く流れる。従って、さらなる信頼性の
向上が図れる。In the above embodiment, the base region 14
It is arranged in the drift region 13 in a lattice pattern. However, the arrangement of the base region 14 is not limited to this, and may be, for example, as shown in FIG. In FIG. 5, the base region 14 is a first surface region 14 between adjacent ones.
The ba and the second surface region 14bb are arranged so as to face each other. According to this configuration, when a gate voltage is applied, a well-balanced electric field is formed.
The current flows in a well-balanced manner. Therefore, the reliability can be further improved.
【００５７】上記実施の形態では、絶縁膜１９は実質的
に均一の厚さとした。しかし、これに限らず、例えば、
ドリフト領域１３上の絶縁膜１９を選択的に厚く形成し
てもよい。このように、ドリフト領域１３上の絶縁膜１
９を厚く形成することにより、ゲート−ドレイン間容量
を低減することができる。これにより、入力容量のさら
なる低減を図ることができ、動作効率の向上が図れる。In the above embodiment, the insulating film 19 has a substantially uniform thickness. However, not limited to this, for example,
The insulating film 19 on the drift region 13 may be selectively formed thick. Thus, the insulating film 1 on the drift region 13
By forming 9 thick, the capacitance between the gate and the drain can be reduced. As a result, the input capacitance can be further reduced, and the operation efficiency can be improved.
【００５８】[0058]
【発明の効果】以上説明したように、本発明によれば、
動作効率の高い絶縁ゲート型電界効果トランジスタが提
供される。As described above, according to the present invention,
An insulated gate field effect transistor with high operation efficiency is provided.
【図１】本発明の実施の形態にかかる絶縁ゲート型電界
効果トランジスタの断面構成図である。FIG. 1 is a sectional configuration diagram of an insulated gate field effect transistor according to an embodiment of the present invention.
【図２】本発明の実施の形態にかかる絶縁ゲート型電界
効果トランジスタの上面図である。FIG. 2 is a top view of the insulated gate field effect transistor according to the embodiment of the present invention.
【図３】孔の構成を示す図である。FIG. 3 is a diagram showing a configuration of a hole.
【図４】本発明の実施の形態にかかる絶縁ゲート型電界
効果トランジスタの上面図である。FIG. 4 is a top view of the insulated gate field effect transistor according to the embodiment of the present invention.
【図５】本発明の他の実施の形態を示す図である。FIG. 5 is a diagram showing another embodiment of the present invention.
１１ 絶縁ゲート型電界効果トランジスタ １２ ドレイン領域 １３ ドリフト領域 １４ ベース領域 １５ ソース領域 １６ 半導体基板 １７ ドレイン電極 １８ ゲート電極層 １９ 絶縁膜 １９ａ 孔 ２０ 孔 ２１ 円形部 ２２ 切り込み部 ２３ ソース電極層 Reference Signs List 11 insulated gate field effect transistor 12 drain region 13 drift region 14 base region 15 source region 16 semiconductor substrate 17 drain electrode 18 gate electrode layer 19 insulating film 19a hole 20 hole 21 circular portion 22 cut portion 23 source electrode layer
Claims (10)
レイン領域と、 前記ドレイン領域上に設けられ、前記ドレイン領域より
も不純物濃度の低い第１導電型のドリフト領域と、 前記ドリフト領域内に島状に設けられた第２導電型のベ
ース領域と、 前記ベース領域内に島状に設けられ、前記ドリフト領域
よりも不純物濃度の高い第１導電型のソース領域と、 前記ドリフト領域と前記ソース領域とに挟まれた前記ベ
ース領域の露出面を、間欠的に覆うように設けられたゲ
ート電極層と、 を備えることを特徴とする絶縁ゲート型電界効果トラン
ジスタ。A first conductive type drain region provided on a semiconductor substrate; a first conductive type drift region provided on the drain region and having a lower impurity concentration than the drain region; A second conductivity type base region provided in an island shape therein; a first conductivity type source region provided in the base region in an island shape having a higher impurity concentration than the drift region; A gate electrode layer intermittently covering an exposed surface of the base region sandwiched between the source region and the base region.
孔を有する、ことを特徴する請求項１に記載の絶縁ゲー
ト型電界効果トランジスタ。2. The insulated gate field effect transistor according to claim 1, wherein the gate electrode layer has a hole overlapping the exposed surface.
前記環状の露出面の内径と略同径を有する円形の第１の
領域と、前記円形の第１の領域から外側に切り込まれた
第２の領域と、を備え、前記第２の領域は前記環状の露
出面の一部と重なる、ことを特徴とする請求項２に記載
の絶縁ゲート型電界効果トランジスタ。3. The exposed surface is formed in an annular shape, and the hole is
A circular first region having substantially the same diameter as the inner diameter of the annular exposed surface; and a second region cut out from the circular first region, wherein the second region is 3. The insulated gate field effect transistor according to claim 2, wherein the insulated gate field effect transistor overlaps a part of the annular exposed surface.
よりも大径の扇状に設けられている、ことを特徴とする
請求項３に記載の絶縁ゲート型電界効果トランジスタ。4. The insulated gate field effect transistor according to claim 3, wherein said second region is provided in a fan shape having a diameter larger than an outer diameter of said annular exposed surface.
に略等間隔に複数設けられている、ことを特徴とする請
求項３または４に記載の絶縁ゲート型電界効果トランジ
スタ。5. The insulated gate field effect transistor according to claim 3, wherein a plurality of said second regions are provided at substantially equal intervals around said first region.
に３つ設けられている、ことを特徴とする請求項３乃至
５のいずれか１項に記載の絶縁ゲート型電界効果トラン
ジスタ。6. The insulated gate field effect according to claim 3, wherein three second regions are provided around the first region. Transistor.
レイン領域と、 前記ドレイン領域上に設けられ、前記ドレイン領域より
も不純物濃度の低い第１導電型のドリフト領域と、 前記ドリフト領域内に島状に設けられた第２導電型のベ
ース領域と、 前記ベース領域内に島状に設けられ、前記ドリフト領域
よりも不純物濃度の高い第１導電型のソース領域と、 前記ドリフト領域と前記ソース領域とに挟まれた前記ベ
ース領域の露出面を、絶縁膜を介して覆うように設けら
れたゲート電極層と、を備え、 前記ベース領域の露出面は、前記ゲート電極層に覆われ
た第１の表面領域と、前記ゲート電極層に覆われていな
い第２の表面領域と、を備える、ことを特徴とする絶縁
ゲート型電界効果トランジスタ。7. A drain region of a first conductivity type provided on a semiconductor substrate, a drift region of a first conductivity type provided on the drain region and having a lower impurity concentration than the drain region, and the drift region A second conductivity type base region provided in an island shape therein; a first conductivity type source region provided in the base region in an island shape having a higher impurity concentration than the drift region; A gate electrode layer provided so as to cover an exposed surface of the base region sandwiched between the source region and an insulating film. An exposed surface of the base region is covered with the gate electrode layer. An insulated gate field effect transistor, comprising: a first surface region; and a second surface region not covered by the gate electrode layer.
域は、前記ベース領域の露出面に交互に配置されてい
る、ことを特徴とする請求項７に記載の絶縁ゲート型電
界効果トランジスタ。8. The insulated gate field effect according to claim 7, wherein said first surface region and said second surface region are alternately arranged on an exposed surface of said base region. Transistor.
ス領域の前記第１の表面領域は、隣接する他の前記ベー
ス領域の前記第２の表面領域と互いに対向するように配
置されている、ことを特徴とする請求項７または８に記
載の絶縁ゲート型電界効果トランジスタ。9. A plurality of the base regions are provided, and the first surface region of the base region is arranged so as to face the second surface region of another adjacent base region. 9. The insulated gate field effect transistor according to claim 7, wherein:
から前記ドレイン領域に向かって延伸する略円柱状に設
けられている、ことを特徴とする請求項１乃至９のいず
れか１項に記載の絶縁ゲート型電界効果トランジスタ。10. The device according to claim 1, wherein the base region is provided in a substantially columnar shape extending from the gate electrode layer side toward the drain region. Insulated gate field effect transistor.
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|---|---|---|---|
| JP2001179249A JP3620472B2 (en) | 2001-06-13 | 2001-06-13 | Insulated gate field effect transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001179249A JP3620472B2 (en) | 2001-06-13 | 2001-06-13 | Insulated gate field effect transistor |
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|---|---|---|---|---|
| US8125005B2 (en) | 2006-05-18 | 2012-02-28 | Panasonic Corporation | Semiconductor element and method for manufacturing same |
| CN110957351A (en) * | 2019-12-17 | 2020-04-03 | 华羿微电子股份有限公司 | Super-junction MOSFET device and preparation method thereof |
-
2001
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8125005B2 (en) | 2006-05-18 | 2012-02-28 | Panasonic Corporation | Semiconductor element and method for manufacturing same |
| CN110957351A (en) * | 2019-12-17 | 2020-04-03 | 华羿微电子股份有限公司 | Super-junction MOSFET device and preparation method thereof |
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