JP3620472B2 - Insulated gate field effect transistor - Google Patents

Insulated gate field effect transistor Download PDF

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JP3620472B2
JP3620472B2 JP2001179249A JP2001179249A JP3620472B2 JP 3620472 B2 JP3620472 B2 JP 3620472B2 JP 2001179249 A JP2001179249 A JP 2001179249A JP 2001179249 A JP2001179249 A JP 2001179249A JP 3620472 B2 JP3620472 B2 JP 3620472B2
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base region
electrode layer
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gate electrode
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JP2002373987A (en
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良治 高橋
正行 花岡
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Sanken Electric Co Ltd
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、動作効率の高い絶縁ゲート型電界効果トランジスタに関する。
【０００２】
【従来の技術】
産業用パワースイッチ等に用いられるパワーデバイスとして、絶縁ゲート型電界効果トランジスタ（Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ：ＦＥＴ）等が使用されている。このような絶縁ゲート型ＦＥＴは、一般に高電圧下で使用され、高耐圧特性が要求されるとともに、高速のスイッチング速度が要求される。
【０００３】
絶縁ゲート型ＦＥＴは、例えば、Ｎ形のドリフト領域と、Ｎ＋型のドレイン領域と、Ｐ形の複数のベース領域と、Ｎ＋型の複数のソース領域と、を備える半導体基板と、ドレイン領域に接続するドレイン電極と、ソース領域に接続するソース電極と、ドリフト領域とソース領域との間のベース領域（チャネル領域）の上方に絶縁膜を介して設けられたゲート電極と、を備える。
【０００４】
高い耐圧特性を得るため、ベース領域を柱状に形成した絶縁ゲート型ＦＥＴが開発されている。この絶縁ゲート型ＦＥＴは、ベース領域が、ドリフト領域中をドレイン電極側に柱状に延伸し、その底面がドレイン領域とドリフト領域との界面近くにまで達した構造を有する。
【０００５】
上記した柱状のベース領域を複数備える絶縁ゲート型ＦＥＴでは、ベース領域とドリフト領域との間に形成されるＰＮ接合に逆バイアスが印加されたときには、ＰＮ接合により形成される空乏層が、ベース領域間のドリフト領域全体に拡がる。これにより、電界の集中は緩和され、高い耐圧が得られる。また、高耐圧が得られることにより、ドリフト領域の不純物濃度を高く設定して低抵抗とすることができる。
【０００６】
例えば、柱状のベース領域でなく、浅いベース領域を用いた場合と比べ、ドリフト領域の比抵抗を１／３〜１／５に設定しても、浅いベース領域を用いた構造と同等の耐圧が得られる。
【０００７】
【発明が解決しようとする課題】
上記絶縁ゲート型ＦＥＴの動作時には、ゲート−ドレイン間およびゲート−ソース間に必然的に入力容量が発生する。ゲート−ドレイン間容量およびゲート−ソース間容量が過大である場合には、スイッチング速度が低下するなどの不具合が起こる。
【０００８】
入力容量のうち、ゲート−ドレイン間容量を低減させるため、ドリフト領域の上面のゲート酸化膜のうち、チャネル領域上の酸化膜を選択的に厚く形成する方法が知られている。しかしながら、ゲート−ドレイン間容量に関しては、これを低減する効果的な方法は未だ開発されていない。このように、従来の絶縁ゲート型ＦＥＴは、十分に入力容量が低減された、高い動作効率を有するものではなかった。
【０００９】
上記事情を鑑みて、本発明は、動作効率の高い絶縁ゲート型電界効果トランジスタを提供することを目的とする。
また、本発明は、入力容量の低減された絶縁ゲート型電界効果トランジスタを提供することを目的とする。
【００１７】
上記構成において、ベース領域は、ゲート電極層に覆われた第１の表面領域を有するとともに、ゲート電極層に覆われていない第２の表面領域を備える。このように、ゲート電極層に覆われていない第２の表面領域を備えることにより、ゲート電極層とベース領域との対向面積は実質的に減少する。これにより、ゲート−ソース間の寄生容量は低減され、スイッチング特性等が高く、動作効率の高い絶縁ゲート型電界効果トランジスタが提供される。
【００１８】
前記第１の表面領域及び前記第２の表面領域は、前記ベース領域の露出面に交互に配置されていることが好ましい。これにより、ゲート電圧の印加時には、ベース領域に等間隔にチャネルが形成される。従って、バランスの良い電界が形成され、また、電流がバランス良く流れるので、高い信頼性が得られる。
【００１９】
前記ベース領域は複数設けられ、前記ベース領域の前記第１の表面領域は、隣接する他の前記ベース領域の前記第２の表面領域と互いに対向するように配置されていることが好ましい。これにより、バランスの良い電界が形成され、また、電流がバランス良く流れるので、より高い信頼性が得られる。
【００２０】
【課題を解決するための手段】
上記目的を達成するため、本発明の絶縁ゲート型電界効果トランジスタは、
半導体基板内に設けられた第１導電型のドレイン領域と、
前記ドレイン領域上に設けられ、前記ドレイン領域よりも不純物濃度の低い第１導電型のドリフト領域と、
前記ドリフト領域内に島状に設けられた第２導電型のベース領域と、
前記ベース領域内に島状に設けられ、前記ドリフト領域よりも不純物濃度の高い第１導電型のソース領域と、
前記ドリフト領域と前記ソース領域とに挟まれた前記ベース領域の露出面を、絶縁膜を介して覆うように設けられたゲート電極層と、を備え、
前記ベース領域の露出面は、前記ゲート電極層に覆われた第１の表面領域と、前記ゲート電極層に覆われていない第２の表面領域と、を備え、
前記ベース領域は、前記ゲート電極層側から前記ドレイン領域に向かって該ドレイン領域近傍まで垂直に延伸するように柱状に設けられている、ことを特徴とする。
上記構成において、前記第１の表面領域及び前記第２の表面領域は、前記ベース領域の露出面に交互に配置されていることが好ましい。
また、上記構成において、前記ベース領域は複数設けられ、前記ベース領域の前記第１の表面領域は、隣接する他の前記ベース領域の前記第２の表面領域と互いに対向するように配置されていることが好ましい。
【００２１】
ゲート電極層と、ベース領域との対向面積の減少は、オン抵抗の上昇につながるが、上記のように、ベース領域を円柱状に形成することにより、オン抵抗の上昇は補償される。
【００２２】
【発明の実施の形態】
本発明の実施の形態にかかる絶縁ゲート型電界効果トランジスタについて、以下図面を参照して説明する。本実施の形態の絶縁ゲート型電界効果トランジスタは、ＭＯＳ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）型の電界効果トランジスタ（Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ：ＦＥＴ）である。
【００２３】
図１は、実施の形態の絶縁ゲート型電界効果トランジスタ１１の断面構成図である。また、図２は、その上面図であり、図１は、図２のＡ−Ａ’線矢視断面を示す。
【００２４】
図１に示す絶縁ゲート型電界効果トランジスタ１１は、ドレイン領域１２と、ドリフト領域１３と、ベース領域１４と、ソース領域１５と、を備えたシリコン半導体基板１６から構成される。
【００２５】
ドレイン領域１２は、Ｎ形のシリコン半導体基板として形成される。ドレイン領域１２は、シリコン半導体基板１６の一面に露出しており、その表面上（図１の下面側）には、アルミニウム等からなるドレイン電極１７が設けられている。
【００２６】
ドリフト領域１３は、ドレイン領域１２の上にＮ形のエピタキシャル成長層として形成されている。ドリフト領域１３は、ドレイン領域１２よりも低い不純物濃度で形成されている。ドリフト領域１３は、ドレイン領域１２と同一導電型であり、ドレイン領域としても機能する。
【００２７】
ベース領域１４は、ドリフト領域１３に島状に、その表面が露出するように設けられている。ベース領域１４はＰ形の導電型に形成され、これを包囲するＮ形のドリフト領域１３との界面でＰＮ接合を形成する。
【００２８】
ベース領域１４は、ドリフト領域１３内に島状に設けられている。ベース領域１４は円形の断面を有する柱状に形成されている。ベース領域１４は、ドリフト領域１３に複数設けられ、実質的に等間隔に設けられている。
【００２９】
ベース領域１４は柱状に設けられ、その底部がドレイン領域１２近傍まで垂直に延伸するように形成されている。ここで、ベース領域１４は、ドリフト領域１３のエピタキシャル成長層に、以下のように形成される。
【００３０】
まず、ドレイン領域１２の上に、薄いＮ形半導体層（ドリフト領域１層分）をエピタキシャル成長により形成し、この層にＰ形不純物を拡散してＰ形拡散層（ベース領域１層分）を形成する。続いて、Ｎ形半導体層の上にＮ形エピタキシャル成長層をさらに形成し、下層のＰ形拡散層と重なるように、Ｐ形の不純物拡散を行ってＰ形拡散層を形成する。このように、Ｎ形半導体層の成長工程と、Ｐ形拡散層の拡散工程と、を繰り返すことにより、Ｎ形ドリフト領域１３と、これに包囲された柱状のＰ形ベース領域１４と、が形成される。上記成長工程および拡散工程は、例えば、５回づつ繰り返される。
【００３１】
ベース領域１４の表面領域には、Ｎ＋型のソース領域１５が形成されている。ソース領域１５は、ベース領域１４内に環状に設けられている。
【００３２】
図２に、図１に示す絶縁ゲート型電界効果トランジスタ１１の上面図を示す。なお、理解を容易にするため、図２中では、ベース領域１４、ソース領域１５等が形成された半導体基板１６の表面と、その表面上に設けられたゲート電極層１８のみを示す。
【００３３】
図２に示すように、ベース領域１４は、ドリフト領域１３にほぼ等間隔に、格子状に配置されている。また、ベース領域１４の表面領域には、ソース領域１５が環状に露出して設けられている。ベース領域１４の表面領域は、環状のソース領域１５により、内周側の円形の露出面１４ａと、外周側の環状の露出面１４ｂと、に分けられる。
【００３４】
図１に戻り、ソース領域１５の外縁およびベース領域１４の環状の露出面１４ｂ上方には、シリコン酸化膜、シリコン窒化膜等からなる絶縁膜１９が設けられている。言い換えると、絶縁膜１９は、ソース領域１５に包囲されたベース領域１４の円形の露出面１４ａと、ソース領域１５の内縁を除いて、ベース領域１４の環状の露出面１４ｂおよびドリフト領域１３の露出面を覆うように形成されている。
【００３５】
絶縁膜１９中には、ゲート電極１８層が埋設されている。ゲート電極層１８は、不純物の導入されたポリシリコン膜から構成されている。ゲート電極層１８は、ソース領域１５の外縁およびソース領域１５の外側に露出したベース領域１４の環状の露出面１４ｂを覆うように設けられている。ゲート電極層１８の直下の環状の露出面１４ｂは、絶縁膜１９をゲート絶縁膜とする絶縁ゲート型ＦＥＴの、いわゆるチャネル領域（ｃｈ）として機能する。
【００３６】
図２を参照して、ゲート電極層１８は、半導体基板１６のほぼ全面を覆うように設けられている。ここで、ゲート電極層１８は孔２０を有する。ゲート電極層１８の孔２０を介して、少なくとも、ベース領域１４の円形の露出面１４ａと、ソース領域１５の内縁が露出している。
【００３７】
図３に、孔２０の拡大図を示す。孔２０は、中心の円形部２１と、３つの切り込み部２２と、から構成されている。切り込み部２２は、円形部２１の外側に切り込まれ、円形部２１よりも大きい半径を有する扇状に形成されている。扇状の切り込み部２２は、円形部２１と略同心を有し、円形部２１の周囲に実質的に等間隔に３つ形成されている。切り込み部２２は、例えば、中心角が略６０°の扇形が、略１２０°毎に設けられて、形成されている。
【００３８】
図２に戻り、孔２０の円形部２１は、環状のソース領域１５（およびベース領域１４の円形の露出面１４ａ）と同心に形成され、ソース領域１５の外縁よりもわずかに小さい半径を有する。これにより、ゲート電極層１８は、少なくとも、ベース領域１４の環状の露出面１４ｂの一部に重なるように設けられている。
【００３９】
しかし、ベース領域１４の環状の露出面１４ｂのうち、切り込み部２２の下にの領域はゲート電極層１８により覆われず、切り込み部２２を介して露出している。このように、切り込み部２２があることにより、ベース領域１４の環状の露出面１４ｂは、ゲート電極層１８と、は間欠的に（不連続に）対向している。
【００４０】
図４は、図２とは異なり、ゲート電極層１８を除いて、ドリフト領域１３、ベース領域１４およびソース領域１５の表面露出領域を示した図である。なお、点線にて、孔２０を示す。
【００４１】
図４に示すように、ベース領域１４の環状の露出面１４ｂは、ゲート電極層１８に覆われた第１の表面領域１４ｂａと、覆われていない第２の表面領域１４ｂｂと、に分けられる。孔２０の形状に従い、第１の表面領域１４ｂａと第２の表面領域１４ｂｂとは、交互に、等間隔に配置されている。このように、ベース領域１４が、ゲート電極層１８に覆われていない第２の表面領域１４ｂｂを有することにより、ゲート電極層１８とベース領域１４との対向面積は実質的に減少する。
【００４２】
ゲート電極層１８にゲート電圧が印加された際には、切り込み部２２の直下の、ゲート電極層１８に覆われたベース領域１４の第１の表面領域１４ｂａが、チャネル領域として機能する。従って、ゲート電極層１８に覆われていない第２の表面領域１４ｂｂ分の対向面積の減少は、チャネル領域の実質的な減少をもたらす。
【００４３】
図１を参照して、ゲート電極層１８を内包する絶縁膜１９は、ゲート電極層１８の孔２０に対応する孔１９ａを有する。絶縁膜１９の孔１９ａは、ソース領域１５と同心を有してより小径に設けられている。絶縁膜１９の孔１９ａを介して、ソース領域１５の内縁、および、その内側のベース領域１４の円形の露出面１４ａが露出している。
【００４４】
ここで、絶縁膜１９の孔１９ａには、ゲート電極層１８の孔２０の切り込み部２２に相当するものは形成されていない。従って、切り込み部２２の下のベース領域１４は、ゲート電極層１８には覆われていないが、絶縁膜１９には覆われている。
【００４５】
半導体基板１６の上面には、ソース電極層２３が設けられている。ソース電極層２３は、絶縁膜１９の孔１９ａを介して、ソース領域１５の内縁と、ソース領域１５の内側のベース領域１４と、に接触している。ソース電極層２３はソース領域１５と接触し、絶縁ゲート型電界効果トランジスタ１１のソース電極として機能する。
【００４６】
上記のようにドレイン電極１７、ゲート電極層１８およびソース電極層２３を備える絶縁ゲート型電界効果トランジスタ１１において、ソース−ドレイン間に逆バイアスが印加されると、ベース領域１４とドリフト領域１３との間のＰＮ接合から空乏層が形成される。複数の柱状のベース領域１４の形成する空乏層は、ドリフト領域１３のドレイン領域１２側に至る全体を覆うように一体化する。これにより、高い耐圧が得られる。
【００４７】
ここで、上記のような孔２０を有するゲート電極層１８を備える構成では、ベース領域１４の環状の露出面１４ｂは、ゲート電極層１８と間欠的に（不連続に）対向する。これにより、ベース領域１４の環状の露出面１４ｂには、ゲート電極層１８に覆われない第２の表面領域１４ｂｂが形成され、ゲート電極層１８とベース領域１４との対向面積は、実質的に低減される。従って、ベース領域１４と、絶縁膜１９を挟んでこれに対向するゲート電極層１８と、の間に誘起する寄生容量は、切り込み部２２を有しない場合と比べ、小さいものとなる。
【００４８】
ゲート−ソース間容量を含む入力容量が大きい場合、絶縁ゲート型ＦＥＴの特性、特に、スイッチング特性は劣化する。しかし、上記のように、ゲート電極層１８とベース領域１４との対向面積を低減させた構成では、ゲート−ソース間の容量は低いものとなり、高速なスイッチング動作の可能な、動作効率の高い絶縁ゲート型ＦＥＴが得られる。
【００４９】
一方で、ゲート電極層１８に切り込み部２２を形成した構成では、ベース領域１４の環状の露出面１４ｂのうち、ゲート電極層１８と対向する領域（チャネル流域）は実質的に減少する。チャネル領域の減少は動作抵抗（オン抵抗）の増大をもたらす。しかしながら、柱状のベース領域１４を備える絶縁ゲート型電界効果トランジスタ１１においては、ドリフト領域１３の不純物濃度を高くしても高い耐圧が得られる。従って、チャネル領域の減少による動作抵抗の上昇分は、ドリフト領域１３の不純物濃度を上昇させることにより補償可能である。従って、切り込み部２２によりチャネル領域が実質的に減少した構成においても、高い耐圧および高い動作効率を高水準に維持可能である。
【００５０】
以上説明したように、ベース領域１４とゲート電極層１８との対向面積を実質的に減少させた本発明によれば、ゲート−ソース間に誘起される寄生容量は低減される。これにより、動作時に絶縁ゲート型電界効果トランジスタ１１に誘起する入力容量は低減され、スイッチング特性等の優れた、高い動作特性が得られる。
【００５１】
また、ベース領域１４とゲート電極層１８との対向面積の減少に伴うチャネル領域の実質的な減少は、ドリフト領域１３の不純物濃度の上昇により補償可能である。ドリフト領域１３の動作抵抗が低い場合でも、柱状のベース領域１４を備える絶縁ゲート型電界効果トランジスタ１１は、高い耐圧特性を維持可能である。
【００５２】
本発明は、上記実施の形態に限られず、種々の変形、応用が可能である。以下、本発明に適用可能な上記実施の形態の変形態様について、説明する。
【００５３】
上記実施の形態では、本発明をベース領域１４が柱状の絶縁ゲート型ＦＥＴに適用した構成とした。しかし、柱状のベース領域を有しない構造の絶縁ゲート型ＦＥＴに適用することもできる。また、絶縁ゲート型バイポーラトランジスタ等に適用してもよい。ただし、上記実施の形態で示したように、柱状のベース領域を有する絶縁ゲート型ＦＥＴに適用した場合には、ドリフト領域の不純物濃度を比較的高く設定してオン抵抗を小さくすることができる。
【００５４】
上記実施の形態では、ゲート電極層１８の孔２０は、３つの切り込み部２２を有するものとした。しかし、切り込み部２２の数はこれに限らず、２つ以下、あるいは、４つ以上であってもよい。また、切り込み部２２の形状も扇状に限らず、方形、多角形等、ベース領域１４と絶縁膜１９との対向面積を減少可能な構成であればいかなる形状も可能である。逆に、孔２０の形状に対応して、ベース領域１４の第１の表面領域１４ｂａおよび第２の表面領域１４ｂｂも、等間隔に限らず、どのように配置してもよい。
【００５５】
上記実施の形態では、円柱状のベース領域１４を、ドリフト領域１３に島状に設ける構成とした。しかし、これに限らず、ベース領域１４を四角柱等の多角柱形状として、島状に設ける構成としてもよい。また、ベース領域１４をストライプ形状や格子形状に形成してもよい。この場合、ゲート電極層１８の孔２０をベース領域１４の形状に合わせて形成すればよい。
【００５６】
上記実施の形態では、ベース領域１４は、ドリフト領域１３に格子状に配置されるものとした。しかし、ベース領域１４の配置はこれに限られず、例えば、図５に示すようにしてもよい。図５において、ベース領域１４は、隣接するもの同士の第１の表面領域１４ｂａと、第２の表面領域１４ｂｂとが、互いに対向するように配置されている。この構成によれば、ゲート電圧の印加時には、バランスのよい電界が形成され、また、電流がバランス良く流れる。従って、さらなる信頼性の向上が図れる。
【００５７】
上記実施の形態では、絶縁膜１９は実質的に均一の厚さとした。しかし、これに限らず、例えば、ドリフト領域１３上の絶縁膜１９を選択的に厚く形成してもよい。このように、ドリフト領域１３上の絶縁膜１９を厚く形成することにより、ゲート−ドレイン間容量を低減することができる。これにより、入力容量のさらなる低減を図ることができ、動作効率の向上が図れる。
【００５８】
【発明の効果】
以上説明したように、本発明によれば、動作効率の高い絶縁ゲート型電界効果トランジスタが提供される。
【図面の簡単な説明】
【図１】本発明の実施の形態にかかる絶縁ゲート型電界効果トランジスタの断面構成図である。
【図２】本発明の実施の形態にかかる絶縁ゲート型電界効果トランジスタの上面図である。
【図３】孔の構成を示す図である。
【図４】本発明の実施の形態にかかる絶縁ゲート型電界効果トランジスタの上面図である。
【図５】本発明の他の実施の形態を示す図である。
【符号の説明】
１１ 絶縁ゲート型電界効果トランジスタ
１２ ドレイン領域
１３ ドリフト領域
１４ ベース領域
１５ ソース領域
１６ 半導体基板
１７ ドレイン電極
１８ ゲート電極層
１９ 絶縁膜
１９ａ 孔
２０ 孔
２１ 円形部
２２ 切り込み部
２３ ソース電極層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate field effect transistor having high operating efficiency.
[0002]
[Prior art]
As a power device used for an industrial power switch or the like, an insulated gate field effect transistor (Field Effect Transistor: FET) or the like is used. Such an insulated gate FET is generally used under a high voltage, requires a high breakdown voltage characteristic, and requires a high switching speed.
[0003]
The insulated gate FET includes, for example, a semiconductor substrate including an N type drift region, an N + type drain region, a plurality of P type base regions, and a plurality of N + type source regions, and a drain region. A drain electrode connected to the source region, a source electrode connected to the source region, and a gate electrode provided above the base region (channel region) between the drift region and the source region via an insulating film.
[0004]
In order to obtain high breakdown voltage characteristics, an insulated gate FET having a base region formed in a columnar shape has been developed. This insulated gate FET has a structure in which the base region extends in a columnar shape in the drift region toward the drain electrode, and the bottom surface thereof reaches near the interface between the drain region and the drift region.
[0005]
In the insulated gate FET having a plurality of the columnar base regions described above, when a reverse bias is applied to the PN junction formed between the base region and the drift region, the depletion layer formed by the PN junction becomes the base region. It extends to the entire drift region. Thereby, the concentration of the electric field is relaxed and a high breakdown voltage is obtained. Further, since a high breakdown voltage can be obtained, the impurity concentration in the drift region can be set high to reduce the resistance.
[0006]
For example, as compared with the case where a shallow base region is used instead of a columnar base region, even if the specific resistance of the drift region is set to 1/3 to 1/5, the breakdown voltage equivalent to the structure using the shallow base region can be obtained. can get.
[0007]
[Problems to be solved by the invention]
During the operation of the insulated gate FET, input capacitance is inevitably generated between the gate and the drain and between the gate and the source. When the gate-drain capacitance and the gate-source capacitance are excessive, problems such as a decrease in switching speed occur.
[0008]
In order to reduce the gate-drain capacitance of the input capacitance, a method of selectively forming an oxide film on the channel region out of the gate oxide film on the upper surface of the drift region is known. However, an effective method for reducing the gate-drain capacitance has not been developed yet. As described above, the conventional insulated gate FET does not have high operating efficiency with sufficiently reduced input capacitance.
[0009]
In view of the above circumstances, an object of the present invention is to provide an insulated gate field effect transistor with high operating efficiency.
Another object of the present invention is to provide an insulated gate field effect transistor with reduced input capacitance.
[0017]
In the above configuration, the base region has a first surface region covered with the gate electrode layer and a second surface region not covered with the gate electrode layer. Thus, by providing the second surface region that is not covered with the gate electrode layer, the facing area between the gate electrode layer and the base region is substantially reduced. Thereby, the parasitic capacitance between the gate and the source is reduced, an insulating gate type field effect transistor having high switching characteristics and high operation efficiency is provided.
[0018]
It is preferable that the first surface region and the second surface region are alternately arranged on the exposed surface of the base region. Thereby, when a gate voltage is applied, channels are formed at equal intervals in the base region. Therefore, a well-balanced electric field is formed, and the current flows in a well-balanced manner, so that high reliability can be obtained.
[0019]
Preferably, a plurality of the base regions are provided, and the first surface region of the base region is disposed so as to face the second surface region of another adjacent base region. Thereby, a well-balanced electric field is formed, and the current flows in a well-balanced manner, so that higher reliability can be obtained.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, an insulated gate field effect transistor of the present invention comprises:
A drain region of a first conductivity type provided in the semiconductor substrate;
A drift region of a first conductivity type provided on the drain region and having an impurity concentration lower than that of the drain region;
A base region of a second conductivity type provided in an island shape in the drift region;
A source region of a first conductivity type provided in an island shape in the base region and having a higher impurity concentration than the drift region;
A gate electrode layer provided so as to cover an exposed surface of the base region sandwiched between the drift region and the source region via an insulating film;
The exposed surface of the base region includes a first surface region covered with the gate electrode layer, and a second surface region not covered with the gate electrode layer,
The base region is provided in a column shape so as to extend vertically from the gate electrode layer side toward the drain region to the vicinity of the drain region .
The said structure WHEREIN: It is preferable that the said 1st surface area and the said 2nd surface area are alternately arrange | positioned at the exposed surface of the said base area | region.
Further, in the above configuration, a plurality of the base regions are provided, and the first surface region of the base region is disposed so as to face the second surface region of another adjacent base region. It is preferable.
[0021]
Although the decrease in the facing area between the gate electrode layer and the base region leads to an increase in on-resistance, as described above, the increase in on-resistance is compensated by forming the base region in a cylindrical shape.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
An insulated gate field effect transistor according to an embodiment of the present invention will be described below with reference to the drawings. The insulated gate field effect transistor of the present embodiment is a MOS (Metal Oxide Semiconductor) type field effect transistor (FET).
[0023]
FIG. 1 is a cross-sectional configuration diagram of an insulated gate field effect transistor 11 according to an embodiment. FIG. 2 is a top view thereof, and FIG. 1 shows a cross section taken along line AA ′ of FIG.
[0024]
The insulated gate field effect transistor 11 shown in FIG. 1 includes a silicon semiconductor substrate 16 that includes a drain region 12, a drift region 13, a base region 14, and a source region 15.
[0025]
The drain region 12 is formed as an N-type silicon semiconductor substrate. The drain region 12 is exposed on one surface of the silicon semiconductor substrate 16, and a drain electrode 17 made of aluminum or the like is provided on the surface (the lower surface side in FIG. 1).
[0026]
The drift region 13 is formed as an N-type epitaxial growth layer on the drain region 12. The drift region 13 is formed with a lower impurity concentration than the drain region 12. The drift region 13 has the same conductivity type as the drain region 12 and also functions as a drain region.
[0027]
The base region 14 is provided in an island shape in the drift region 13 so that the surface thereof is exposed. The base region 14 is formed in a P-type conductivity type, and forms a PN junction at the interface with the N-type drift region 13 surrounding the base region 14.
[0028]
The base region 14 is provided in an island shape in the drift region 13. The base region 14 is formed in a column shape having a circular cross section. A plurality of base regions 14 are provided in the drift region 13 and are provided at substantially equal intervals.
[0029]
The base region 14 is provided in a columnar shape, and is formed so that the bottom thereof extends vertically to the vicinity of the drain region 12. Here, the base region 14 is formed in the epitaxial growth layer of the drift region 13 as follows.
[0030]
First, a thin N-type semiconductor layer (for one drift region) is formed on the drain region 12 by epitaxial growth, and P-type impurities are diffused into this layer to form a P-type diffusion layer (for one base region). To do. Subsequently, an N-type epitaxial growth layer is further formed on the N-type semiconductor layer, and a P-type diffusion layer is formed by performing P-type impurity diffusion so as to overlap with the lower P-type diffusion layer. As described above, the N-type drift region 13 and the columnar P-type base region 14 surrounded by the N-type semiconductor layer are formed by repeating the N-type semiconductor layer growth step and the P-type diffusion layer diffusion step. Is done. The growth process and the diffusion process are repeated, for example, 5 times.
[0031]
An N + type source region 15 is formed in the surface region of the base region 14. The source region 15 is annularly provided in the base region 14.
[0032]
FIG. 2 is a top view of the insulated gate field effect transistor 11 shown in FIG. For ease of understanding, FIG. 2 shows only the surface of the semiconductor substrate 16 on which the base region 14, the source region 15 and the like are formed, and the gate electrode layer 18 provided on the surface.
[0033]
As shown in FIG. 2, the base regions 14 are arranged in a lattice pattern at substantially equal intervals in the drift region 13. In addition, a source region 15 is provided in a ring shape on the surface region of the base region 14. The surface region of the base region 14 is divided by the annular source region 15 into a circular exposed surface 14a on the inner peripheral side and an annular exposed surface 14b on the outer peripheral side.
[0034]
Returning to FIG. 1, an insulating film 19 made of a silicon oxide film, a silicon nitride film, or the like is provided on the outer edge of the source region 15 and above the annular exposed surface 14 b of the base region 14. In other words, the insulating film 19 is exposed to the circular exposed surface 14 a of the base region 14 surrounded by the source region 15 and the annular exposed surface 14 b of the base region 14 and the drift region 13 except for the inner edge of the source region 15. It is formed so as to cover the surface.
[0035]
A gate electrode 18 layer is buried in the insulating film 19. The gate electrode layer 18 is composed of a polysilicon film into which impurities are introduced. The gate electrode layer 18 is provided so as to cover the outer edge of the source region 15 and the annular exposed surface 14 b of the base region 14 exposed to the outside of the source region 15. The annular exposed surface 14b immediately below the gate electrode layer 18 functions as a so-called channel region (ch) of an insulated gate FET having the insulating film 19 as a gate insulating film.
[0036]
Referring to FIG. 2, gate electrode layer 18 is provided so as to cover almost the entire surface of semiconductor substrate 16. Here, the gate electrode layer 18 has a hole 20. At least the circular exposed surface 14 a of the base region 14 and the inner edge of the source region 15 are exposed through the hole 20 of the gate electrode layer 18.
[0037]
FIG. 3 shows an enlarged view of the hole 20. The hole 20 includes a central circular portion 21 and three cut portions 22. The cut portion 22 is cut out outside the circular portion 21 and is formed in a fan shape having a larger radius than the circular portion 21. The fan-shaped cut portions 22 are substantially concentric with the circular portion 21, and three fan-shaped cut portions 22 are formed at substantially equal intervals around the circular portion 21. The cut portion 22 is formed, for example, by providing a sector shape with a central angle of about 60 ° at every about 120 °.
[0038]
Returning to FIG. 2, the circular portion 21 of the hole 20 is formed concentrically with the annular source region 15 (and the circular exposed surface 14 a of the base region 14), and has a slightly smaller radius than the outer edge of the source region 15. Thereby, the gate electrode layer 18 is provided so as to overlap at least a part of the annular exposed surface 14 b of the base region 14.
[0039]
However, of the annular exposed surface 14 b of the base region 14, the region below the cut portion 22 is not covered by the gate electrode layer 18 and is exposed through the cut portion 22. As described above, due to the notch 22, the annular exposed surface 14 b of the base region 14 faces the gate electrode layer 18 intermittently (discontinuously).
[0040]
FIG. 4 is a diagram showing the surface exposed regions of the drift region 13, the base region 14, and the source region 15 except for the gate electrode layer 18, unlike FIG. 2. In addition, the hole 20 is shown with a dotted line.
[0041]
As shown in FIG. 4, the annular exposed surface 14b of the base region 14 is divided into a first surface region 14ba covered with the gate electrode layer 18 and a second surface region 14bb not covered. According to the shape of the hole 20, the first surface region 14ba and the second surface region 14bb are alternately arranged at equal intervals. Thus, since the base region 14 has the second surface region 14bb that is not covered with the gate electrode layer 18, the facing area between the gate electrode layer 18 and the base region 14 is substantially reduced.
[0042]
When a gate voltage is applied to the gate electrode layer 18, the first surface region 14ba of the base region 14 covered with the gate electrode layer 18 immediately below the notch 22 functions as a channel region. Therefore, the reduction in the facing area corresponding to the second surface region 14bb that is not covered by the gate electrode layer 18 results in a substantial reduction in the channel region.
[0043]
With reference to FIG. 1, the insulating film 19 including the gate electrode layer 18 has a hole 19 a corresponding to the hole 20 of the gate electrode layer 18. The hole 19 a of the insulating film 19 is concentric with the source region 15 and has a smaller diameter. Through the hole 19a of the insulating film 19, the inner edge of the source region 15 and the circular exposed surface 14a of the base region 14 inside the source region 15 are exposed.
[0044]
Here, in the hole 19 a of the insulating film 19, a portion corresponding to the cut portion 22 of the hole 20 of the gate electrode layer 18 is not formed. Accordingly, the base region 14 under the notch 22 is not covered with the gate electrode layer 18 but is covered with the insulating film 19.
[0045]
A source electrode layer 23 is provided on the upper surface of the semiconductor substrate 16. The source electrode layer 23 is in contact with the inner edge of the source region 15 and the base region 14 inside the source region 15 through the hole 19 a of the insulating film 19. The source electrode layer 23 is in contact with the source region 15 and functions as a source electrode of the insulated gate field effect transistor 11.
[0046]
In the insulated gate field effect transistor 11 including the drain electrode 17, the gate electrode layer 18, and the source electrode layer 23 as described above, when a reverse bias is applied between the source and the drain, the base region 14 and the drift region 13 A depletion layer is formed from the PN junction. The depletion layers formed by the plurality of columnar base regions 14 are integrated so as to cover the whole of the drift region 13 reaching the drain region 12 side. Thereby, a high breakdown voltage is obtained.
[0047]
Here, in the configuration including the gate electrode layer 18 having the hole 20 as described above, the annular exposed surface 14 b of the base region 14 faces the gate electrode layer 18 intermittently (discontinuously). As a result, a second surface region 14bb that is not covered by the gate electrode layer 18 is formed on the annular exposed surface 14b of the base region 14, and the opposing area between the gate electrode layer 18 and the base region 14 is substantially equal. Reduced. Therefore, the parasitic capacitance induced between the base region 14 and the gate electrode layer 18 opposed to the insulating film 19 is smaller than that in the case where the notch portion 22 is not provided.
[0048]
When the input capacitance including the gate-source capacitance is large, the characteristics of the insulated gate FET, in particular, the switching characteristics are deteriorated. However, in the configuration in which the facing area between the gate electrode layer 18 and the base region 14 is reduced as described above, the gate-source capacitance is low, and high-speed switching operation is possible and insulation with high operating efficiency is possible. A gate type FET is obtained.
[0049]
On the other hand, in the configuration in which the cut portion 22 is formed in the gate electrode layer 18, the region (channel flow region) facing the gate electrode layer 18 in the annular exposed surface 14 b of the base region 14 is substantially reduced. A decrease in the channel region results in an increase in operating resistance (ON resistance). However, in the insulated gate field effect transistor 11 including the columnar base region 14, a high breakdown voltage can be obtained even if the impurity concentration of the drift region 13 is increased. Therefore, the increase in operating resistance due to the decrease in the channel region can be compensated by increasing the impurity concentration in the drift region 13. Therefore, even in a configuration in which the channel region is substantially reduced by the cut portion 22, high breakdown voltage and high operating efficiency can be maintained at a high level.
[0050]
As described above, according to the present invention in which the facing area between the base region 14 and the gate electrode layer 18 is substantially reduced, the parasitic capacitance induced between the gate and the source is reduced. As a result, the input capacitance induced in the insulated gate field effect transistor 11 during operation is reduced, and high operating characteristics such as excellent switching characteristics can be obtained.
[0051]
A substantial decrease in the channel region accompanying a decrease in the facing area between the base region 14 and the gate electrode layer 18 can be compensated by an increase in the impurity concentration of the drift region 13. Even when the operating resistance of the drift region 13 is low, the insulated gate field effect transistor 11 including the columnar base region 14 can maintain high breakdown voltage characteristics.
[0052]
The present invention is not limited to the above embodiment, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.
[0053]
In the above embodiment, the present invention is applied to an insulated gate FET having a base region 14 having a columnar shape. However, the present invention can also be applied to an insulated gate FET having a structure having no columnar base region. Moreover, you may apply to an insulated gate bipolar transistor etc. However, as shown in the above embodiment, when applied to an insulated gate FET having a columnar base region, the on-resistance can be reduced by setting the impurity concentration in the drift region to be relatively high.
[0054]
In the above embodiment, the hole 20 of the gate electrode layer 18 has the three cut portions 22. However, the number of notches 22 is not limited to this, and may be two or less, or four or more. In addition, the shape of the cut portion 22 is not limited to a fan shape, and may be any shape as long as the opposing area between the base region 14 and the insulating film 19 can be reduced, such as a square or a polygon. Conversely, the first surface region 14ba and the second surface region 14bb of the base region 14 may be arranged in any manner corresponding to the shape of the hole 20 without being limited to the equal interval.
[0055]
In the above embodiment, the cylindrical base region 14 is provided in the drift region 13 in an island shape. However, the present invention is not limited to this, and the base region 14 may be formed in an island shape as a polygonal column shape such as a quadrangular column. Further, the base region 14 may be formed in a stripe shape or a lattice shape. In this case, the hole 20 of the gate electrode layer 18 may be formed in accordance with the shape of the base region 14.
[0056]
In the above embodiment, the base region 14 is arranged in the drift region 13 in a lattice pattern. However, the arrangement of the base region 14 is not limited to this, and may be as shown in FIG. In FIG. 5, the base region 14 is arranged so that the first surface region 14ba and the second surface region 14bb of adjacent ones face each other. According to this configuration, when a gate voltage is applied, a well-balanced electric field is formed, and current flows in a well-balanced manner. Therefore, the reliability can be further improved.
[0057]
In the above embodiment, the insulating film 19 has a substantially uniform thickness. However, the present invention is not limited to this. For example, the insulating film 19 on the drift region 13 may be selectively formed thick. Thus, the gate-drain capacitance can be reduced by forming the insulating film 19 on the drift region 13 thick. Thereby, the input capacity can be further reduced, and the operation efficiency can be improved.
[0058]
【The invention's effect】
As described above, according to the present invention, an insulated gate field effect transistor with high operating efficiency is provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional configuration diagram of an insulated gate field effect transistor according to an embodiment of the present invention.
FIG. 2 is a top view of an insulated gate field effect transistor according to an embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of holes.
FIG. 4 is a top view of an insulated gate field effect transistor according to an embodiment of the present invention.
FIG. 5 is a diagram showing another embodiment of the present invention.
[Explanation of symbols]
11 Insulated gate type field effect transistor 12 Drain region 13 Drift region 14 Base region 15 Source region 16 Semiconductor substrate 17 Drain electrode 18 Gate electrode layer 19 Insulating film 19a Hole 20 Hole 21 Circular portion 22 Cut portion 23 Source electrode layer

Claims (3)

半導体基板内に設けられた第１導電型のドレイン領域と、
前記ドレイン領域上に設けられ、前記ドレイン領域よりも不純物濃度の低い第１導電型のドリフト領域と、
前記ドリフト領域内に島状に設けられた第２導電型のベース領域と、
前記ベース領域内に島状に設けられ、前記ドリフト領域よりも不純物濃度の高い第１導電型のソース領域と、
前記ドリフト領域と前記ソース領域とに挟まれた前記ベース領域の露出面を、絶縁膜を介して覆うように設けられたゲート電極層と、を備え、
前記ベース領域の露出面は、前記ゲート電極層に覆われた第１の表面領域と、前記ゲート電極層に覆われていない第２の表面領域と、を備え、
前記ベース領域は、前記ゲート電極層側から前記ドレイン領域に向かって該ドレイン領域近傍まで垂直に延伸するように柱状に設けられている、ことを特徴とする絶縁ゲート型電界効果トランジスタ。A drain region of a first conductivity type provided in the semiconductor substrate;
A drift region of a first conductivity type provided on the drain region and having an impurity concentration lower than that of the drain region;
A base region of a second conductivity type provided in an island shape in the drift region;
A source region of a first conductivity type provided in an island shape in the base region and having a higher impurity concentration than the drift region;
A gate electrode layer provided so as to cover an exposed surface of the base region sandwiched between the drift region and the source region via an insulating film;
The exposed surface of the base region includes a first surface region covered with the gate electrode layer, and a second surface region not covered with the gate electrode layer,
The insulated gate field effect transistor, wherein the base region is provided in a columnar shape so as to extend vertically from the gate electrode layer side toward the drain region to the vicinity of the drain region . 前記第１の表面領域及び前記第２の表面領域は、前記ベース領域の露出面に交互に配置されている、ことを特徴とする請求項１に記載の絶縁ゲート型電界効果トランジスタ。The insulated gate field effect transistor according to claim 1, wherein the first surface region and the second surface region are alternately arranged on an exposed surface of the base region. 前記ベース領域は複数設けられ、前記ベース領域の前記第１の表面領域は、隣接する他の前記ベース領域の前記第２の表面領域と互いに対向するように配置されている、ことを特徴とする請求項１または２に記載の絶縁ゲート型電界効果トランジスタ。A plurality of the base regions are provided, and the first surface region of the base region is disposed so as to face the second surface region of another adjacent base region. The insulated gate field effect transistor according to claim 1 or 2.
JP2001179249A 2001-06-13 2001-06-13 Insulated gate field effect transistor Expired - Fee Related JP3620472B2 (en)

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