JP3497716B2 - Horizontal insulated gate bipolar transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral insulated gate bipolar transistor, and more particularly to a device structure that affects current paths of electrons and holes.

[0002]

2. Description of the Related Art FIG. 16 shows a conventional lateral MOS gate bipolar transistor (hereinafter, IGBT (Insulated Gate).
Bipolar Transistor). ) Is a view showing a sectional structure of FIG.

Generally, in the lateral IGBT, taking an n-channel type as an example, an n-type epitaxial layer 53 which is a low concentration impurity diffusion layer formed on a silicon (Si) single crystal substrate.
It is formed in the 0 main surface area. As shown in FIG.
A p-type base region 550, which is a p-type impurity diffusion layer, is formed in the main surface region of the p-type epitaxial layer 530, and a high-concentration n-type impurity diffusion region is formed in a part of the surface region of the p-type base region 550. N-type emitter region 5 which is a layer
60 is formed.

A gate oxide film 600 and a gate electrode 540 are formed on a part of the exposed surface of n-type emitter region 560, a part of the exposed surface of n-type epitaxial layer 530 and the exposed surface of p-type base region 550 therebetween. Has been done. p-type base region 550 and n-type emitter region 56
Each of 0s is electrically connected to the emitter electrode E. The gate electrode G connected to the gate electrode 540 has a certain level or more (threshold voltage Vth or more) with respect to the emitter.
By applying a positive voltage of n, an electron-induced n-type inversion layer, that is, an electron channel is formed under the gate electrode 540. As described above, the gate electrode 540 and the surrounding structure close to the gate electrode 540 have MOSFETs (Metal Oxide Semiconductor).
It has the same configuration as the Field Effect Transistor).

On the other hand, p is formed in the main surface region of the n-type epitaxial layer 530 which is separated from the p-type base region 550 by a certain distance.
A p-type collector region 510 which is a type impurity diffusion layer is formed. The p-type collector region 510 is electrically connected to the collector electrode C. This p-type collector region 51
Paying attention to the structures of 0, the n-type epitaxial layer 530, and the p-type base region 550, these form a pnp-type bipolar transistor.

FIG. 17 (a) shows an example of an equivalent circuit of a general IGBT. As shown in the circuit diagram, the equivalent circuit of the IGBT can be represented as a composite circuit of a pnp bipolar transistor and a MOSFET. The source terminal of the MOSFET is connected to the collector terminal of the pnp transistor, and the drain terminal of the MOSFET is connected to the base terminal of the pnp transistor.
That is, in the IGBT, it can be understood that the base current of the pnp transistor is controlled by the MOSFET.

FIG. 18A is a plan view of a conventional IGBT. Only the gate electrode 540 and the p-type collector region 510 are shown in the drawing. The IG shown in FIG. 16 described above.
A cross-sectional view of BT is a dashed-dotted line A0 shown in FIG.
Corresponds to the cross section at -A'0.

As shown in FIG. 18 (a), a conventional IGB is used.
T is a strip-shaped collector region 510 having round upper and lower ends,
It has a gate electrode 540 that surrounds the periphery thereof in a ring shape with a constant interval.

FIG. 18 (b) is an enlarged view of a part of the plan view shown in FIG. 18 (a). This corresponds to a plan view near the one-dot chain line A0-A'0. A strip-shaped p-type collector region 510 is shown on the right side of FIG. p-type collector region 510
And a band-shaped gate electrode 540 provided at a constant interval
In the lower layer, a p-type base region 550 and an n-type emitter region 560 are formed so as to partially overlap each other. A broken line 550a parallel to the band-shaped gate electrode 540 and a broken line 56
0a indicates the boundary between the p-type base region 550 and the n-type emitter region 560, respectively.

As described above, in the conventional general IGBT, the collector region 510 and the gate electrode 54 are locally provided.
0, p-type base region 550, and n-type emitter region 5
Each of 60 can be represented by a strip-shaped region, and can be seen as being arranged in parallel with each other.

[0011]

First, the conventional IGBT is used.
The first problem in will be described.

In the plan view shown in FIG. 18B, IG
A solid line 590 indicates a current path of holes that are the first carriers and a solid line 580 indicates a current path of electrons that are the second carrier when the BT operates.

In reality, the current path of each carrier is formed in a plane shape rather than a linear shape. For example, the electron current path is
A direction perpendicular to the longitudinal direction of the gate electrode 540, where n
It is formed in a direction from the type emitter region 560 toward the p-type collector region. The current path of the holes is formed in the direction perpendicular to the longitudinal direction of the gate electrode 540 and in the direction from the p-type collector region 510 to the n-type emitter region 560. That is, the current paths of electrons and holes overlap in the vertical direction, and the traveling directions of the carriers are opposite to each other.

Referring again to FIG. 16, the electron and hole current paths during operation of the IGBT are observed in a cross-sectional view of the device. As shown in FIG. 16, in the lateral IGBT, current paths of electrons and holes are mainly formed in a shallow portion of the device main surface region.

When a constant voltage is applied to the gate electrode 540, M
The OSFET is turned on, and an inversion layer is formed on the surface of the p-type base region 550 directly below the gate electrode 540. n
The electrons (e), which are the majority carriers in the type emitter region 560, enter the n-type epitaxial layer 530 through the channel that is the inversion layer, and further enter the surface region of the n-type epitaxial layer 530, as shown by the solid line 580. It passes through and reaches the p-type collector region 510.

On the other hand, the holes (h) injected from the p-type collector region 510 into the n-type epitaxial layer 530 pass through the surface region of the n-type epitaxial layer 530 and then reach the p-type base region as shown by the solid line 590. Enter 550,
Reach the emitter electrode E. However, as shown in FIG.
Since a channel for electrons and an n-type emitter region 560 are formed in the surface layer of the p-type base region 550 on the right side of the figure close to the type collector region 510, holes are below this channel and the n-type emitter region 560. There is no choice but to take a current path that passes through the gate and reaches the emitter electrode E.

At this time, paying attention to the structures of the n-type emitter region 560, the p-type base region 550, and the n-type epitaxial layer 530, these are parasitic npn bipolar transistors (hereinafter referred to as parasitic npn transistors).
Are configured.

In FIG. 16, the p-type base region 550 through which the holes pass has a constant specific resistance value according to the concentration of p-type impurities and the like. When a hole passes through the p-type base region 550 for a certain distance, a resistance R proportional to the passing distance is generated. Therefore, a voltage drop (Vt) obtained by adding a current value depending on the resistance R and the amount of carriers is applied between the base and emitter terminals of the parasitic npn transistor. The longer the passage distance of the holes in the p-type base region 550, the more the resistance R and the value of the voltage drop (Vt).

The circuit shown in FIG. 17B has the parasitic n
It shows an equivalent circuit of an IGBT including a pn bipolar transistor. A transistor surrounded by a broken line in the figure corresponds to a parasitic npn transistor. This parasitic np
The emitter terminal of the n-transistor is connected to the source terminal of the MOSFET, and the base terminal of the parasitic npn transistor is connected to the collector terminal of the pnp transistor. The collector terminal of the parasitic npn transistor is MO
It is connected to both the drain terminal of the SFET and the base terminal of the pnp transistor.

When the voltage drop (Vt) due to the resistance R generated in the p-type base region 550 exceeds a certain voltage, the parasitic npn transistor surrounded by the broken line is turned on and p
The base current of the np transistor flows through the parasitic npn transistor. Therefore, regardless of the gate potential of the MOSFET, a state in which the current continues to flow in the IGBT,
This is the so-called "latch-up" state. When this happens M
The current control of the pnp transistor using the OSFET cannot be performed, and the element may be destroyed.

Although the n-channel type IGBT has been described above as an example, the above-mentioned n-type is also applied to the case of the p-channel type IGBT.
Although the conductivity types of the respective regions of the channel type IGBT are all opposite to each other and the bias relationship is reversed, latch-up similarly occurs.

In view of the above problems of the conventional IGBT, the first object of the present invention is to provide a lateral IGBT having a novel structure capable of suppressing the occurrence of latch-up as described above.
Is to provide.

Next, the second problem in the conventional IGBT will be described.

When the IGBT is used as a power switching element of a motor or the like, it is desired that the saturation voltage Vce between the collector and the emitter, which is necessary for obtaining the specified collector current IC, is low in order to reduce the power consumption. ing.

This saturation voltage Vce decreases as the resistance value in the n-type epitaxial layer 530 corresponding to the carrier drift region decreases. Further, this resistance value becomes lower as the total carrier concentration becomes higher.

In the conventional lateral IGBT structure shown in FIG. 16, p-type collector region 510 is formed in the surface region of n-type epitaxial layer 530. This is inevitably p
Around the type collector region 510, a hole carrier accumulation layer C ₀ was formed due to the presence of the pn junction.

The presence of the carrier storage layer C ₀ increases the hole concentration in the drift region. According to the law of conservation of charge, an increase in hole concentration is accompanied by an increase in electron concentration in the drift region.
As a result, the total carrier concentration in the drift region is doubled.
Therefore, the apparent total amount of carriers in the drift region is
The impurity concentration of the n-type epitaxial layer becomes higher than that of the n-type epitaxial layer itself, and the resistance value of the drift region becomes lower than that of the n-type epitaxial layer itself.

As described above, since the IGBT generally has a carrier storage layer in the drift region due to its structure, the saturation voltage Vce is lower than that of a MOSFET or the like which does not have the carrier storage layer.
It has the advantage of low power consumption. However, the demand for power saving is still strong, and the emergence of IGBTs with lower power consumption is desired.

A second object of the present invention is to provide a lateral IGBT having a novel structure that meets the demand for power saving.

[0030]

A first characteristic of the lateral insulated gate bipolar transistor of the present invention is that a first semiconductor layer having a first conductivity type and a first semiconductor layer formed in a surface region of the first semiconductor layer are provided. A base region having two conductivity types, an emitter region having a first conductivity type formed in a partial surface region in the base region, and an exposure from the emitter region to the first semiconductor layer through the base region. A gate insulating film formed so as to cover the surface, and a gate electrode formed on the exposed surface reaching the first semiconductor layer through the emitter region and the base region via the gate insulating film.
A collector region having a second conductivity type formed in a surface region of the first semiconductor layer independently of a base region; an emitter electrode electrically connected to the emitter region and the base region; and the collector region. In a lateral insulated gate bipolar transistor having a collector electrode electrically connected to, the emitter region is offset from a main current path of carriers flowing from the collector region to the base region through the first semiconductor layer. Is to be placed.

According to the first aspect of the present invention, since the main current path of the carrier does not pass through the emitter region when passing through the base region, the resistance of the base region and the inside of the base region. The voltage drop due to the movement distance of the carrier does not occur between the emitter electrode and the first semiconductor region. Therefore, the operation of the parasitic transistor composed of the emitter region, the base region and the first semiconductor layer is suppressed, and the latch-up can be prevented from occurring.

A second characteristic of the lateral insulated gate bipolar transistor of the present invention is that a second semiconductor layer having a first conductivity type and a second semiconductor layer formed in a surface region of the first semiconductor layer are provided.
A base region having a conductivity type, an emitter region having a first conductivity type formed in a partial surface region in the base region, and an exposed surface extending from the emitter region through the base region to the first semiconductor layer. A gate insulating film formed so as to cover the first semiconductor layer, a gate electrode formed on the exposed surface reaching the first semiconductor layer through the emitter region and the base region, the gate electrode being formed via the gate insulating film, and the first semiconductor. A collector region having a second conductivity type formed independently of the base region in the surface region of the layer, an emitter electrode electrically connected to the emitter region and the base region, and electrically connected to the collector region. A lateral insulated gate bipolar transistor having a collector electrode
Of the horizontal boundary lines of the base region, the boundary line facing the collector region has a regular irregular shape in a plane, and the emitter region has the shortest distance between the collector region and the base region. That is, they are arranged so as to be displaced from the straight line path that connects the two regions at the position.

According to the second aspect of the present invention, since the boundary line of the base region facing the collector region has the regular uneven shape as described above, the gap between the collector region and the base region is large. The distance changes regularly depending on the place. The main carriers flowing from the collector region to the base region through the first semiconductor layer flow along the path having the shortest distance between the two regions. Therefore, if the emitter region is arranged so as to be displaced from the shortest linear path, the emitter region will not be formed on the main current path of the carrier. Therefore,
It is possible to suppress the operation of the parasitic transistor including the emitter region, the base region, and the first semiconductor layer, and prevent the occurrence of latch-up.

The third characteristic of the lateral insulated gate bipolar transistor of the present invention is that the first semiconductor layer having the first conductivity type and the base region having the second conductivity type formed in the surface region of the first semiconductor layer. And an emitter region having a first conductivity type formed in a partial surface region in the base region, and an exposed surface from the emitter region to the first semiconductor layer via the base region. A gate insulating film, a gate electrode formed on the exposed surface reaching the first semiconductor layer through the emitter region and the base region via the gate insulating film, and a base region on the surface region of the first semiconductor layer. A collector region independently of the second conductivity type, an emitter electrode electrically connected to the emitter region and the base region, and an electrical collector electrode electrically connected to the collector region. And a collector electrode connected, on the plane, the collector region is disposed in the device center,
In a lateral insulated gate bipolar transistor in which the gate electrode is arranged to annularly surround the collector region at regular intervals, the base region and the emitter region are self-implanted by an ion implantation method using the gate electrode as a mask. It is formed in alignment, the outer boundary line of the gate electrode has a shape having regular irregularities in a plane, and the emitter region is formed between the outer boundary line of the gate electrode and the collector region. This means that the two regions at the position where the distance is the shortest are displaced from the straight line path connecting the straight lines.

According to the third feature of the present invention, the base region and the emitter region are formed in a self-aligned manner by the ion implantation method using the gate electrode as a mask. It depends on the planar shape of the gate electrode. Therefore, the planar shape of the lateral boundary line of the base region on the side close to the collector region has regular irregularities, like the planar shape of the gate electrode.

Further, a straight line connecting the outer boundary line of the gate electrode and the collector region with a straight line at the position where the distance between the outer boundary line of the gate electrode and the collector region is the shortest is the distance between the collector region and the base region. Is substantially the same as the shortest path, and this shortest straight path is the main current path of carriers flowing into the base region through the first semiconductor layer. Therefore, by arranging the emitter region so as to deviate from this straight line path, the operation of the parasitic transistor formed of the emitter region, the base region and the first semiconductor layer can be suppressed, and the occurrence of latch-up can be prevented.

The fourth characteristic of the lateral insulated gate bipolar transistor of the present invention is, in addition to the third characteristic, that the gate electrode has a comb-shaped planar shape having comb teeth on the outside, and the base region is It has a planar shape having an uneven boundary line along the shape of the outer boundary line, slightly inside the outer boundary line, and the emitter region is formed below both ends of each comb tooth of the gate electrode. It has a strip-shaped planar shape.

According to the fourth aspect of the present invention, the distance between the base region and the collector region is determined by the path connecting the base region and the collector region formed under the gate electrode between the adjacent comb teeth. Since they are closest to each other, the main current path of the carrier is formed here. Since the emitter region does not exist on this main current path, the operation of the parasitic transistor formed of the emitter region, the base region and the first semiconductor layer can be suppressed, and the latch-up can be prevented.

A fifth characteristic of the lateral insulated gate bipolar transistor of the present invention is that in addition to the fourth characteristic, the gate electrode has a planar shape in which the width of each comb tooth is narrowed down only at the root portion of the tooth. That is, the emitter region is formed below both end portions of the comb teeth in a portion ahead of the narrowed portion.

According to the fifth feature of the present invention, in addition to the action of the fourth feature, the width of the base of the comb teeth of the gate electrode is narrowed, so that it faces the collector region before the emitter region. The width of the base region can be increased.
Therefore, the carriers can be more reliably taken into the base region before the emitter region, and the latch-up can be suppressed more effectively.

A sixth characteristic of the lateral insulated gate bipolar transistor of the present invention is, in addition to the third characteristic, that the outer boundary line of the gate electrode has a planar shape of pseudo-wave-shaped unevenness, Has a planar shape having an uneven boundary line along the shape of the outer boundary line, slightly inside the outer boundary line, and the emitter region has lower portions on both sides of each of the convex portions of the outer boundary line. It has a strip-shaped planar shape.

According to the sixth aspect of the present invention, since the shapes of the base region and the emitter region depend on the planar shape of the gate electrode, the distance between the base region and the collector region is a pseudo-waveform of the gate electrode. Are closest to each other in the path connecting the base region and the collector region formed in the concave groove portion. Therefore, the main current path of the carrier is formed here. Since the emitter region does not exist on this main current path, the operation of the parasitic transistor formed of the emitter region, the base region and the first semiconductor layer can be suppressed, and the latch-up can be prevented.

A seventh characteristic of the lateral insulated gate bipolar transistor of the present invention is that a second semiconductor layer having a first conductivity type and a second semiconductor layer formed in a surface region of the first semiconductor layer are provided.
A base region having a conductivity type, an emitter region having a first conductivity type formed in a partial surface region in the base region, and an exposed surface extending from the emitter region through the base region to the first semiconductor layer. A gate insulating film formed so as to cover the first semiconductor layer, a gate electrode formed on the exposed surface reaching the first semiconductor layer through the emitter region and the base region, the gate electrode being formed via the gate insulating film, and the first semiconductor. A collector region having a second conductivity type formed independently of the base region in the surface region of the layer, an emitter electrode electrically connected to the emitter region and the base region, and electrically connected to the collector region. And a collector electrode that is formed, and the collector region is arranged in the center of the element on a plane,
In a lateral insulated gate bipolar transistor in which the gate electrode is arranged so as to annularly surround the collector region at regular intervals, the gate electrode has a strip shape in which rectangular openings are arranged in a row in the longitudinal direction at regular intervals. The base region and the emitter region have a planar shape of
It is formed by using the gate electrode as a mask and implanting ions into the opening, and the base region is formed in a self-aligned manner by implanting ions into the entire opening. , The emitter region is
It is to be formed in a region of the opening except a part of the side close to the collector region.

According to the seventh aspect of the present invention, the carriers flowing into the base region through the first semiconductor layer flow into the base region which is in front of the emitter region as seen from the collector region. Therefore, since the emitter region does not exist on the main current path of this carrier, the operation of the parasitic transistor formed of the emitter region, the base region and the first semiconductor layer can be suppressed, and the occurrence of latch-up can be suppressed.

An eighth characteristic of the lateral insulated gate bipolar transistor of the present invention is that the first semiconductor layer is surrounded by a dielectric layer.

According to the eighth feature of the present invention, the parasitic capacitance of the wiring can be reduced.

A ninth characteristic of the lateral insulated gate bipolar transistor of the present invention is that a second semiconductor layer having a first conductivity type and a second semiconductor layer formed on a surface region of the first semiconductor layer are provided.
A base region having a conductivity type, an emitter region having a first conductivity type formed in a partial surface region in the base region, and an exposed surface extending from the emitter region through the base region to the first semiconductor layer. A gate insulating film formed so as to cover the first semiconductor layer, a gate electrode formed on the exposed surface from the emitter region to the base region to the first semiconductor layer via the gate insulating film, and the first semiconductor Formed in the surface region of the layer independently of the base region,
A lateral insulated gate bipolar transistor having a collector region having a second conductivity type, an emitter electrode electrically connected to the emitter region and the base region, and a collector electrode electrically connected to the collector region, A width L covered by the gate electrode on the first semiconductor layer, which is a main current path of carriers flowing from the collector region to the base region through the first semiconductor layer.
_G is at least 3 times or more the channel length L _C of another carrier formed under the gate electrode.

According to the ninth feature of the present invention, a low-resistance electron storage layer is formed on the surface layer of the first semiconductor layer, which is covered with the gate electrode and is adjacent to the base region. The presence of this low-resistance electron storage layer lowers the electric field gradient between the base region and the edge of the gate electrode and limits the drift velocity of hole carriers. Therefore, the hole carriers whose flow is blocked remain at the end of the gate electrode to form an accumulation layer. Due to the existence of the hole accumulation layer, the total number of carriers in the first semiconductor layer, which is a carrier drift region, increases, and the saturation voltage generated between the collector region and the emitter region can be reduced.

[0049]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 6 (b).

FIG. 1A is a plan view showing the structure of the lateral IGBT according to the first embodiment. In the drawing, the n-type emitter region, the p-type base region, the emitter electrode, and the collector electrode are omitted, and only the gate electrode 40 and the collector region 10 are shown (hereinafter, planes in each embodiment). Same in the figure).

The IGBT is formed in the surface region of the n-type epitaxial layer formed on the surface of the Si substrate as a base substrate with an insulating film interposed therebetween. As shown in FIG. 1A, as in the conventional case, the strip-shaped collector region 10 is arranged in the center, and the gate electrode 40 is formed in an annular shape around the collector region 10 at a constant interval. The IGBT according to the first embodiment is characterized in that the gate electrode 40 has a comb shape. In addition, a diagram in which the comb teeth Pg of the gate electrode and the periphery thereof are further enlarged is shown in the lower left part of FIG.

FIG. 1B is an enlarged plan view in which the area around the one-dot chain line A1-A'1 shown in FIG. 1A is enlarged. The strip-shaped collector region 10 is shown on the right side of the figure, and the comb-shaped gate electrode 40 is shown on the left side of the figure. Each comb tooth Pg is formed outside the gate electrode, and an inner (right side in the figure) boundary line of the gate electrode 40 is shown by a straight line parallel to the boundary line of the collector region 10.

A broken line 50a formed slightly inward of the comb shape of the gate electrode 40 indicates the p-type base region 5.
This shows the boundary line of 0. The p-type base region 50 is formed on the left side of the broken line 50a in the figure, that is, on the outer side.

On both sides of each comb tooth Pg of the gate electrode 40,
A pair of rectangular n-type emitter regions 60 is formed. Each n-type emitter region 60 is formed slightly outside the root portion Bg of each comb tooth of the gate electrode 40. Therefore, the n-type emitter region 60 is closer to the gate electrode Bg corresponding to the bottom of the comb-shaped groove, that is, the position of the boundary line of the p-type base region 50 formed below the gate electrode 40 between the comb teeth Pg.
It is formed at a position away from the central collector region 10 (on the left side in the drawing).

In the IGBT shown in FIG. 1B, MO
The channel of the SFET is formed in the surface region of the p-type base region 50 between the n-type emitter region 60 and the n-type epitaxial layer 30 below both ends of each comb tooth Pg of the gate electrode 40.

Therefore, the electrons (e) in this IGBT are
An example of the current path of
80b. As indicated by the solid line 80a, the electrons pass from the respective n-type emitter regions 60 through the channels under both ends of the comb teeth Pg of the gate electrode 40, and as indicated by the solid line 80b, the electrons are under the central lower part of each comb tooth Pg of the gate electrode 40. It flows into the n-type epitaxial layer 30, and further flows in the surface region of the n-type epitaxial layer 30 toward the collector region 10. That is, the main electrons move in a direction nearly perpendicular to the comb teeth Pg of the gate electrode 40 at the time of passing through the channel, and thereafter change their moving direction in a direction substantially parallel to the comb teeth Pg of the gate electrode.

On the other hand, the current path of the hole (h) is as shown by the solid line 90, for example. Generally, the carrier is
It is natural to select the current path with the least resistance load, and the holes injected from the collector region 10 into the n-type epitaxial layer 30 flow toward the p-type base region 50 closest to the collector region 10. That is, the main holes flow from the collector region 10 toward the p-type base region 50 formed below the gate electrode Bg between the comb teeth.

Thus, when observing the current paths of electrons and holes on a plane, the main electrons are the comb teeth P of the gate electrode 40.
A surface region of the n-type epitaxial layer 30 below g and on the extension line of the comb tooth Pg is used as a current path. On the other hand, the main hole is the p-type base region 5 under the gate electrode Bg between the comb teeth.
A path connecting 0 and the collector region 10 with the shortest distance is used as a current path, and the current paths of electrons and holes are separated in a plane. Further, unlike the conventional IGBT, the n-type emitter region does not exist on the current path of the main holes.

Next, with reference to FIGS. 2A to 2C, the above-described current paths of electrons and holes are observed again from the cross section of the device.

FIG. 2A shows a chain line A in FIG. 1B.
It is a sectional view in 1-A'1. FIG. 2B is a sectional view taken along one-dot chain line B1-B′1 in FIG. FIG. 2C is a dashed-dotted line C1- in FIG.
It is a sectional view in C'1.

As shown in FIG. 2A, the gate electrode 40
In the cut surface passing between the comb teeth of
The holes (h) injected into the epitaxial layer 30 are
It passes through the surface region of the n-type epitaxial layer 30, enters the p-type base region 50, and reaches the emitter electrode E. Since the n-type emitter region 60 does not exist on the current path of the hole, there is no parasitic npn transistor at this cut surface.

As shown in FIG. 2B, the gate electrode 40
In the cut surface obtained by cutting the comb teeth Pg of the above in a direction perpendicular to the direction of the comb teeth, the p-type base regions 50 are formed below both ends of the comb teeth Pg of the gate electrode 40, and the n-type is formed in the surface region. An emitter region 60 is formed. The gate electrode 40 is formed via the gate insulating film 100 so as to cover a part of the n-type emitter regions 60 on both sides.

An electron channel is formed in the surface region of the p-type base region 50 below the gate electrode 40, and the electron passes through this channel and enters the n-type epitaxial layer 30 below the comb teeth Pg of the gate electrode 40. Since there are almost no holes having current paths around the cut surface, the n-type emitter region 6
0, the p-type base region 50, and the n-type epitaxial layer 30 do not operate the parasitic npn transistor.

As shown in FIG. 2C, the gate electrode 40
In the cross section in the comb tooth direction passing through the center of the comb tooth Pg of
A p-type base region is formed below the tips of the comb teeth of the gate electrode 40. Electrons that enter the n-type epitaxial layer 30 through the channel under the gate electrode 40 move along the main surface of the n-type epitaxial layer 30 and reach the p-type collector region 10. At this cut surface, the n-type emitter region 60 does not exist, so that the parasitic npn transistor does not exist. The hole current path is hardly formed in this region.

Thus, the IG according to the first embodiment is
As shown in FIG. 1A, since the BT has a planar configuration in which the n-type emitter region is displaced from the main current path of the holes, the npn parasitic transistor does not operate and latch-up is prevented. Occurrence can be suppressed.

In order to suppress the occurrence of latch-up more effectively, holes are formed in the p-type base region 50 below the gate electrode Bg between the comb teeth of the comb-shaped gate electrode 40.
The gate electrode Bg between each comb tooth so as to flow more reliably.
It is desirable to make the shortest distance Ln between the collector region 10 and the n-type emitter region 60 longer than the shortest distance Lp between the underlying p-type base region 50 and the collector region 10.

The distance Lp at which the collector region 10 and the p-type base region 50 are closest to each other is mainly determined by the withstand voltage design value of the device and the like. For example, when a withstand voltage value of 500 V is required, the distance Lp is set to about 50 μm.

According to the experiments by the inventors, the distance Lp is 50
μm and the distance Ln is 55 μm, the conventional IGBT
Compared with the above, the occurrence of latch-up could be suppressed sufficiently. The length of the comb teeth Pg of the gate electrode used at this time was 11 μm, and the interval between the adjacent comb teeth Pg was 14 μm.

The IGBT shown in the first embodiment can be manufactured by using a general lateral IGBT manufacturing method. Hereinafter, the SOI (Silicon) will be described with reference to FIGS.
The steps of a method for manufacturing an IGBT using an On Insulator) substrate will be briefly described. Note that the right side of each drawing is a cross-sectional view taken along the alternate long and short dash line A1-A′1 shown in FIG. 1B, and the left side is a cross sectional view taken along the alternate long and short dash line B1-B′1 in FIG. 1B. Below, A1-A'1 cross section, B1-B '
1).

The SOI substrate is, as shown in FIG.
It is composed of a Si single crystal substrate 110 as a base substrate, an intermediate insulating film 120 formed thereon, and an Si n-type epitaxial layer 30 further formed on the intermediate insulating film 120. The thickness of the intermediate insulating film 120 is, for example, about 3 to 4 μm.
m SiO ₂ layer is used, and Si epitaxial layer 30
For example, an n-type Si layer doped with phosphorus (P) at about 5 × 10 ¹⁴ / cm ³ is used. As a method for manufacturing an SOI substrate, there is a wafer direct bonding method or the like.

Usually, after this, the n-type epitaxial layer 30 is formed.
A field oxide film is formed by thermally oxidizing the surface of the. As will be described later, when forming a deep diffusion region,
This field oxide film is patterned, ions are implanted using the pattern as a mask, and a diffusion layer is formed by annealing. Then, if necessary, the field oxide film is removed by etching to expose the surface of the n-type epitaxial layer 30 again.

By thermally oxidizing the surface of the substrate, a gate oxide film 100 having a film thickness of about 50 to 500 nm is formed on the n-type epitaxial layer 30. A SiO ₂ film is usually used as the gate oxide film 100, but an insulating film other than this may be used.

Further, a reduced pressure CV is formed on the gate oxide film 100.
Using the D method, a polycrystalline Si film 40a doped with phosphorus (P) and having a thickness of about 500 nm is formed. In the steps up to here, the A1-A′1 cross section and the B1-B′1 cross section have the same structure.

As shown in FIG. 3B, the polycrystalline Si film 4
0a is patterned using a normal photolithography process to form a gate electrode 40. Further, a resist film is formed on the surface of the substrate on which the gate electrode 40 is formed, and this is patterned to obtain a resist pattern 130.

Gate electrode 40 and resist pattern 130
Using the as a mask, p-type impurity ions of boron (B) are implanted into the substrate surface by an ion implantation method. The ion implantation condition used at this time is, for example, an ion implantation energy of 40.
˜50 keV and a dose amount of 10 ¹³ to 10 ¹⁴ / cm ² . After that, the substrate is annealed at about 1100 ° C. for 5 hours to 10 hours to simultaneously form the p-type base region 50 and the p-type collector region 10 having a diffusion depth of about 2 to 3 μm. Since the gate electrode 40 is used as an implantation mask, p
The shape of the inner boundary line of the mold base region 50 is the gate electrode 4
It depends on the shape of the outer boundary line of 0. After this,
The resist pattern 130 remaining on the substrate is removed by etching.

As shown in FIG. 4C, a resist pattern 140 is formed again on the surface of the substrate. Using the resist pattern 140 and the gate electrode 40 as a mask, arsenic (As) ions, which are p-type impurities, are implanted into the substrate surface region by an ion implantation method. Ion implantation conditions may be, for example, an ion implantation energy of 30 to 40 keV and a dose amount of about 10 ¹⁵ / cm ² . After this about 900 ℃ ~
The substrate is annealed at 1000 ° C. for about 10 to 20 minutes to form an n-type emitter region 60 having a diffusion depth of about 0.2 to 0.3 μm. The unnecessary resist is removed after this.

As shown in FIG. 4D, an interlayer insulating film 160 having a film thickness of about 1.5 μm to 3 μm is formed on the surface of the substrate by using the CVD method. As the interlayer insulating film 160, Si
O ₂ film, boron phosphosilicate glass (BPS
It may be a G) film or a laminated film thereof.

As shown in the figure, the p-type collector region 1
Contact holes are opened in the interlayer insulating film 160 on the 0, p-type base region 50 and the n-type emitter region 60, respectively. Then, an aluminum (Al) film having a film thickness of about 1 to 4 μm is formed on the surface of the substrate by using a sputtering method, and these contact holes are filled. This Al film is patterned using a photolithography process, and p
Collector electrode 17 connected on the mold collector region 10
0, and p-type base region 50 and n-type emitter region 60
An emitter electrode 180 connected to the.

Thereafter, as in the case of manufacturing a normal IGBT, a passivation film is formed on the surface of the substrate, and the substrate is cut into individual chips as necessary.

IGBT in another embodiment described later
Can also be manufactured using the steps described above.

As shown in FIG. 5E, the p-type collector region 10 is formed so that holes are efficiently injected from the p-type collector region 10 into the n-type epitaxial layer 30.
A high-concentration n-type diffusion layer 190 may be formed around the.

In this case, as already described in the step shown in FIG. 3A, a field oxide film pattern is formed on the surface of the n-type epitaxial layer 30 before the gate oxide film 100 is formed. Using the pattern of the field oxide film as a mask, n-type impurity ions such as phosphorus are ion-implanted and annealed to form a high-concentration n-type impurity diffusion layer 190.

FIG. 6A shows an example of a plane structure of another gate electrode 40 in the first embodiment.
The comb teeth of the gate electrode need not be formed around the entire circumference of the ring-shaped gate electrode 40, as shown in FIG. Figure 6
As shown in (a), the comb teeth may be formed only on the linear portion of the annular gate electrode 40 excluding the curved portion. Since the unit cell of the IGBT is formed for each comb tooth, the number of comb teeth to be formed may be adjusted according to the required number of cells.

Further, in order to obtain a higher current value, a plurality of IGBTs may be formed on a single chip. Figure 6
In (a), two IGBTs are formed in parallel on the chip, and the extraction electrodes taken out from the ends of the respective gate electrodes are common.

FIG. 6B shows a chain line D in FIG.
It is a sectional view in 1-D'1. The structure of the cut surface is
The structure is almost the same as the structure shown in FIG. 2B, but the cross-sectional structure of a wider region is shown.

Collector region 10 is formed in the central surface region of n-type epitaxial layer 30, and n-type high-concentration impurity region 190 is formed around it. On both sides of the collector region 10, a p-type base region 50 is formed in the surface region of the n-type epitaxial layer 30 with a slight distance, and an n-type emitter region 60 is formed in the inner surface region thereof. . The gate electrode 40 is formed so as to cover a part of the n-type emitter region 60, the p-type base region 50 and the n-type epitaxial layer 30 via the gate oxide film. The collector region 10 is electrically connected to the collector electrode C, the n-type emitter region 60 and the p-type base region 50 are connected to the emitter electrode E, and the gate electrode 40 is connected to the gate extraction electrode G.

As shown in FIG. 6B, the dielectric 120 such as SiO ₂ is formed on the bottom surface around the n-type epitaxial layer 30.
Are formed. Further, by surrounding the n-type epitaxial layer 30 with a dielectric layer 120a having a depth from the substrate surface to the dielectric layer 120 outside the n-type emitter region 60, the parasitic capacitance can be reduced. . The structure of such a dielectric layer can be effectively applied to other embodiments.

(Second Embodiment) FIGS. 7A to 7
The IGBT according to the second embodiment will be described with reference to (c). IGB in the first embodiment described above
Similar to T, a strip-shaped collector region 10 is formed in the center of the device, and a ring-shaped gate electrode 41 is arranged around the collector region 10 in a planar structure of the device.

FIG. 7A shows the I of the second embodiment.
It is an enlarged plan view showing a part of GBT. Although the gate electrode 41 has a comb shape in the first embodiment,
Here, the both sides of each comb tooth are inclined so that each comb tooth has a trapezoidal shape. Therefore, the outer boundary line of the gate electrode 41 has a pseudo wave-shaped uneven shape.

As described in the first embodiment, the p-type base region 51 is formed in a self-aligned manner by using the gate electrode 41 as an ion implantation mask.
The shape of the mold base region 51 depends on the shape of the gate electrode 41. A broken line 71 a drawn slightly inside the outer boundary line of the gate electrode 41 becomes the inner boundary line of the p-type base region 51.

In the figure, a solid line 81 indicates an electron current path. Electrons are transferred from the n-type emitter region 61 to the gate electrode 41.
It enters the n-type epitaxial layer 30 through the channel formed below and further reaches the collector region 10. Gate electrode 4
Since the comb teeth of No. 1 are trapezoidal, the channel is the gate electrode 41.
It will be formed slightly obliquely rather than perpendicularly to the inner boundary line of. Therefore, a smoother electron flow can be obtained.

On the other hand, the solid line 91 in FIG.
A current path of main holes injected from 0 to the epitaxial layer 30 is shown. These holes are located in the collector region 10
Located closest to the p-type base region 51, that is, p located under the concave portion of the gate electrode 41 having a pseudo-wave-shaped uneven shape.
It flows into the mold base region 51. As in the case of the first embodiment, the n-type emitter region 6 is formed on the current path of the main hole.
1 does not exist.

FIG. 7 (b) shows the alternate long and short dash line A in FIG. 7 (a).
It is a sectional view taken along line 2-A′2. FIG. 7C is a sectional view taken along alternate long and short dash line B2-B′2 in FIG.

As shown in FIG. 7B, a cross section that passes through the concave portion of the gate electrode 41 having a pseudo-wave-shaped concavo-convex shape and is perpendicular to the inner boundary line of the gate electrode 41 is mainly indicated by a solid line 91. A current path for the holes is formed. Since the n-type emitter region 61 does not exist on the current path of the hole, the parasitic npn transistor does not exist in this region.

Further, as shown in FIG. 7C, a current path of electrons is mainly formed on a cross section that passes through the n-type emitter region 61 and is perpendicular to the inner boundary line of the gate electrode 41. Channel and n-type emitter region 61 as in the conventional
Since there is no current path for holes flowing under, the parasitic npn transistor does not operate.

As described above, the IGBT according to the second embodiment is
Also in this case, since the n-type emitter region 61 is formed deviating from the current path of the main hole, the parasitic npn transistor does not operate and the latch-up is generated as in the case of the first embodiment described above. Can be suppressed.

(Third Embodiment) FIGS. 8A to 8
The IGBT according to the third embodiment will be described with reference to (c). A planar configuration of an element in which a strip-shaped collector region 10 is formed in the center and an annular gate electrode is arranged around the strip-shaped collector region 10 is similar to that of the IGBT in the first embodiment.

FIG. 8A shows the I of the third embodiment.
It is an enlarged plan view showing a part of GBT. The difference from the first embodiment is that the roots of the comb teeth of the comb-shaped gate electrode 42 are narrowed down. Therefore, the boundary line of the p-type base region 52 formed in a self-aligned manner using the gate electrode 42 also has substantially the same shape. The broken line 52a drawn slightly inside the outer boundary line of the gate electrode 42 is p
It becomes an inner boundary line of the mold base region 52. The n-type emitter regions 62 are formed on the lower portions on both sides of the tip portions of the wide comb teeth.

The electron current path shown by the solid line 82 in the figure and the hole current path shown by the solid line 92 are almost the same as in the case of the first embodiment.

Since the width of the base of the comb teeth of the gate electrode 42 is narrowed, the width of the p-type base region 52 facing the collector region 10 is expanded before the n-type emitter region 62 accordingly. Therefore, it becomes possible to more surely capture the holes in the p-type base region 52 before the n-type emitter region 61.

FIG. 8B shows a chain line A in FIG.
It is a sectional view taken along line 3-A′3. FIG. 8C is a cross-sectional view taken along alternate long and short dash line B3-B′3 in FIG. The current paths of electrons and holes in each cut surface are almost the same as in the case of the first embodiment.

As shown in FIG. 8B, the gate electrode 42
In the cross section that passes between the comb teeth and is perpendicular to the inner boundary line of the gate electrode, the main hole is n-type epitaxial layer 30 from the collector region 10 as shown by the solid line 92.
To reach the p-type base region 52. The current path is formed along the main surface of the substrate, and since there is no n-type emitter region 62 on this current path, there is no parasitic npn transistor.

Further, as shown in FIG. 8C, the lower surface of each comb tooth of the gate electrode 42 in which the n-type emitter region 62 is formed is cut in parallel with the inner boundary line of the gate electrode. , Electrons that have passed through the channels on both sides merge under the center of the gate electrode 42, and then flow into the collector region in the direction toward the back of the drawing. Here, a current path of electrons is mainly formed, and a current path of holes flowing under the channel and the n-type emitter region 61 unlike the conventional IGBT does not exist, so that the parasitic npn transistor does not operate.

(Fourth Embodiment) FIGS. 9A to 10
The IGBT according to the fourth embodiment will be described with reference to (b). The planar configuration of the element in which the strip-shaped collector region 10 is formed in the center and the annular gate electrode 43 is arranged around the strip-shaped collector region 10 is similar to that of the IGBT in the first embodiment described above.

FIG. 9A shows the I of the fourth embodiment.
It is an enlarged plan view showing a part of GBT. As shown in the figure, the gate electrode 43 has rectangular openings 43 at regular intervals.
a is formed. The p-type base region 53 is formed in a rectangular region surrounded by a broken line 53a provided around the opening 43a. The n-type emitter region 63 is inside the p-type base region 53 and outside the center of the opening 43a, that is, the opening 43a on the side away from the collector region 10.
It is formed in a concave shape around the periphery.

As shown by the solid line 83a, the electrons pass through the channel formed under the gate electrode 43 from the n-type emitter region 63 and reach the surrounding n-type epitaxial layer 30. After this, as indicated by the solid line 83b, the p-type base region 5 is
3 flows toward the collector region 10 in the n-type epitaxial layer 30 around the outer periphery.

On the other hand, the holes are, as shown by the solid line 93,
It flows from the collector region 10 through the n-type epitaxial layer 30 into the p-type base region 53 adjacent to the collector region. Similar to the first to third embodiments described above, also in this case, the n-type emitter region 63 does not exist on the current path of the hole. The electron current paths are mainly formed on both sides of the hole current path, and the electron and hole current paths are separated on a plane.

FIG. 9B shows a chain line A in FIG. 9A.
It is a sectional view taken along line 4-A′4. As shown in FIG. 9B, in the cross section that passes through the opening 43 a provided in the gate electrode 43 and is perpendicular to the inner boundary line of the gate electrode 43, the electron channel of the MOSFET is closer to the center of the opening. It is formed below the outer gate electrode 43. As indicated by the solid line 83 in the figure, the electrons pass through the channel from the n-type emitter region 63 and enter the n-type epitaxial layer 30 outside the n-type emitter region 63. After that, it passes under the p-type base region 53 and reaches the p-type collector region 10. On the other hand, from the p-type collector region 10 to the n-type epitaxial layer 3
The holes injected at 0 flow along the main surface of the n-type epitaxial layer 30 as shown by the solid line 93, and p
Reach the mold base region 53.

Since the distance that the holes move in the p-type base region 53 is short, the parasitic npn transistor formed of the n-type emitter region 63, the p-type base region 53 and the n-type epitaxial layer 30 does not operate.

Here, the n-type emitter region 63 is used.
Is formed in a concave shape outside the center of the rectangular opening 43a, but a rectangular n-type emitter region is formed around only one side of the opening 43a located farthest from the collector region 10. Good. However, by forming the n-type emitter region in the concave shape as described above, it is possible to substantially widen the width of the channel portion and reduce the resistance of the channel.

FIG. 10A is a plan view showing another IGBT having the same gate electrode pattern as the IGBT in the above-mentioned fourth embodiment. Fourth shown in FIG.
The difference from the IGBT in the embodiment is that the n-type emitter region 64 is formed in a frame shape corresponding to the rectangular opening of the gate electrode 44.

Along with this, a frame-shaped electron channel region is formed around the opening of the gate electrode. Therefore, the channel width is substantially widened, the resistance of the channel portion is lowered, and a high current value can be obtained.

FIG. 10B is a sectional view taken along alternate long and short dash line A5-A'5 in FIG. As shown in the figure, by forming the n-type emitter region 64 in a frame shape, the n-type emitter region 64 is also formed in the inner surface region of the p-type base region 54.

Therefore, the holes injected from the p-type collector region 10 into the n-type epitaxial layer 30 flow along the main surface of the n-type epitaxial layer 30 as shown by the solid line 94, and then the p-type base layer is formed. It enters the region 54, passes under the n-type emitter region 64 on the front side, and reaches the emitter electrode E2. In this case, as in the case of the conventional IGBT,
Although there is a possibility of latch-up, if attention is paid to the MOSFET having the outer n-type emitter region 64, it has the effect of preventing latch-up as in the case of the fourth embodiment described above. .

(Fifth Embodiment) FIG. 11A to FIG.
The IGBT according to the fifth embodiment will be described with reference to FIG. This IGBT has the effect of suppressing the occurrence of latch-up and suppressing the saturation voltage Vce to a low level.

FIG. 11A is a plan view showing the structure of this IGBT. FIG. 11B is an enlarged plan view of the area around the alternate long and short dash line A6-A′6 shown in FIG. The basic configuration is common to the IGBT shown in the above-described first embodiment. On the substrate, as in the case of the IGBT in the first embodiment shown in FIG. 1A, the strip-shaped collector region 10 and the ring-shaped comb-shaped gate electrode 45 around the strip-shaped collector region 10 with a constant space therebetween. Have.

The difference from the IGBT in the first embodiment is that the p-type base region 50 between the comb teeth Pg of the gate electrode is formed.
That is, the distance L _G between the boundary of the gate electrode and the inner boundary of the gate electrode 45 is widened. That is, the feature is that the n-type epitaxial layer 30, which is a carrier drift region, is widely covered with the gate electrode.

FIG. 12A is a sectional view taken along alternate long and short dash line A6-A'6 in FIG. 11A. Figure 12 (b)
FIG. 12 is a sectional view taken along alternate long and short dash line B6-B′6 in FIG.

As shown in FIG. 12A, also in this case, the hole carriers injected from the collector region 10 into the n-type epitaxial layer 30 pass through the surface layer of the n-type epitaxial layer 30 and the p-type base region 50. Emitter electrode E
To reach. However, the IGB in the fifth embodiment
At T, since the surface of the n-type epitaxial layer 30 is widely covered by the gate electrode 45 via the gate oxide film 100, the mode of carrier movement is different from that of the IGBT in the first embodiment.

In the surface region of the n-type epitaxial layer 30 covered with the gate electrode 45, electron carriers are induced and an electron storage layer C1 is formed. The electron accumulation layer C1 becomes a region having a low resistance value due to the presence of high-concentration electrons. Therefore, the potential difference ΔV (L _G ) between immediately below the inner end of the gate electrode 45 and the p-type base region 50 becomes extremely small.

Since the drift velocity of the hole carriers depends on the electric field strength, when the potential difference ΔV (L _G ) between the p-type base region 50 and the inner end portion of the gate electrode 45, which is the moving path of the carriers, decreases, the hole carriers decrease. Will also slow down the drift speed. As a result, the flow of the hole carriers is obstructed just below the inner end of the gate electrode 45, and the hole carriers stay there. This forms a new hole carrier storage layer C2.

That is, the IGBT according to the fifth embodiment
In the above, since not only the carrier storage layer C0 formed around the collector region 10 but also the new carrier storage layer C2 can be formed in the region adjacent to the gate electrode 45, the hole carrier concentration in the drift region is apparent. To increase. According to the law of conservation of charge, an increase in hole carrier concentration promotes an increase in electron carrier concentration to cancel the hole carrier concentration. As a result, the total carrier concentration in the drift region increases synergistically.

Increasing the total carrier concentration in the drift region reduces the resistance value of the drift region. As a result, the saturation voltage Vce, which is the voltage between the collector electrode C and the emitter electrode E, decreases.

FIG. 13 is a graph showing an example of the IV characteristic of the IGBT. Horizontal axis shows collector electrode C and emitter electrode E
A voltage Vce between them and a collector current Ic are shown on the vertical axis.
A broken line A is an example of the characteristics of the conventional IGBT, and a solid line B is an example of the characteristics of the IGBT in the fifth embodiment. As shown by the broken line A, in the conventional IGBT, when Vce exceeds about 0.6 V, the current value rises linearly, and eventually the current value becomes saturated. Here, the voltage between the collector electrode C and the emitter electrode E required to reach the specified collector current is called the saturation voltage.

For example, in order to obtain the specified current IX, the saturation voltage of VS is required in the conventional structure.
In the IGBT according to the embodiment described above, as a result of the resistance value of the drift region being lowered, the rising slope of the current with respect to the voltage is increased as shown by the solid line B, and the required saturation voltage is reduced to VX. Therefore, when the IGBT according to the fifth embodiment is used for a power switch or the like, it is possible to drive at a low voltage and reduce power consumption.

As the width of the drift region covered with the gate electrode is increased, the amount of hole carriers accumulated in the accumulation layer C2 is increased and the saturation voltage can be reduced. On the other hand, however, the area occupied by the gate electrode on the chip increases, which is disadvantageous in reducing the size of the chip.

[0127] Therefore, in the IGBT of the fifth embodiment, when the length of the electronic channel shown in FIG. 12 (b) and L _C, the distance L _G is preferably at least L _C of 3 times or more. Further, in FIG. 12A, the gate oxide film 10
Even with respect to the width L _B of the P-type base region 50 covered with the gate electrode 45 via 0, the distance L _G is preferably at least three times as large as L _B or more.

FIGS. 14 (a) to 15 (d) show another I having the same effect as that of the IGBT in the fifth embodiment.
It is a top view which shows the constructional example of GBT. In both cases, the width of the gate electrode is widened, and the wide range of the n-type epitaxial layer 30 that is the drift region is covered with the gate electrode. 14
(A) is based on the IGBT of the second embodiment,
With wider gate electrode 46, FIG.
(B) is based on the IGBT of the third embodiment,
With wider gate electrode 47, FIG.
(C) is provided with a wide gate electrode based on the IGBT of the fourth embodiment. These IGB
As described in each embodiment, T can prevent the occurrence of latch-up and reduce the saturation voltage.

Note that FIG. 15D is an IGBT having a wider gate electrode 49 based on the IGBT having the conventional structure shown in FIG. Also in this structure, the effect of reducing the saturation voltage can be obtained as in the structure described above.

In any case, the distance L _G between the boundary of the p-type base region 50, which is the drift region of hole carriers, and the inner boundary of the gate electrode 45 is 3 with respect to the electron channel length Lc under the gate electrode of each. It is preferably doubled or more.

The present invention has been described above with reference to the first to fifth embodiments, but the present invention is not limited to these. For example, in the above-described embodiment, the emitter region is n-type, the base region is p-type, and the epitaxial layer is n-type, but these conductivity types may be reversed.

In the plan views used to describe the first to fourth embodiments, the emitter electrode and collector electrode are not shown, but the emitter electrode is an n-type emitter region. The collector electrode may be electrically connected to the p-type base region, and the collector electrode may be electrically connected to the p-type collector region. Therefore, the pattern shape is not particularly limited. For example, as shown in FIG. 4D, each electrode may be formed over a wide area on the interlayer insulating film and connected to each diffusion region via a contact hole.

It will be apparent to those skilled in the art that various other changes, improvements, combinations and the like can be made.

[0134]

In the lateral insulated gate bipolar transistor of the present invention, since the emitter region is arranged laterally or outwardly from the main current path of carriers flowing from the collector region to the base region, the emitter region is arranged. The operation of the parasitic transistor formed of the base region and the first semiconductor layer can be suppressed, and the occurrence of latch-up can be suppressed.

Further, in the lateral insulated gate bipolar transistor of the present invention in which the width of the gate electrode covering the surface of the first semiconductor region corresponding to the carrier drift region is widened, the hole carrier accumulation layer is formed in the first semiconductor region adjacent to the gate electrode. It is possible to increase the substantially total number of carriers in the drift region and reduce the saturation voltage generated between the collector region and the emitter region. Therefore, the device can be operated at a low voltage, and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view of an element showing a configuration of an IGBT according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of an element showing the configuration of the IGBT according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of an element in each step for explaining the manufacturing step of the IGBT according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of the element in each step for explaining the manufacturing step of the IGBT according to the first embodiment of the present invention.

FIG. 5 is another IGB according to the first embodiment of the present invention.
It is sectional drawing of the element which shows the structure of T.

FIG. 6 is another IGB according to the first embodiment of the present invention.
It is a top view of the element which shows the structure of T.

7A and 7B are a plan view and a cross-sectional view of an element showing a configuration of an IGBT according to a second embodiment of the present invention.

FIG. 8 is a plan view and a cross-sectional view of an element showing a configuration of an IGBT according to a third embodiment of the present invention.

FIG. 9 is a plan view and a cross-sectional view of an element showing the configuration of an IGBT according to a fourth embodiment of the present invention.

FIG. 10 is another IG according to the fourth embodiment of the present invention.
It is the top view and sectional drawing of an element which show the composition of BT.

FIG. 11 is an IGBT according to a fifth embodiment of the present invention.
FIG. 3 is a plan view of an element showing the configuration of FIG.

FIG. 12 is an IGBT according to a fifth embodiment of the present invention.
3 is a cross-sectional view of an element showing the configuration of FIG.

FIG. 13 is an IGBT according to a fifth embodiment of the present invention.
5 is a graph showing the IV characteristic of FIG.

FIG. 14 is another IG according to the fifth embodiment of the present invention.
It is a top view of the element which shows the structure of BT.

FIG. 15 is another IG according to the fifth embodiment of the present invention.
It is a top view of the element which shows the structure of BT.

FIG. 16 is a sectional view of an element showing a configuration of a conventional IGBT.

FIG. 17 is a circuit diagram showing an equivalent circuit of a general IGBT and an equivalent circuit including a parasitic transistor.

FIG. 18 is a plan view of an element showing the configuration of a conventional IGBT.

[Explanation of symbols]

10 ... p-type collector region 20 ... Collector electrode 30: n-type epitaxial layer 40 to 49 ... Gate electrode 50-53 ... p-type base region 60-63 ... n-type emitter region 100: Gate oxide film C0, C2 ... Hole carrier storage layer C1 ... Electron carrier storage layer

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-5-335563 (JP, A) JP-A-8-139319 (JP, A) JP-A-9-74197 (JP, A) JP-A-9- 153615 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (10)

(57) [Claims] 1. A first semiconductor layer having a first conductivity type, a base region having a second conductivity type formed in a surface region of the first semiconductor layer, and a partial surface region in the base region. A formed emitter region having a first conductivity type; a gate insulating film formed to cover an exposed surface from the emitter region through the base region to the first semiconductor layer; the emitter region and the base; A gate electrode formed on the exposed surface reaching the first semiconductor layer through a region via the gate insulating film; and a second region formed independently of the base region on the surface region of the first semiconductor layer. Horizontal insulation having a collector region having a conductivity type, an emitter electrode electrically connected to the emitter region and the base region, and a collector electrode electrically connected to the collector region In a bipolar bipolar transistor, a lateral insulated gate bipolar transistor is characterized in that the emitter region is displaced from a main current path of carriers flowing from the collector region to the base region through the first semiconductor layer. . 2. A first semiconductor layer having a first conductivity type, a base region having a second conductivity type formed in a surface region of the first semiconductor layer, and a partial surface region in the base region. The formed emitter region having the first conductivity type, the gate insulating film formed on the exposed surface from the emitter region to the base region to the first semiconductor layer, and the emitter region to the base region. A gate electrode formed on the exposed surface of the first semiconductor layer via the gate insulating film, and a second conductivity type formed independently of the base region on the surface region of the first semiconductor layer. A lateral insulated gate electrode having a collector region, an emitter electrode electrically connected to the emitter region and the base region, and a collector electrode electrically connected to the collector region. In the polar transistor, among the horizontal boundary lines of the base region, a boundary line facing the collector region has a regular uneven shape in a plane, and the emitter region has the collector region and the base region. The lateral insulated gate bipolar transistor is characterized in that it is arranged so as to be displaced from the straight line path connecting the two regions at the position where the distance is the shortest. 3. A first semiconductor layer having a first conductivity type, a base region having a second conductivity type formed in a surface region of the first semiconductor layer, and a partial surface region in the base region. An emitter region having a first conductivity type, a gate insulating film formed on an exposed surface from the emitter region through the base region to the first semiconductor layer, and the emitter region through the base region and A gate electrode formed on the exposed surface reaching the first semiconductor layer via the gate insulating film, and a collector region having a second conductivity type formed in the surface region of the first semiconductor layer independently of the base region. And an emitter electrode electrically connected to the emitter region and the base region, and a collector electrode electrically connected to the collector region. In a center, and the gate electrode is arranged so as to annularly surround the collector region at a constant interval, the base region and the emitter region use the gate electrode as a mask. Which is formed by self-alignment by the ion implantation method described above, the outer boundary line of the gate electrode has a shape having regular irregularities on a plane, and the emitter region is an outer boundary line of the gate electrode. A lateral insulated gate bipolar transistor, wherein the outer boundary line at a position where the distance between the collector region and the collector region is the shortest and the collector region are arranged so as to be offset from a straight line path connecting the straight lines. 4. The gate electrode has a comb-shaped planar shape having comb teeth on the outside, and the base region is slightly inward of the outer boundary line and has an uneven shape along the shape of the outer boundary line. 4. The planar shape having a boundary line of 1., the emitter region being formed below both ends of each of the comb teeth of the gate electrode, and having a rectangular planar shape. Lateral insulated gate bipolar transistor. 5. The gate electrode has a planar shape in which the width of each of the comb teeth is narrowed down only at the root portion of the tooth, and the emitter region is formed of a comb tooth in a portion preceding the narrowed portion. The lateral insulated gate bipolar transistor according to claim 4, wherein the lateral insulated gate bipolar transistor is formed below both ends. 6. The outer boundary line of the gate electrode has a planar shape of pseudo-wave-shaped unevenness, and the base region extends slightly inward of the outer boundary line along the shape of the outer boundary line. 4. The lateral insulated gate bipolar transistor according to claim 3, wherein the emitter region has a planar shape having a concavo-convex boundary line, and the emitter region has a rectangular planar shape on the lower portions on both sides of each of the convex portions of the outer boundary line. 7. A first semiconductor layer having a first conductivity type, a base region having a second conductivity type formed in a surface region of the first semiconductor layer, and a partial surface region in the base region. The formed emitter region having the first conductivity type, the gate insulating film formed on the exposed surface from the emitter region to the base region to the first semiconductor layer, and the emitter region to the base region. A gate electrode formed on the exposed surface of the first semiconductor layer via the gate insulating film, and having a second conductivity type formed independently of a base region in a surface region of the first semiconductor layer. A collector region, an emitter electrode electrically connected to the emitter region and the base region, and a collector electrode electrically connected to the collector region; In a lateral insulated gate bipolar transistor in which the gate electrode is arranged so as to surround the collector region in a ring shape at regular intervals, the gate electrodes are arranged in a row in the longitudinal direction at regular intervals. Having a planar shape in which an opening is arranged, the base region and the emitter region are formed in a self-aligned manner by using a method of implanting ions into the opening using the gate electrode as a mask, The base region is formed by implanting ions into the entire opening, and the emitter region is formed in a region of the opening excluding a part of the opening close to the collector region. Is a lateral insulated gate bipolar transistor. 8. The lateral insulated gate bipolar transistor according to claim 1, wherein the first semiconductor layer is surrounded by a dielectric layer. 9. A first semiconductor layer having a first conductivity type, a base region having a second conductivity type formed in a surface region of the first semiconductor layer, and a partial surface region in the base region. A formed emitter region having a first conductivity type; a gate insulating film formed to cover an exposed surface from the emitter region to the base region to the first semiconductor layer; and the emitter region to the base. A gate electrode formed on the exposed surface reaching the first semiconductor layer through a region via the gate insulating film, and a second region formed on the surface region of the first semiconductor layer independently of the base region; A lateral isolation having a collector region having a conductivity type, an emitter electrode electrically connected to the emitter region and the base region, and a collector electrode electrically connected to the collector region. In gate bipolar transistor, the width L _G of the first semiconductor layer above corresponding to the main current path covers said gate electrode of the carrier flowing into the base region through said first semiconductor layer from the collector region, at least the gate electrode under A lateral insulated gate bipolar transistor, characterized in that the channel length L _C of another carrier formed in the above is three times or more. 10. A width L _{G at} which the gate electrode covers at least the first semiconductor layer, which is a main current path of carriers flowing from the collector region to the base region through the first semiconductor layer, is at least below the gate electrode. The lateral insulated gate bipolar transistor according to any one of claims 1 to 8, wherein the channel length L _C of another carrier formed in (1) is 3 times or more.