JPH02275675A - Mos type semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a parasitic transistor from breaking down due to operation of flow of an excess current by providing the same conductivity type region as that of a channel layer in a wide area covering the extended part of a gate film. CONSTITUTION:A P<+> type layer 31 formed by diffusing simultaneously with a p<+> type layer 3 exists at the center of four cells. A source layer is not formed in the P<+> type layer and hence not operated as a FET but a diode is formed with an N<-> type layer 1. It is connected to a source electrode via a contact hole 81 opened at a PSG film 7 on the layer 31. Accordingly, a reverse voltage applied between the layer 1 and the layers 2, 3 via the source electrode is also applied between the layer 1 and the layer 31. When the reverse voltage is raised to break over, a breakover current flows to the diode at the center of the layer 1 to prevent it from flowing to each cell. Thus, it can prevent it from breaking down due to an excess current at the time of breaking over.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a first conductivity type in which a plurality of second conductivity type second regions are arranged vertically and horizontally on the surface of a first conductivity type first region; An annular third region of the first conductivity type is formed on the surface of the channel forming region with a channel forming region remaining between the outer periphery and an insulating film is formed from the surface of the channel forming region to the exposed surface of the first region. For example, a power vertical MOSFET or an insulated gate bipolar transistor (hereinafter referred to as iGBT) has a gate film and one main electrode contacts the surface of the third region and the second region surrounded by it. ) related to MOS type semiconductor devices.

C. Prior art] Figure 2 + a1. (b), tc+ is a power vertical MO
Four cells of an SFET or 1GBT MOS structure are shown, and as shown in the plan view (the mountain in the C-C cross-sectional view of al), one cell provided on the surface of the N-layer 1 is: two layers consisting of a P-channel layer 2 and a P-low resistance layer 3;
A polycrystalline silicon gate film 6 is provided on the channel layer 2 sandwiched between the N source layer 4, the N4 source layer 4, and the N-Jil provided on the surface thereof, with a gate oxide film 5 interposed therebetween. and a PSG film 7 covering the polycrystalline silicon gate film 6. Contact hole 8 made in PSG film 7
The source electrode (not shown) is connected to the P'' layer 3 and the source electrode 1-4.
In this structure, as shown in Figure tc+, which is a cross-sectional view taken along the line D-D of Figure (Al), in the area where there is no MOS cell, the polycrystalline silicon film 6 and the PsG film 7 are all over the oxide film 5. These membranes therefore surround each cell.

[The invention tries to solve i! ! Title]

Gate film 6 of a semiconductor device having a MOS structure as described above
N-Ji below and surrounding 23 layer 3 and P- layer 2
The area between the four cells is larger than the area between the cells arranged vertically and horizontally.

Therefore, 2 layers 2.3 and Nl! ! When the reverse voltage applied between N There is a problem in that a parasitic transistor consisting of the source layer 4P and the channel layer 2°N-1111 operates and causes destruction.

This issue will be discussed in more detail regarding iGBT.

FIG. 3 is a partial cross-sectional view of a conventional iGBT. This I
In the GBT, a Po drain QIO is provided under the N− layer 1 via the N−buff 1 layer 9, and the drain layer 10
The drain 11 pole 11 in contact with the drain 11 and the source electrode 12 in contact with the P" 13 and the source layer 4 in the contact hole 8 face each other as main electrodes. In this iGBT conductive state, electrons are transferred to the source as shown by the dotted line. Po is injected from N4 through the channel layer 2 from the N- layer 1 and the N'' layer 9 into the drain layer 10, and in response, N is injected from the drain layer 10.

Holes are injected into the N-layer 1 through the layer 9 as shown by the solid line, so that the N-layer l undergoes conductivity modulation and has a low resistance. The holes flow in the two layer 2 along the underside of the N source 14. Since the second layer 2 has a relatively low resistance, the potential at point A located at the bottom of the source layer 4 increases due to the excessive flow of holes, and when this value exceeds the junction potential of the PN junction, P[2
The PN junction between N and N114 is forward biased, and as described above, the parasitic NPN transistor is turned on, causing a ruff-up phenomenon, which may lead to destruction of the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS type semiconductor device which solves the above-mentioned problems and prevents damage caused by excessive current during breakover due to non-uniform area between cells.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention has a plurality of second regions of a second conductivity type arranged horizontally and vertically on the surface of a first region of a first conductivity type, and an outer periphery and an outer periphery on the surface of the second region. An annular third region of the first conductivity type is formed with a channel formation region left in between, a gate film is provided from the surface of the channel formation region to the exposed surface of the first region via an insulating film, and In a MOS type semiconductor device in which one of the main electrodes is in contact with the surface of the three regions and the second region surrounded by the three regions, a second conductivity type electrode of the second conductivity type is located in the center of the surface of the first region surrounded by the four second regions. It shall have four areas.

[Effect]

If one main electrode is connected to the fourth region of the second i1 type formed in the center of the region surrounded by the four second 11 regions, the majority carriers in the fourth region will flow from the first region, and the ,
The current flowing from the first region to the second region is reduced. Further, even when the main electrode is not connected, the fourth region narrows the path of the current flowing into the second region, so the current flowing into the second region is reduced. M formed in each of the four second regions
The region surrounded by the O8 structure has a larger area than the region sandwiched between the MOS structures formed in the two adjacent second regions, and when a reverse voltage exceeding the withstand voltage is applied, the region from this region flows into the channel layer. Especially when excessive current flows,
This can be prevented, and a reverse current uniformly flows into the channel layer of each MOS cell from the surroundings.

This makes it difficult for parasitic transistors to operate due to excessive current flow.

〔Example〕

Figure 1 (fat, (bl, [C)] shows an embodiment of the present invention;
Line sectional view, Figure (C) is a BB line sectional view of (al),
Components common to those in FIG. 2 are given the same reference numerals. As can be seen from FIG. 1 (al and tel), there is a P+ layer 31 formed by simultaneous diffusion of the P layer 3 in the center of the four cells.

No source layer is formed in these 20 layers, so F
It does not operate as an ET, but forms a diode with N-1'll. The source electrode (not shown) is P
'' layer 31 through a contact hole 81 made in the PSG film 7. Therefore, the reverse voltage applied between N-111 and the second layer 2.3 by the source electrode is When the reverse voltage applied between layer 1 and layer 2 31 becomes high and causes a breakover, the breakover current flows into this diode located in the center of the wide N-layer 1, preventing it from flowing into each cell. To prevent.

FIG. 4 shows a perspective view of an iGBT according to an embodiment of the present invention;
In FIG. 0, in which parts common to those in FIG.
A contact hole 8 directly below the source electrode 12 is in contact with the source electrode 12.
Or there are 81. The gate film 6 has recesses 21 and 22
．． 21, 23, 22, 24, and below the middle of 23 and 24, respectively. Below the recesses 25.degree. 26, the source electrode 12 is in contact with the 24 layer 31. This i GB
For T, the launch-up capacity has been increased from 30A to 35A.
It improved to ~40A.

FIG. 5 shows an i GBT according to another embodiment of the present invention;
In the plan view of the GBT substrate surface, the region surrounded by the chain line represents one unit having four MOS structures.The source electrode (not shown) is in contact with the P layer 3 and the surrounding N layer 4 through the contact hole 8. However, as in FIGS. 1 and 4, the contact hole 81 located at the center of the four contact holes 8 contacts the 20th layer 31. N°
A channel forming region of channel layer 2 surrounds the outside of layer 5 . N under the gate oxide film outside the channel layer 2
- Layer 1 is exposed. A gate film 6 whose boundaries are indicated by dotted lines 61 and whose regions are indicated by diagonal lines is provided on the insulating film surrounding the contact holes 8 and 81. The gate wiring is in contact with this gate film through a contact hole 82 in a surface protection film covering it.

FIG. 6 shows IC and BT according to still another embodiment of the present invention. What is different from FIG. 5 is that the N
- The P' diffusion layer 32 is formed in the layer 1 at the same time as the P' layer 31. Since this P"7132 is not connected to the source electrode, it is not useful for extracting holes, but it reduces the area of the N- layer 1 and narrows the path of the genuine plate flowing into the channel 1i2, and as a result, the channel layer Holes that enter are restricted, making it difficult for launch-up to occur.By arranging in this way, even if the P diffusion layer 32 is formed, the area of the gate film does not decrease, and the contact with the gate film 6 is made for each unit. The hole 82 can be provided, making it possible to lower the gate resistance.

FIG. 7 shows that without increasing the contact area of the source electrode 12, that is, without increasing the distance between the MOS structures,
An example will be shown in which the area of the P° layer 31 is increased. In this case, the P° layer 31 is formed by entering under the gate film 6 from the edge 61 of the gate film 6 shown by the dotted line. By making the P' layer 31 enter under the gate film 6 in this way, holes flow to the source electrode using the P' layer 2.
It's on.

In addition, the P' layer 3 is located at the corner of the P' layer 2 where the hole current is concentrated.
By arranging one side of 1 to face each other, holes can easily flow into Po[31. Thereby, the launch amplifier durability can be further improved.

Not only the hole current but also the electron current can be suppressed by the P0 diffusion layer 31.32, but by forming the P° layer 31.32 to an appropriate size, the effect of suppressing the electron current can be moderated, The latch-up resistance can be improved without affecting the operating current.

In the iGBT of each example, the N' layer 9N- layer 1 was sequentially formed on the drain layer 10 by an epitaxial method. After forming a P layer 3 on the surface of the N- layer 1, a polycrystalline silicon layer was deposited on the surface with a gate oxide film 5 interposed therebetween, and a window was opened to form a gate Ws6. Using this gate film 6 as a mask, the P-type channel layer 2 was diffused.

After that, using the gate film 6 as a part of the mask again, an N0 source layer 4 is formed, the surface is covered with an insulating film 7, and a hole is made for connection to bring the source electrode 12 into contact. ,
Further, a drain electrode 11 was brought into contact with the P+ layer 10.

The lower the resistance of the P layer 31, 32 provided according to the present invention, the more desirable it is.
．． For each diffusion for the formation of P layer 2, 20 layers 31.3
By doping at point 2, a low resistance P° layer can be obtained.

Note that all of the above embodiments are N-channel IGBTs, but by switching the conductivity types, P-channel IGBTs
It goes without saying that this method can also be implemented in T.

〔Effect of the invention〕

According to the present invention, by providing a region having the same conductivity type as the channel layer in a wide area covered by the extension of the gate film and located in the middle of the channel layer provided with the MO8 structure surrounding the main electrode, the region By connecting the channel to the main electrode and drawing carriers opposite to the carriers flowing through the channel to the main electrode, or by narrowing the passage of the opposite carriers to make it difficult to flow, the parasitic transistor is It was possible to obtain a MOS type semiconductor device which was prevented from being destroyed due to operation and had a high reverse current withstand capacity.

[Brief explanation of drawings]

FIG. 1 shows an MO5 type semiconductor device according to an embodiment of the present invention, (a) is a plan view, (mountain) is a cross-sectional view along A-AvA of (al), and (C1 is fa) B-B A cross-sectional view taken along the !l!jl line, FIG. 2 shows a conventional MOS type semiconductor device.
(5) is a plan view, tllll is a cross-sectional view along the C-C line, fcl is a cross-sectional view of fal along the D-D line,
FIG. 3 is a partial sectional view of a conventional IGBT, FIG. 4 is a partial perspective sectional view of an IGBT according to another embodiment of the present invention, and FIGS. Example [
FIG. 2 is a partial plan view of a GBT semiconductor substrate. 1-N-layer, 2:P-channel layer, 3.31.32:2
3 layers, 4: N source layer 5: gate oxide film, 6: gate film, 'l: PsG film, 8.81.82: 17 tact hole, 10: drain layer, 11: drain electrode, 12
: Source electrode. Figure 1 Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] (1) A plurality of second regions of the second conductivity type are arranged vertically and horizontally on the surface of the first region of the first conductivity type, and a channel formation region is left between the surface of the second region and the outer periphery in an annular shape. A third region of the first conductivity type is formed, a gate film is provided from the surface of the channel forming region to the exposed surface of the first region via an insulating film, and the third region and the second region surrounded by the third region are formed. A MOS type semiconductor in which one of the main electrodes is in contact with the surface of the region, characterized in that a fourth region of the second conductivity type is provided at the center of the surface of the first region surrounded by four second regions. Device.