JP2000294770A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a MOSFET capable of improving its dielectric strength without destroying transistor cells even if surges in the reverse direction are applied instantly in association with inductive loads. SOLUTION: A plurality of p-type body regions 2 are formed in the surface of an n--type semiconductor layer 1 serving as a drain region, and source regions 3 are formed with n-type impurities introduced around each of the regions 2. Gate electrodes 6 are formed on the regions 3 through gate oxide films 5, whereby a plurality of transistor cells T are formed. A source electrode 12 is formed while connected to the regions 2 and 3 of the cells T. Further, at least two p-type diffusion regions 7 and 8 are formed in the surface of the layer 1 independently of the regions 2. The electrode 12 is connected also to the region 7, and the regions 7 and 8 are formed such that the distance (d) between them becomes wider than the distance (a) between the regions 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a MOSFET in which a coil or the like is connected to a load (L load), a MOSFET such as an insulated gate bipolar transistor (IGBT), which has an improved L load resistance between a drain and a source. The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device capable of preventing breakdown of a transistor cell and improving its resistance even when a large surge is applied between a drain and a source due to an L load during switching or the like.

[0002]

2. Description of the Related Art Conventionally, for example, a vertical MOSFET has a high switching speed and is used as a high-output switching device. This vertical MOSFET
For example, as shown in FIG.
^{On the + type} semiconductor substrate 21a, n ^{− as a} drain region
A semiconductor layer (epitaxial growth layer) 21 is epitaxially grown, and a p-type impurity is diffused on the surface side thereof to form a p-type body region 22. An n ^{+ -type} body region is formed on the surface side of the body region (base region) 22. Source region 23 is formed. A gate electrode 25 is provided on an end portion of the body region 22 and a surface side of the semiconductor layer 21 outside the body region 22 via a gate oxide film 24. Then, Al is connected to the source region 23 through the interlayer insulating film 26.
The source electrode 27 is formed by, for example, the semiconductor substrate 21.
The FET portion (transistor cell region) 20 is formed by forming a drain electrode (not shown) on the back surface of “a”.

Further, a gate electrode pad 33 is formed on a p-well 31 formed on the surface of the semiconductor layer 21 via an insulating film 32 next to the cell region. The wiring 35 is provided. p
The well 31 is provided to extend the depletion layer formed between the body region 22 of the transistor cell and the semiconductor layer 21 to increase the withstand voltage between the drain and the source. By forming the body regions 22 in a matrix, many transistor cells are formed, and the sum of the current of each cell becomes a drain current, thereby forming a power MOSFET corresponding to a large current.

In the power MOSFET having this structure, when the distance a between the body region 22 and the p-type region of the p-well 31 exceeds a certain level, as shown in FIG. It is known that the breakdown voltage between the sources decreases. Therefore, for example, when assuring a withstand voltage between the drain and the source of about 600 V, the distance a is set so as to obtain a withstand voltage of about 670 V, and all the p-type regions (the body region 2
2) The distance a is formed to be the same. The rate of reduction in the breakdown voltage varies depending on the shape and impurity concentration of the transistor cell, the desired breakdown voltage, and the like. For example, in a transistor cell having a body region 22 of 15 μm square and a breakdown voltage of about 600 V, the interval is 0.25 μm. As the width increases, the breakdown voltage decreases by about 10V.

[0005]

In a conventional semiconductor device of this type, there is no problem if this level of withstand voltage is present under normal conditions, but in the case of an L load in which a coil or the like is connected to the load, instantaneous switching occurs. However, there is a problem that a large current flows in the opposite direction and the transistor cell is destroyed. Since the breakdown of the transistor cell is particularly likely to occur in a cell near the p-well, conventionally, a transistor cell is not formed near the p-well where a gate electrode pad or a gate finger is provided. Area 2
Although a method is adopted in which a deep p-type diffusion region is doubled in 3 to achieve high breakdown strength, breakdown due to an L load cannot be sufficiently prevented.

In the case of using a technique for reducing the on-resistance by forming a cell into a trench, it is possible to reduce the chip area, but on the contrary, there is a problem that the resistance to an L load or the like must be reduced.

The present invention has been made in order to solve such a problem. Even if a reverse surge is instantaneously applied due to an L load or the like, a portion that partially breaks down is formed. It is an object of the present invention to provide a semiconductor device capable of absorbing a surge and improving the breakdown resistance of the transistor cell without destroying the transistor cell.

[0008]

According to the present invention, there is provided a semiconductor device comprising:
(A) a first conductivity type semiconductor layer serving as a drain region;
(B) a plurality of body regions of the second conductivity type are provided on the surface of the semiconductor layer, and a first conductivity type impurity is introduced around the plurality of body regions to form a source region; And a plurality of transistor cells formed by a gate electrode provided on a surface of the body region sandwiched between the semiconductor layer and a gate oxide film,
(C) at least two second conductivity type diffusion regions formed separately from the body region on the surface of the semiconductor layer of the first conductivity type; and (d) connected to a source region and a body region of the transistor cell. The source electrode is connected to the second conductivity type diffusion region, and the distance between the second conductivity type diffusion regions is wider than the distance between the body regions of the transistor cell. The diffusion region of the second conductivity type is formed in the semiconductor device.

With this structure, when a surge in the reverse direction due to an L load is applied between the drain and the source, the withstand voltage becomes weak in a wide space between the body region and the second conductivity type diffusion region. An avalanche breakdown current of surge flows between the diffusion regions of the second conductivity type which are not transistor cells. Since no diffusion region (source region) of the first conductivity type is formed in the second conductivity type region, a parasitic bipolar transistor cannot be formed. Therefore, the current is not amplified to a large current, only the avalanche breakdown current is required, and the pn junction is not broken.

The second conductivity type diffusion region is provided on a surface of the semiconductor layer near a location where a gate electrode pad and / or a gate finger is provided.
This is preferable because a portion to be broken down can be provided using the p-well under the conventional gate electrode pad or gate finger without substantially affecting the region of the conventional transistor cell.

A region corresponding to the source region of the transistor cell is not formed in the second conductivity type diffusion region.
In addition, a conductive film corresponding to the gate electrode of the transistor cell is provided on the surface of the diffusion region of the second conductivity type via a gate oxide film, without requiring a special mask. The interval between the diffusion regions can be controlled accurately.

The extent that the distance between the second conductivity type diffusion regions is wider than the distance between the body regions of the transistor cells is as follows:
When the thickness is 3 μm or less, the breakdown between the second conductivity type diffusion regions can be surely achieved without significantly lowering the normally required breakdown voltage.

[0013]

Next, a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 1 shows a semiconductor device according to the present invention.
FIG. 5 is a cross-sectional explanatory view of a part of the vertical MOSFET according to the embodiment.
As described above, the first conductivity type (e.g.,
If n ^-Surface of the semiconductor layer 1 of the second conductivity type (p-type).
A plurality of body regions 2 are provided, and each of the plurality
Of the first conductivity type (n-type) around the body region 2
To form a source region 3, and the source region 3
A gate is formed on the surface of the body region 2 sandwiched between the semiconductor layer 1 and the semiconductor layer 1.
The gate electrode 6 is provided via the oxide film 5.
A plurality of transistor cells T are formed. Soshi
The source region 3 and the body region of the transistor cell T.
A source electrode 12 is provided so as to be connected to the region 2. Ma
The semiconductor layer 1 different from the region of the transistor cell T
On the surface, apart from the body region 2, at least two second
Conductive (p-type) diffusion regions 7 and 8 are formed,
The above-mentioned source electrode 1 is also provided in the conductive (p-type) diffusion regions 7 and 8.
2 are connected and the body of the transistor cell T is
The second conductivity type (p-type) diffusion region
The second conductivity type (p) is set such that the distance d between the regions 7 and 8 is increased.
Shape) is characterized in that diffusion regions 7 and 8 are formed.
You.

As shown in FIG. 1, the transistor cell T is formed on the surface of an n ^{− type} semiconductor layer 1 epitaxially grown on an n ^{+ type} semiconductor substrate 1a.
That is, a body region 2 is provided in a matrix by introducing a p-type dopant on the surface side of n ⁻ -type semiconductor layer 1. Since the body region 2 is once diffused with the p-type impurity, the second diffusion region 2a for forming the channel region 4 is further formed therearound using the gate electrode 6 as a mask, as shown in FIG. It is formed in a stepped structure. An n-type impurity is introduced into the outer peripheral portion of body region 2 to form source region 3, and a gate is formed on channel region 4 around body region 2 sandwiched between source region 3 and n ⁻ -type semiconductor layer 1. By providing gate electrode 6 via oxide film 5, a transistor cell T portion is formed. The body region 2 has one side of, for example, about 15 μm, and the interval a is determined by, for example, about 5 μm, which is determined by the specific resistance and the withstand voltage of the semiconductor layer 1. The body regions 2 are provided in a matrix as shown in the plan view of FIG.
Are formed in parallel and a large current can be obtained.
It is an SFET. On the gate electrode 6, an interlayer insulating film 10 made of phosphorus glass or the like is provided, and a contact hole is opened. By providing Al or the like by vacuum evaporation or the like, the source region 3 of each transistor cell T is provided.
And source wiring 12 so as to be connected to body region 2.
Are formed.

Next to the transistor cell T portion, a gate electrode pad 9 (G in FIG. 3) is formed of a polysilicon film made of the same material as the gate electrode 6 via an insulating film 5 similarly to a conventional vertical MOSFET. Have been. On the surface of the semiconductor layer 1 under the gate electrode pad 9, as described above, in order to stabilize the depletion layer in the region of the transistor cell T,
A p-type diffusion region (p-well) 8 is formed. In the example shown in FIG. 1, the p-well 8 is used as one of the p-type diffusion regions different from the body region 2 to be described later, and thus the source wiring 12 is connected to the p-well 8. . Then, similarly to the above-mentioned source wiring 12, the gate wiring 1 is formed via the interlayer insulating film 10 by vacuum deposition of Al or the like.
1 is provided. As shown in FIG. 3, an example of a layout of a plane is shown in FIG. 3. In order to alleviate an increase in resistance due to the polysilicon film to a cell far from the gate electrode pad G, the gate wiring 11 is located far away from the transistor cell. Gate fingers GF that lower the resistance by partially connecting the gate electrodes of T are formed by Al wiring. Under the gate finger GF, a p-type diffusion region is formed similarly to under the gate electrode pad 9. Similarly, a drain electrode (not shown) is formed on the back surface of the semiconductor substrate 1a by vacuum deposition of an electrode metal or the like.

In the present invention, in addition to these, a p-type diffusion region 7 in which the transistor cell T is not formed is formed between the region of the transistor cell T and the p well 8. At least two p-type diffusion regions are formed. In the example shown in FIG. 1, the p-type diffusion region (p-well) 8 formed below the gate electrode pad 9 is used as one of them. Therefore, only one new p-type diffusion region 7 is shown. That is, the p-type diffusion regions 7 and 8
Is provided with a structure in which an n-type impurity is not diffused in the outer peripheral portion, that is, in a state where the source region 3 is not formed, like the body region 2 constituting the transistor cell T. The distance d between the p-type diffusion regions 7 and 8 is
P-type diffusion regions 7 and 8 are formed so as to be larger than interval a between body regions 2 forming transistor cell T. However, the formation of the other gate electrode 6 and the second diffusion region 7a (the region into which the p-type impurity is introduced using the polysilicon film (gate electrode) 6 as a mask), the connection with the source line 12, and the like are performed in the transistor cell T. It is formed similarly to the part. Since p-type region 7 is formed in the same manner as body region 2, it can be formed in the same step as the formation of transistor cell T without providing a special step, and also forms second diffusion region 7a. Accordingly, the distance d between the p-type diffusion regions 7 and 8 can be controlled by the dimension of the patterning of the polysilicon film serving as the gate electrode 6, so that the distance d between the p-type diffusion regions 7 and 8 can be set accurately. Can be.

As described above, the distance d between the p-type diffusion regions 7 and 8 is formed larger than the distance a between the body regions 2 of the transistor cells. However, if the distance d is too large, the drain becomes larger as described above. -Since the breakdown voltage between the sources is weakened, the breakdown voltage is reduced regardless of the L load. Therefore, it is preferable to form the body region 2 so as to be slightly larger than the distance a. Since the desired breakdown voltage varies depending on the structure of the product, the impurity concentration, and the like, the distance d cannot be specified unconditionally. For example, as described above, when the size of the body region 2 is about 15 μm on each side,
When the distance a is about 5 μm, the distance is 0.25.
When it is increased by about μm, the breakdown voltage is reduced by about 10V. On the other hand, for example, MOSFE that guarantees a withstand voltage of about 600 V
Because it is manufactured so that the ability becomes about 670V at T,
Even if the interval d is set so that the breakdown voltage of about 10 to 20 V is lowered, normal operation is not hindered. In other words, the distance a is 3 μm or less than the distance a between the body regions 2, preferably about 2 to 0.2 μm, and more preferably 1 to 0.5 μm.
By setting the distance between the p-type diffusion regions 7 and 8 to be larger than the distance between the body regions 2 by about m, the normal breakdown voltage is not hindered and the semiconductor device can be operated even when a surge due to the L load is applied. Destruction can be prevented.

According to the present invention, when a large power surge in the reverse direction due to, for example, an L load is applied between the drain electrode and the source electrode, the p-type diffusion regions 7, 8 and the n-type semiconductor layer 1 An avalanche breakdown current flows between the source and the drain due to the breakdown of the pn junction between them. In this case, the body region 2 of the transistor cell T portion
A similar pn junction is formed between the semiconductor region 1 and the semiconductor layer 1, and there is a possibility of breakdown, but the body region 2
Is different from the distance d between the p-type diffusion regions 7 and 8. As described above, the wider the distance, the lower the breakdown voltage. now,
Since the interval d between the p-type diffusion regions 7 and 8 is formed to be wider than the interval between the body regions 2, when a breakdown occurs, first, at the pn junction between the p-type diffusion regions 7 and 8, Cause a breakdown. As a result, breakdown occurs at the pn junction between the p-type diffusion region 7 and the p-well 8, and an avalanche breakdown current flows through the p-type diffusion regions 7 and 8. This current is momentary, and when the surge due to the L load disappears, the pn junction returns to a normal state. If an n-type diffusion region is further formed in the p-type diffusion regions 7 and 8 as in the transistor cell T portion, a parasitic bipolar transistor is formed.
Although the current is amplified and becomes very large, the pn junction is destroyed and becomes defective. However, in the present invention, the p-type diffusion region 7,
Since no n-type diffusion region is formed in 8, no parasitic bipolar transistor is formed. Therefore, even if an avalanche breakdown current flows, the semiconductor device does not break down, and as a result, a semiconductor device having a MOSFET that does not break down against an L load can be obtained.

In order to manufacture this semiconductor device, first, for example, the surface of an n ^{+ type} semiconductor substrate 1a has a specific resistance of 0.1 to 0.1.
An n-type semiconductor layer 1 is formed by epitaxial growth with a thickness of about several tens to several tens of micrometers at about several tens of ohm-cm, and a mask is formed on the surface thereof to introduce a p-type impurity to form a transistor cell. A body region 2, a p-type diffusion region 7, and a p-type diffusion region (p-well) 8 forming a well below the gate electrode pad 9 are simultaneously formed. Next, a gate oxide film 5 is formed on the surface of the semiconductor layer 1, and a polysilicon film is formed by, for example, a CVD method. Then, the polysilicon film is patterned to form the gate electrode 6 and the gate electrode pad 9 of the transistor cell T. At this time, patterning is performed so that the size of the polysilicon film on the p-type diffusion region 7 is larger than the size of the gate electrode 6 in the transistor cell T portion, for example, by about 0.5 to 1 μm on one side. Then, a p-type impurity is introduced using the gate electrode 6 as a mask to form a second diffusion region 2 for forming a channel region.
a and 7 a are formed on the surface of the semiconductor layer 1. At this time, a mask is applied to the p-well 8 to prevent diffusion.

Thereafter, a desired resist mask is formed,
By introducing an n-type impurity, a source region 3 is provided in the body region 2 to form a transistor cell T. At this time, a resist mask is provided on the surface of p-type diffusion region 7 so that n-type impurities are not introduced. afterwards,
A PSG film is formed on the entire surface by, for example, a normal pressure CVD method, an interlayer insulating film 10 is formed, and a contact hole is formed.
1 and the like are provided on the entire surface by vacuum evaporation or the like, and are patterned to form the gate wiring 11 and the source wiring 12.
To form At this time, contact holes are provided so that the source wirings 12 are also connected to the p-type diffusion regions 7 and 8.

In the above-described example, the p-type diffusion regions 7 and 8 are formed in the semiconductor layer below the gate electrode pad 9 and in the vicinity thereof.
Although a portion through which an avalanche breakdown current flows is formed, the example shown in FIG. 2 is an example formed on the surface of the semiconductor layer below the source electrode pad S in FIG. As described above, it can be formed in the formation region of the transistor cell T or in the vicinity thereof, or can be formed under the gate finger GF or in the vicinity thereof. Gate finger G
Since a p-type diffusion region is formed under F, a region to be broken down can be formed by forming at least another p-type diffusion region by using the p-type diffusion region.

In the example shown in FIG. 2, three p-type diffusion regions 7 are formed so that the respective intervals are equal to each other. By forming three or more in this way,
When a breakdown occurs, the region through which the current flows becomes twice or more, so that it is difficult to break even with a large current. Therefore, when the power of the surge of the L load is large, it is preferable to increase the number of the p-type diffusion regions 7. However, if the number of the regions is increased, the region of the transistor cell must be reduced or the chip area must be increased. Therefore, the number of the p-type diffusion regions 7 is set according to the purpose of use by balancing the two. In FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

Although each of the above-described examples is an example of a vertical MOSFET, the same applies to an insulated gate bipolar transistor (IGBT) in which a bipolar transistor is further formed in this vertical MOSFET.

[0025]

According to the present invention, M having a large breakdown strength even under an L load can be used without increasing a special manufacturing process.
A semiconductor device having an OSFET can be obtained at low cost. As a result, the reliability is greatly improved.

[Brief description of the drawings]

FIG. 1 is a vertical MOS of one embodiment of a semiconductor device of the present invention.
FIG. 3 is an explanatory cross-sectional view of the FET.

FIG. 2 is a vertical MO according to another embodiment of the semiconductor device of the present invention.
FIG. 3 is an explanatory sectional view of an SFET.

FIG. 3 is an explanatory diagram of an example of a planar layout of a vertical MOSFET.

FIG. 4 is an explanatory view of a cross section of a conventional vertical MOSFET.

FIG. 5 is a diagram showing a relationship between a distance a between p-type regions and a withstand voltage in the structure of FIG. 4;

[Explanation of symbols]

 Reference Signs List 1 n-type semiconductor layer 2 body region 3 source region 6 gate electrode 7 p-type diffusion region 8 p-well (p-type diffusion region) 9 gate electrode pad

Claims (4)

[Claims] 1. A semiconductor layer of a first conductivity type serving as a drain region, and (b) a plurality of body regions of a second conductivity type provided on a surface of the semiconductor layer. A first conductivity type impurity is introduced into the periphery of the body region to form a source region. The source region is formed by a gate electrode provided on the surface of the body region interposed between the source region and the semiconductor layer via a gate oxide film. And (c) at least two second transistors formed separately from the body region on the surface of the semiconductor layer of the first conductivity type.
A diffusion region of a conductivity type, and (d) a source electrode connected to a source region and a body region of the transistor cell, wherein the source electrode is connected to the diffusion region of the second conductivity type, and A semiconductor device in which the second conductivity type diffusion regions are formed such that the distance between the second conductivity type diffusion regions is larger than the distance between the body regions. 2. The semiconductor device according to claim 1, wherein the second conductivity type diffusion region is provided on a surface of the semiconductor layer near a location where a gate electrode pad and / or a gate finger is provided. 3. A region corresponding to a source region of the transistor cell is not formed in the second conductivity type diffusion region, and a surface of the second conductivity type diffusion region is formed on a gate electrode of the transistor cell. 3. The semiconductor device according to claim 1, wherein a corresponding conductive film is provided via a gate oxide film. 4. The semiconductor device according to claim 1, wherein the distance between the second conductivity type diffusion regions is wider than the distance between the body regions of the transistor cells by 3 μm or less.