WO2016046984A1 - Silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device Download PDF

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Publication number
WO2016046984A1
WO2016046984A1 PCT/JP2014/075720 JP2014075720W WO2016046984A1 WO 2016046984 A1 WO2016046984 A1 WO 2016046984A1 JP 2014075720 W JP2014075720 W JP 2014075720W WO 2016046984 A1 WO2016046984 A1 WO 2016046984A1
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Prior art keywords
silicon carbide
insulating layer
type silicon
semiconductor device
layer
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PCT/JP2014/075720
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French (fr)
Japanese (ja)
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俊一 中村
昭彦 菅井
徹人 井上
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新電元工業株式会社
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Priority to JP2015504450A priority Critical patent/JP5784860B1/en
Priority to PCT/JP2014/075720 priority patent/WO2016046984A1/en
Publication of WO2016046984A1 publication Critical patent/WO2016046984A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the present invention relates to a silicon carbide semiconductor device using silicon carbide.
  • the semiconductor device may be destroyed due to the parasitic bipolar transistor operation.
  • a deep P body as described above is disclosed in, for example, Patent Document 1, Patent Document 2, and the like.
  • silicon carbide has a small diffusion coefficient of impurities, a deep P body cannot be formed by diffusing impurities. Further, it is difficult to form a deep P body only by ion implantation. Since it is difficult to form a deep P body as described above, in the silicon carbide semiconductor device, by deepening the P body, the electric field strength applied to the gate insulating film can be reduced, or by deepening the P body. It is difficult to suppress the operation of the parasitic bipolar transistor.
  • Japanese Patent Laid-Open No. 11-330091 Japanese Unexamined Patent Publication No. 63-128757 (see, for example, FIG. 2)
  • the present invention has been made in view of the above points, and provides a silicon carbide semiconductor device having high avalanche resistance as a result of suppressing parasitic bipolar transistor operation in the silicon carbide semiconductor device.
  • a silicon carbide semiconductor device includes: A first conductivity type silicon carbide layer; A plurality of second conductivity type silicon carbide layers provided in the horizontal direction on the first conductivity type silicon carbide layer; A first conductivity type source region formed in the second conductivity type silicon carbide layer; An insulating layer provided on the first conductivity type silicon carbide layer located between adjacent second conductivity type silicon carbide layers; With The insulating layer is located on the second conductivity type silicon carbide layer and the source region, and on the second conductivity type silicon carbide layer, and not on the source region.
  • An insulating layer, A gate electrode is provided in the first insulating layer; No gate electrode is provided in the second insulating layer, In the horizontal direction, the second insulating layer is disposed next to the first insulating layer, Second distance L 2 between the second conductivity type silicon carbide layer located below the second insulating layer, a first distance between the second conductivity type silicon carbide layer located below the first insulating layer It is longer than L 1.
  • the first insulating layer and the second insulating layer may be alternately arranged.
  • the second insulating layer is arranged next to a certain first insulating layer, and another first insulating layer is arranged next to the second insulating layer, and the first insulating layer and the A second insulating layer may be disposed.
  • the thickness obtained by subtracting the thickness of the gate electrode from the thickness of the first insulating layer and the thickness of the second insulating layer may be the same.
  • a plurality of the insulating layers are provided, Each of the horizontal distances between the adjacent insulating layers may be equal.
  • a plurality of the first insulating layer and the second insulating layer are provided, Each of the horizontal distances between the adjacent first insulating layer and the second insulating layer may be equal.
  • the second distance L 2 may be equal to or less than 2 times 1.25 times or more of the first distance L 1.
  • the portion of the second conductivity type silicon carbide layer that contacts the source electrode may have a higher impurity concentration than the portion of the second conductivity type silicon carbide layer that does not contact the source electrode.
  • the impurity concentration in the first conductivity type source region may be higher than the impurity concentration in the first conductivity type silicon carbide layer.
  • the second insulating layer is disposed next to the first insulating layer in the horizontal direction. For this reason, when a large voltage is applied to the silicon carbide semiconductor device, the electric field may be concentrated on the second insulating layer having no gate electrode therein instead of the first insulating layer having the gate electrode provided therein. it can. For this reason, the electric field strength applied to the gate insulating film located below the gate electrode can be relaxed, and a large avalanche resistance can be obtained.
  • FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device according to a first embodiment of the present invention.
  • 2 (a) to 2 (c) are cross-sectional views showing steps of manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention.
  • 3 (a) to 3 (c) are cross-sectional views illustrating steps for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention, and are cross-sectional views illustrating steps subsequent to FIG. 2 (c).
  • FIG. FIG. 4 is an upper plan view of the silicon carbide semiconductor device according to the first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a silicon carbide semiconductor device according to the second embodiment of the present invention.
  • FIG. 6 is an upper plan view of the silicon carbide semiconductor device according to the second embodiment of the present invention.
  • the silicon carbide semiconductor device of the present embodiment is, for example, a planar gate type vertical MOSFET.
  • the planar gate type vertical MOSFET will be described as a silicon carbide semiconductor device.
  • this is merely an example of the semiconductor device, and other devices having a MOS gate such as an insulated gate bipolar transistor (IGBT). It should be noted that it can also be applied to structures.
  • IGBT insulated gate bipolar transistor
  • the silicon carbide semiconductor device of the present embodiment includes a high concentration n-type silicon carbide semiconductor substrate 11 (first conductivity type silicon carbide substrate) and a high concentration n-type silicon carbide semiconductor substrate.
  • a high concentration n-type silicon carbide semiconductor substrate 11 first conductivity type silicon carbide substrate
  • a high concentration n-type silicon carbide semiconductor substrate On the low-concentration n-type silicon carbide layer 12 (corresponding to the “first-conductivity-type silicon carbide layer” in the claims) and the low-concentration n-type silicon carbide layer 12.
  • a low concentration p-type silicon carbide region 13 which is provided in the horizontal direction and constitutes the P body.
  • the silicon carbide semiconductor device of the present embodiment has a high concentration n-type source region 17 formed in the low concentration p-type silicon carbide region 13 (the “first conductivity type source” in the claims). And a high-concentration p-type silicon carbide region 18 formed in the low-concentration p-type silicon carbide region 13.
  • the silicon carbide semiconductor device of the present embodiment includes insulating layers 21 and 22 provided on n-type silicon carbide layer 12 positioned between adjacent p-type silicon carbide regions 13 and 18. Yes. Note that the low-concentration p-type silicon carbide region 13 and the high-concentration p-type silicon carbide region 18 of the present embodiment correspond to the “second conductivity type silicon carbide layer” in the claims.
  • the insulating layers 21 and 22 described above are formed on the plurality of first insulating layers 21 located on the low-concentration p-type silicon carbide region 13 and the n-type source region 17 and on the high-concentration p-type silicon carbide region 18. And a plurality of second insulating layers 22 not located on the source region. That is, the first insulating layer 21 is provided on the n-type silicon carbide layer 12 positioned between the adjacent low-concentration p-type silicon carbide regions 13, while the second insulating layer 22 is adjacent to the adjacent high-concentration silicon carbide region 12. It is provided on the n-type silicon carbide layer 12 located between the p-type silicon carbide regions 18 having a concentration.
  • the gate electrode 31 made of, for example, polysilicon is provided in the first insulating layer 21, but the gate electrode 31 is not provided in the second insulating layer 22.
  • the first insulating layer 21 is disposed next to the second insulating layer 22.
  • the second insulating layer 22 is the first insulating layer 22.
  • the first insulating layer 21 and the second insulating layer 22 are alternately arranged on both sides of the insulating layer 21.
  • each of the distance of the horizontal direction between the adjacent 1st insulating layer 21 and the 2nd insulating layer 22 is equal.
  • positioned next to the 1st insulating layer 21 is not the 1st insulating layer 21 but the 2nd insulating layer 22 on the one side or both sides of the 1st insulating layer 21.
  • the second insulating layer 22 is disposed on one side of the first insulating layer 21.
  • the first insulating layer 21 is disposed on the other side of 21 (see the second embodiment described later).
  • the first insulating layer 21 and the second insulating layer 22 are alternately disposed as in the present embodiment. Will be.
  • a source electrode 32 is provided on the insulating layers 21 and 22, the high-concentration n-type source region 17, and the high-concentration p-type silicon carbide region 18.
  • a drain electrode 36 is provided on the back surface of the high-concentration n-type silicon carbide semiconductor substrate 11.
  • the second distance L 2 between the adjacent p-type silicon carbide regions 18 located below the second insulating layer 22 is equal to the adjacent p-type silicon carbide located below the first insulating layer 21. It is longer than the first distance L 1 between the region 13, and has a L 2> L 1.
  • the thickness obtained by subtracting the thickness of the gate electrode 31 from the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. 1 to 3A to 3C relating to the present embodiment and FIG. 5 relating to the second embodiment, the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. This is because they are merely schematic representations of the arrangement. Actually, the thickness obtained by subtracting the thickness of the gate electrode 31 from the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. In the present embodiment, the width of the first insulating layer 21 and the width of the second insulating layer 22 are the same length.
  • the second distance L 2 between the adjacent p-type silicon carbide regions 18 located below the second insulating layer 22 is equal to the adjacent p-type silicon carbide located below the first insulating layer 21. It is preferable that the first distance L 1 between the regions 13 is, for example, 1.25 times or more and 2 times or less.
  • the portions of p-type silicon carbide regions 13 and 18 that are in contact with source electrode 32 have impurities compared to the portions of p-type silicon carbide regions 13 and 18 that are not in contact with source electrode 32.
  • the concentration is high. That is, the portion of the p-type silicon carbide regions 13 and 18 that contacts the source electrode 32 becomes the high-concentration p-type silicon carbide region 18 and does not contact the source electrode 32 of the p-type silicon carbide regions 13 and 18.
  • the portion is a low-concentration p-type silicon carbide region 13.
  • the impurity concentration in the n-type source region 17 is higher than the impurity concentration in the n-type silicon carbide layer 12.
  • FIG. 4 is an upper plan view of first insulating layer 21 and second insulating layer 22 of the silicon carbide semiconductor device according to the present embodiment as viewed from above. As shown in FIG. 4, in the present embodiment, the first insulating layer 21 and the second insulating layer 22 have a stripe shape. "Manufacturing process"
  • FIGS. 2 (a)-(c) and FIGS. 3 (a)-(c). An example of the manufacturing process of the silicon carbide semiconductor device of the present embodiment having the above-described configuration will be described mainly with reference to FIGS. 2 (a)-(c) and FIGS. 3 (a)-(c). .
  • n-type silicon carbide semiconductor substrate 11 is prepared (see FIG. 2A).
  • a low-concentration n-type silicon carbide layer 12 is formed by epitaxial growth on the high-concentration n-type silicon carbide semiconductor substrate 11 (see FIG. 2A).
  • a mask made of, for example, an oxide film is laminated on the entire surface of the low-concentration n-type silicon carbide layer 12.
  • an opening is provided at a predetermined portion of the mask, and p-type impurity ions are implanted through the opening to form a low-concentration p-type silicon carbide region 13 (see FIG. 2B). ).
  • the low-concentration p-type silicon carbide region 13 is formed in a stripe shape (see FIG. 4), and the p-type silicon carbide region will be located below the second insulating layer 22 to be formed later.
  • second distance L 2 between the 13 is longer than the first distance L 1 between the p-type silicon carbide region 13 to be positioned below the first insulating layer 21 to be later formed.
  • a mask made of, for example, an oxide film is laminated on the entire surface of the low concentration n-type silicon carbide layer 12 and the low concentration p-type silicon carbide region 13.
  • an opening is provided in a predetermined portion of the mask, and p-type impurity ions are implanted through the opening, thereby forming a high-concentration p-type silicon carbide region 18 (FIG. 2C). reference).
  • the high-concentration p-type silicon carbide region 18 is formed in the p-type silicon carbide region 13 located below the second insulating layer 22 and is adjacent to the high-concentration p-type silicon carbide region 18. the distance between the region 18 becomes the second distance L 2.
  • a mask made of an oxide film or the like is laminated on the entire surface of the low-concentration n-type silicon carbide layer 12, the high-concentration p-type silicon carbide region 18, and the low-concentration p-type silicon carbide region 13. .
  • an opening is provided at a predetermined portion of the mask, and n-type impurity ions are implanted through the opening to form a high-concentration n-type source region 17 (see FIG. 2C). ).
  • the high-concentration n-type source region 17 is formed adjacent to the high-concentration p-type silicon carbide region 18.
  • activation annealing is performed in an atmosphere of an inert gas such as argon.
  • an oxide film is formed on the entire surface of the low-concentration n-type silicon carbide layer 12, the high-concentration n-type silicon carbide layer 17 and the high-concentration p-type silicon carbide region 18 shown in FIG. 29 are stacked.
  • polysilicon is stacked on the surface of the oxide film 29, and then patterned to leave only the polysilicon at the location to be the gate electrode 31 (see FIG. 3A).
  • an oxide film is stacked on the entire surface of the oxide film 29 and the gate electrode 31, and then patterned to leave only the oxide film where the first insulating layer 21 and the second insulating layer 22 are disposed (FIG. 3 (b)). Thereby, the first insulating layer 21 and the second insulating layer 22 are formed.
  • a source electrode 32 is laminated on the entire surface of the first insulating layer 21, the second insulating layer 22, the high concentration n-type silicon carbide layer 17 and the high concentration p-type silicon carbide region 18, and the high concentration
  • a drain electrode 36 is provided on the back surface of the n-type silicon carbide semiconductor substrate 11 (see FIG. 3C).
  • a silicon carbide semiconductor device is manufactured as described above.
  • the second distance L 2 between the p-type silicon carbide regions 18 located below the second insulating layer 22 is the p-type carbonized located below the first insulating layer 21. Since it is longer than the first distance L 1 between the silicon regions 13, the number of electric lines of force that flow from below between the p-type silicon carbide regions 18 located below the second insulating layer 22. Is greater than the number of lines of electric force flowing from below between the p-type silicon carbide regions 13 located below the first insulating layer 21. As described above, in the aspect of the present embodiment, breakdown is most likely to occur due to the lines of electric force flowing from below between the p-type silicon carbide regions 18 located below the second insulating layer 22. Become.
  • the high-concentration p-type silicon carbide region 18 located below the second insulating layer 22 is used before the electric field of the gate insulating film 21a below the gate electrode 31 is increased.
  • An avalanche breakdown can occur, and an avalanche current can flow into the source electrode 32 without passing below the n-type source region 17. Therefore, the voltage drop in the low-concentration p-type silicon carbide region 13 due to the avalanche current is reduced, the operation of the parasitic bipolar transistor is suppressed, and the avalanche breakdown resistance can be improved.
  • the electric field strength applied to the gate insulating film 21a below the gate electrode 31 can be relaxed, and the avalanche breakdown resistance can be improved. According to the present embodiment, it is not necessary to narrow the interval between the p-type silicon carbide regions or deepen the p-type silicon carbide regions as in the prior art.
  • the second insulating layer 22 is disposed next to the first insulating layer 21 in the horizontal direction. For this reason, the electric field can be concentrated on the p-type silicon carbide region 18 located below the second insulating layer 22 instead of the p-type silicon carbide region 13 located below the first insulating layer 21.
  • the first insulating layers 21 and the second insulating layers 22 are alternately arranged in the horizontal direction, and the second insulating layers 22 are always arranged on both sides of the first insulating layer 21. It will be.
  • the electric field is more reliably concentrated on the second insulating layer 22 not including the gate electrode 31 instead of the first insulating layer 21 including the gate electrode 31. Can do. Therefore, the electric field strength applied to the gate insulating film 21a can be more reliably alleviated, and the avalanche breakdown resistance can be more reliably improved.
  • the crystal defect region can be reduced, and an increase in leakage current can be suppressed.
  • the second distance L 2 preferably is equal to or less than 2 times 1.25 times the first distance L 1. If the first distance L 1 is assumed to be 2 [mu] m, it is preferable that the second distance L 2 has a 2.5 [mu] m ⁇ 4.0 .mu.m. Second distance when the length and the length of the first distance L 1 L 2 has become too close length, the second insulating layer does not contain a gate electrode 31 instead of the first insulating layer 21 includes a gate electrode 31 The second distance L 2 is preferably 1.25 times or more of the first distance L 1 because the effect of concentrating the electric field on 22 is difficult to obtain.
  • the second distance L 2 is less than twice the first distance L 1.
  • the thickness obtained by subtracting the thickness of the gate electrode 31 from the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. This is a result of forming the first insulating layer 21 and the second insulating layer 22 by the same method as described above. Thus, the manufacturing method can be simplified by forming the first insulating layer 21 and the second insulating layer 22 in the same manner.
  • the horizontal distances between the first insulating layer 21 and the second insulating layer 22 adjacent to each other are equal. For this reason, even if a large voltage is applied to the silicon carbide semiconductor device, the generated electric field can be evenly concentrated on each second insulating layer 22. For this reason, the electric field strength applied to the gate insulating film 21a can be relaxed reliably and without unevenness.
  • the portion that contacts the source electrode 32 is a high-concentration p-type silicon carbide region 18. For this reason, in this high-concentration p-type silicon carbide region 18, sufficient ohmic contact with the source electrode 32 can be obtained. Further, since the impurity concentration in the n-type source region 17 is high, sufficient ohmic contact with the source electrode 32 can be obtained also in the n-type source region 17.
  • the first insulating layer 21 and the second insulating layer 22 are alternately arranged.
  • the second insulating layer 22 is arranged next to a certain first insulating layer 21 in the horizontal direction as described in the second embodiment. A description will be given using a mode in which the first insulating layer 21 and the second insulating layer 22 are arranged at a period in which another first insulating layer 21 is arranged next to the second insulating layer 22.
  • the other configurations are substantially the same as those in the first embodiment.
  • the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • a second insulating layer 22 is disposed next to a certain first insulating layer 21 (for example, the second first insulating layer 21 from the left in FIGS. 5 and 6), and Next to the second insulating layer 22, another first insulating layer 21 (for example, the rightmost first insulating layer 21 in FIGS. 5 and 6) is arranged at a period, and the first insulating layer 21 and the second insulating layer Layer 22 is disposed. That is, the first insulating layer 21, the second insulating layer 22, the first insulating layer 21, the first insulating layer 21, the second insulating layer 22, the first insulating layer 21, and so on are repeated in order from the left. Will be.
  • one second insulating layer 22 is necessarily arranged next to each first insulating layer 21.
  • the electric field can be concentrated on the second insulating layer 22 not including the gate electrode 31 instead of the first insulating layer 21 including the gate electrode 31.
  • the electric field intensity concerning each gate insulating film 21a can be relieved, and it can be expected to improve the avalanche breakdown resistance.
  • the number of second insulating layers 22 can be reduced. As described above, since the gate electrode 31 is not provided in the second insulating layer 22, it becomes a useless region for flowing current. In this regard, according to the present embodiment, since the area occupied by the second insulating layer 22 can be reduced, it is possible to reduce a useless area for flowing current.
  • Silicon carbide semiconductor substrate (first conductivity type silicon carbide substrate) 12 n-type silicon carbide layer (first conductivity type silicon carbide layer) 13 p-type silicon carbide region (second conductivity type silicon carbide layer) 17 n-type source region (source region of first conductivity type) 18 High-concentration p-type silicon carbide region (second conductivity type silicon carbide layer) 21 First insulating layer 21a Gate insulating film 22 Second insulating layer 31 Gate electrode 32 Source electrode 36 Drain electrode

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Abstract

The present invention is provided with: a first conductivity-type silicon carbide layer 12; a plurality of second conductivity-type silicon carbide layers 13 that are provided in the horizontal direction on the first conductivity-type silicon carbide layer 12; and first conductivity-type source regions 17 that are formed in the second conductivity-type silicon carbide layers 13, respectively. On the second conductivity-type silicon carbide layers 13 and the source regions 17, first insulating layers 21 are provided, and in regions, which are on the second conductivity-type silicon carbide layers 13, and are not positioned on the source regions 17, second insulating layers 22 are provided, respectively. In each of the first insulating layers 21, a gate electrode 31 is provided, and in each of the second insulating layers 22, the gate electrode 31 is not provided. In the horizontal direction, the second insulating layers 22 are disposed adjacent to the first insulating layers 21. The second distance L2 between the second conductivity-type silicon carbide layers positioned below the second insulating layers 22 is longer than the first distance L1 between the second conductivity-type silicon carbide layers positioned below the first insulating layers 21.

Description

炭化ケイ素半導体装置Silicon carbide semiconductor device
　本発明は、炭化ケイ素を用いた炭化ケイ素半導体装置に関する。 The present invention relates to a silicon carbide semiconductor device using silicon carbide.
　ＭＯＳＦＥＴを用いてモータ等の誘導性負荷を駆動した場合、定格電圧以上の電圧が半導体装置に印加され、アバランシェ降伏を起こし、半導体装置を破壊してしまうことがある。特に、炭化ケイ素半導体装置では、絶縁破壊強度が高いことから、絶縁膜にかかる電界強度が高くなる。このため、ＳｉＣ－ＭＯＳＦＥＴにおいては、炭化ケイ素半導体装置がアバランシェ降伏を起こす前に、ゲート絶縁膜の絶縁破壊が起こり、半導体装置を破壊してしまうことがある。 When an inductive load such as a motor is driven using a MOSFET, a voltage higher than the rated voltage is applied to the semiconductor device, which may cause avalanche breakdown and destroy the semiconductor device. In particular, since the silicon carbide semiconductor device has high dielectric breakdown strength, the electric field strength applied to the insulating film is high. For this reason, in the SiC-MOSFET, before the silicon carbide semiconductor device undergoes avalanche breakdown, the dielectric breakdown of the gate insulating film may occur and the semiconductor device may be destroyed.
　この点、ゲート絶縁膜にかかる電界を緩和するために、Ｐボディ間の間隔を狭くしたり、Ｐボディを深くしたりすることで、ゲート絶縁膜にかかる電界強度を緩和することが考えられる。 In this respect, in order to relax the electric field applied to the gate insulating film, it is conceivable to reduce the electric field strength applied to the gate insulating film by narrowing the interval between the P bodies or increasing the depth of the P body.
　また、アバランシェ降伏を起こした場合には、寄生バイポーラトランジスタ動作によって半導体装置が破壊されることがある。このような寄生バイポーラトランジスタ動作を防止するために、深いＰボディを形成し、寄生バイポーラトランジスタ動作を抑制することが考えられる。 Also, when an avalanche breakdown occurs, the semiconductor device may be destroyed due to the parasitic bipolar transistor operation. In order to prevent such a parasitic bipolar transistor operation, it is conceivable to form a deep P body to suppress the parasitic bipolar transistor operation.
　なお、上述のように深いＰボディを形成することは、例えば特許文献１、特許文献２等で開示されている。しかしながら、炭化ケイ素は不純物の拡散係数が小さいことから、不純物を拡散することによって深いＰボディを形成することができない。また、イオン注入だけで深いＰボディを形成することは困難である。このように深いＰボディを形成することが困難であることから、炭化ケイ素半導体装置では、Ｐボディを深くすることでゲート絶縁膜にかかる電界強度を緩和することや、Ｐボディを深くすることで寄生バイポーラトランジスタ動作を抑制することが困難なものとなっている。 Note that forming a deep P body as described above is disclosed in, for example, Patent Document 1, Patent Document 2, and the like. However, since silicon carbide has a small diffusion coefficient of impurities, a deep P body cannot be formed by diffusing impurities. Further, it is difficult to form a deep P body only by ion implantation. Since it is difficult to form a deep P body as described above, in the silicon carbide semiconductor device, by deepening the P body, the electric field strength applied to the gate insulating film can be reduced, or by deepening the P body. It is difficult to suppress the operation of the parasitic bipolar transistor.
特開平１１－３３００９１号公報（例えば図１参照）Japanese Patent Laid-Open No. 11-330091 (see, for example, FIG. 1) 特開昭６３－１２８７５７号公報（例えば第２図参照）Japanese Unexamined Patent Publication No. 63-128757 (see, for example, FIG. 2)
　本発明は、このような点を鑑みてなされたものであり、炭化ケイ素半導体装置において寄生バイポーラトランジスタ動作を抑制し、その結果、高いアバランシェ耐量を有する炭化ケイ素半導体装置を提供する。 The present invention has been made in view of the above points, and provides a silicon carbide semiconductor device having high avalanche resistance as a result of suppressing parasitic bipolar transistor operation in the silicon carbide semiconductor device.
　本発明による炭化ケイ素半導体装置は、
　第一導電型炭化ケイ素層と、　　　
　前記第一導電型炭化ケイ素層上に、水平方向で複数設けられた第二導電型炭化ケイ素層と、
　前記第二導電型炭化ケイ素層内に形成された第一導電型のソース領域と、
　隣り合った第二導電型炭化ケイ素層の間に位置する前記第一導電型炭化ケイ素層上に設けられた絶縁層と、
　を備え、
　前記絶縁層が、前記第二導電型炭化ケイ素層及び前記ソース領域上に位置する第一絶縁層と、前記第二導電型炭化ケイ素層上に位置し、前記ソース領域上には位置しない第二絶縁層と、を有し、
　前記第一絶縁層内にゲート電極が設けられ、
　前記第二絶縁層内にはゲート電極が設けられておらず、
　水平方向において、前記第一絶縁層の隣に前記第二絶縁層が配置され、
　前記第二絶縁層の下方に位置する第二導電型炭化ケイ素層の間の第二距離Ｌ２が、前記第一絶縁層の下方に位置する第二導電型炭化ケイ素層の間の第一距離Ｌ１よりも長くなっている。 A silicon carbide semiconductor device according to the present invention includes:
A first conductivity type silicon carbide layer;
A plurality of second conductivity type silicon carbide layers provided in the horizontal direction on the first conductivity type silicon carbide layer;
A first conductivity type source region formed in the second conductivity type silicon carbide layer;
An insulating layer provided on the first conductivity type silicon carbide layer located between adjacent second conductivity type silicon carbide layers;
With
The insulating layer is located on the second conductivity type silicon carbide layer and the source region, and on the second conductivity type silicon carbide layer, and not on the source region. An insulating layer,
A gate electrode is provided in the first insulating layer;
No gate electrode is provided in the second insulating layer,
In the horizontal direction, the second insulating layer is disposed next to the first insulating layer,
Second distance L 2 between the second conductivity type silicon carbide layer located below the second insulating layer, a first distance between the second conductivity type silicon carbide layer located below the first insulating layer It is longer than L 1.
　本発明による炭化ケイ素半導体装置では、
　水平方向において、前記第一絶縁層と前記第二絶縁層とが交互に配置されてもよい。 In the silicon carbide semiconductor device according to the present invention,
In the horizontal direction, the first insulating layer and the second insulating layer may be alternately arranged.
　本発明による炭化ケイ素半導体装置では、
　水平方向において、ある第一絶縁層の隣に前記第二絶縁層が配置され、当該第二絶縁層の隣に別の第一絶縁層が配置されるという周期で、前記第一絶縁層と前記第二絶縁層とが配置されてもよい。 In the silicon carbide semiconductor device according to the present invention,
In the horizontal direction, the second insulating layer is arranged next to a certain first insulating layer, and another first insulating layer is arranged next to the second insulating layer, and the first insulating layer and the A second insulating layer may be disposed.
　本発明による炭化ケイ素半導体装置において、
　前記第一絶縁層の厚みから前記ゲート電極の厚みを差し引いた厚みと前記第二絶縁層の厚みは同じ厚さとなってもよい。 In the silicon carbide semiconductor device according to the present invention,
The thickness obtained by subtracting the thickness of the gate electrode from the thickness of the first insulating layer and the thickness of the second insulating layer may be the same.
　本発明による炭化ケイ素半導体装置において、
　前記絶縁層が複数設けられ、
　隣り合った前記絶縁層の間の水平方向の距離の各々が等しくなってもよい。 In the silicon carbide semiconductor device according to the present invention,
A plurality of the insulating layers are provided,
Each of the horizontal distances between the adjacent insulating layers may be equal.
　本発明による炭化ケイ素半導体装置において、
　前記第一絶縁層及び前記第二絶縁層が複数設けられ、
　隣り合った前記第一絶縁層と前記第二絶縁層との間の水平方向の距離の各々が等しくなってもよい。 In the silicon carbide semiconductor device according to the present invention,
A plurality of the first insulating layer and the second insulating layer are provided,
Each of the horizontal distances between the adjacent first insulating layer and the second insulating layer may be equal.
　本発明による炭化ケイ素半導体装置において、
　前記第二距離Ｌ２は、前記第一距離Ｌ１の１．２５倍以上２倍以下となってもよい。 In the silicon carbide semiconductor device according to the present invention,
The second distance L 2 may be equal to or less than 2 times 1.25 times or more of the first distance L 1.
　本発明による炭化ケイ素半導体装置において、
　前記第二導電型炭化ケイ素層のうち前記ソース電極と接触する部分は、前記第二導電型炭化ケイ素層のうち前記ソース電極と接触しない部分と比較して不純物の濃度が高くなってもよい。 In the silicon carbide semiconductor device according to the present invention,
The portion of the second conductivity type silicon carbide layer that contacts the source electrode may have a higher impurity concentration than the portion of the second conductivity type silicon carbide layer that does not contact the source electrode.
　本発明による炭化ケイ素半導体装置において、
　前記第一導電型のソース領域における不純物の濃度は、前記第一導電型炭化ケイ素層における不純物の濃度よりも高くなってもよい。 In the silicon carbide semiconductor device according to the present invention,
The impurity concentration in the first conductivity type source region may be higher than the impurity concentration in the first conductivity type silicon carbide layer.
　本発明によれば、内部にゲート電極が設けられていない第二絶縁層の下方に位置する第二導電型炭化ケイ素層の間の第二距離Ｌ２が、内部にゲート電極が設けられている第一絶縁層の下方に位置する第二導電型炭化ケイ素層の間の第一距離Ｌ１よりも長くなっている。また、水平方向において、第一絶縁層の隣に第二絶縁層が配置されている。このため、炭化ケイ素半導体装置に大きな電圧が加わったときに、内部にゲート電極が設けられた第一絶縁層ではなく内部にゲート電極が設けられていない第二絶縁層に電界を集中させることができる。このため、ゲート電極の下方に位置するゲート絶縁膜にかかる電界強度を緩和することができ、大きなアバランシェ耐量を得ることができる。 According to the present invention, the second distance L 2 between the second conductivity type silicon carbide layer located below the second insulating layer that no gate electrode is provided therein, a gate electrode is provided inside It is longer than the first distance L 1 between the second conductivity type silicon carbide layer located below the first insulating layer. Further, the second insulating layer is disposed next to the first insulating layer in the horizontal direction. For this reason, when a large voltage is applied to the silicon carbide semiconductor device, the electric field may be concentrated on the second insulating layer having no gate electrode therein instead of the first insulating layer having the gate electrode provided therein. it can. For this reason, the electric field strength applied to the gate insulating film located below the gate electrode can be relaxed, and a large avalanche resistance can be obtained.
図１は、本発明の第１の実施の形態による炭化ケイ素半導体装置の断面図である。FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device according to a first embodiment of the present invention. 図２（ａ）－（ｃ）は、本発明の第１の実施の形態による炭化ケイ素半導体装置を製造する工程を示した断面図である。2 (a) to 2 (c) are cross-sectional views showing steps of manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. 図３（ａ）－（ｃ）は、本発明の第１の実施の形態による炭化ケイ素半導体装置を製造する工程を示した断面図であって、図２（ｃ）以降の工程を示した断面図である。3 (a) to 3 (c) are cross-sectional views illustrating steps for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention, and are cross-sectional views illustrating steps subsequent to FIG. 2 (c). FIG. 図４は、本発明の第１の実施の形態による炭化ケイ素半導体装置の上方平面図である。FIG. 4 is an upper plan view of the silicon carbide semiconductor device according to the first embodiment of the present invention. 図５は、本発明の第２の実施の形態による炭化ケイ素半導体装置の断面図である。FIG. 5 is a cross-sectional view of a silicon carbide semiconductor device according to the second embodiment of the present invention. 図６は、本発明の第２の実施の形態による炭化ケイ素半導体装置の上方平面図である。FIG. 6 is an upper plan view of the silicon carbide semiconductor device according to the second embodiment of the present invention.
第１の実施の形態
《構成》
　以下、本発明に係る炭化ケイ素半導体装置の第１の実施の形態について、図面を参照して説明する。 First Embodiment << Configuration >>
A silicon carbide semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings.
　本実施の形態の炭化ケイ素半導体装置は、例えばプレーナゲート型の縦型ＭＯＳＦＥＴである。以下では、炭化ケイ素半導体装置としてこのプレーナゲート型の縦型ＭＯＳＦＥＴを用いて説明するが、これはあくまでも半導体装置の一例に過ぎず、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）等のＭＯＳゲートを有する他のデバイス構造にも適用することができることには留意が必要である。 The silicon carbide semiconductor device of the present embodiment is, for example, a planar gate type vertical MOSFET. Hereinafter, the planar gate type vertical MOSFET will be described as a silicon carbide semiconductor device. However, this is merely an example of the semiconductor device, and other devices having a MOS gate such as an insulated gate bipolar transistor (IGBT). It should be noted that it can also be applied to structures.
　図１に示すように、本実施の形態の炭化ケイ素半導体装置は、高濃度のｎ型の炭化ケイ素半導体基板１１（第一導電型炭化ケイ素基板）と、高濃度のｎ型の炭化ケイ素半導体基板１１上に形成された低濃度のｎ型の炭化ケイ素層１２（特許請求の範囲の「第一導電型炭化ケイ素層」に対応する。）と、低濃度のｎ型の炭化ケイ素層１２上に、水平方向で複数設けられ、Ｐボディを構成する低濃度のｐ型の炭化ケイ素領域１３と、を備えている。 As shown in FIG. 1, the silicon carbide semiconductor device of the present embodiment includes a high concentration n-type silicon carbide semiconductor substrate 11 (first conductivity type silicon carbide substrate) and a high concentration n-type silicon carbide semiconductor substrate. On the low-concentration n-type silicon carbide layer 12 (corresponding to the “first-conductivity-type silicon carbide layer” in the claims) and the low-concentration n-type silicon carbide layer 12. And a low concentration p-type silicon carbide region 13 which is provided in the horizontal direction and constitutes the P body.
　また、本実施の形態の炭化ケイ素半導体装置は、低濃度のｐ型の炭化ケイ素領域１３内に形成された高濃度のｎ型のソース領域１７（特許請求の範囲の「第一導電型のソース領域」に対応する。）と、低濃度のｐ型の炭化ケイ素領域１３内に形成された高濃度のｐ型の炭化ケイ素領域１８も備えている。また、本実施の形態の炭化ケイ素半導体装置は、隣り合ったｐ型の炭化ケイ素領域１３，１８の間に位置するｎ型の炭化ケイ素層１２上に設けられた絶縁層２１，２２を備えている。なお、本実施の形態の低濃度のｐ型の炭化ケイ素領域１３及び高濃度のｐ型の炭化ケイ素領域１８が、特許請求の範囲の「第二導電型炭化ケイ素層」に対応している。 In addition, the silicon carbide semiconductor device of the present embodiment has a high concentration n-type source region 17 formed in the low concentration p-type silicon carbide region 13 (the “first conductivity type source” in the claims). And a high-concentration p-type silicon carbide region 18 formed in the low-concentration p-type silicon carbide region 13. In addition, the silicon carbide semiconductor device of the present embodiment includes insulating layers 21 and 22 provided on n-type silicon carbide layer 12 positioned between adjacent p-type silicon carbide regions 13 and 18. Yes. Note that the low-concentration p-type silicon carbide region 13 and the high-concentration p-type silicon carbide region 18 of the present embodiment correspond to the “second conductivity type silicon carbide layer” in the claims.
　上述の絶縁層２１，２２は、低濃度のｐ型の炭化ケイ素領域１３及びｎ型のソース領域１７上に位置する複数の第一絶縁層２１と、高濃度のｐ型の炭化ケイ素領域１８上に位置し、ソース領域上には位置しない複数の第二絶縁層２２と、を有している。つまり、第一絶縁層２１は隣り合った低濃度のｐ型の炭化ケイ素領域１３の間に位置するｎ型の炭化ケイ素層１２上に設けられ、他方、第二絶縁層２２は隣り合った高濃度のｐ型の炭化ケイ素領域１８の間に位置するｎ型の炭化ケイ素層１２上に設けられている。 The insulating layers 21 and 22 described above are formed on the plurality of first insulating layers 21 located on the low-concentration p-type silicon carbide region 13 and the n-type source region 17 and on the high-concentration p-type silicon carbide region 18. And a plurality of second insulating layers 22 not located on the source region. That is, the first insulating layer 21 is provided on the n-type silicon carbide layer 12 positioned between the adjacent low-concentration p-type silicon carbide regions 13, while the second insulating layer 22 is adjacent to the adjacent high-concentration silicon carbide region 12. It is provided on the n-type silicon carbide layer 12 located between the p-type silicon carbide regions 18 having a concentration.
　第一絶縁層２１内には例えばポリシリコン等からなるゲート電極３１が設けられているが、第二絶縁層２２内にはゲート電極３１が設けられていない。また、水平方向（図１の左右方向）において、第一絶縁層２１が第二絶縁層２２の隣に配置されており、本実施の形態では、その一例として、第二絶縁層２２が第一絶縁層２１の両隣に配置されており、第一絶縁層２１と第二絶縁層２２とが交互に配置されている。また、本実施の形態では、隣り合った第一絶縁層２１と第二絶縁層２２との間の水平方向の距離の各々が等しくなっている。 The gate electrode 31 made of, for example, polysilicon is provided in the first insulating layer 21, but the gate electrode 31 is not provided in the second insulating layer 22. Further, in the horizontal direction (left-right direction in FIG. 1), the first insulating layer 21 is disposed next to the second insulating layer 22. In the present embodiment, as an example, the second insulating layer 22 is the first insulating layer 22. The first insulating layer 21 and the second insulating layer 22 are alternately arranged on both sides of the insulating layer 21. Moreover, in this Embodiment, each of the distance of the horizontal direction between the adjacent 1st insulating layer 21 and the 2nd insulating layer 22 is equal.
　ところで、本願において、第一絶縁層２１の隣に第二絶縁層２２が配置されるとは、第一絶縁層２１の一側方又は両側方に第一絶縁層２１ではなく第二絶縁層２２が配置されることを意味する。第一絶縁層２１の一側方に第二絶縁層２２が配置されている態様においては、第一絶縁層２１の一側方には第二絶縁層２２が配置されるが、第一絶縁層２１の他側方には第一絶縁層２１が配置されることとなる（後述する第２の実施の形態参照）。他方、第一絶縁層２１の両側方に第二絶縁層２２が配置されている態様においては、例えば本実施の形態のように、第一絶縁層２１と第二絶縁層２２とが交互に配置されることとなる。 By the way, in this application, the 2nd insulating layer 22 being arrange | positioned next to the 1st insulating layer 21 is not the 1st insulating layer 21 but the 2nd insulating layer 22 on the one side or both sides of the 1st insulating layer 21. Means to be placed. In the aspect in which the second insulating layer 22 is disposed on one side of the first insulating layer 21, the second insulating layer 22 is disposed on one side of the first insulating layer 21. The first insulating layer 21 is disposed on the other side of 21 (see the second embodiment described later). On the other hand, in the aspect in which the second insulating layer 22 is disposed on both sides of the first insulating layer 21, for example, the first insulating layer 21 and the second insulating layer 22 are alternately disposed as in the present embodiment. Will be.
　また、絶縁層２１，２２、高濃度のｎ型のソース領域１７及び高濃度のｐ型の炭化ケイ素領域１８上にはソース電極３２が設けられている。また、高濃度のｎ型の炭化ケイ素半導体基板１１の裏面にはドレイン電極３６が設けられている。 A source electrode 32 is provided on the insulating layers 21 and 22, the high-concentration n-type source region 17, and the high-concentration p-type silicon carbide region 18. A drain electrode 36 is provided on the back surface of the high-concentration n-type silicon carbide semiconductor substrate 11.
　また、第二絶縁層２２の下方に位置する隣り合ったｐ型の炭化ケイ素領域１８の間の第二距離Ｌ２は、第一絶縁層２１の下方に位置する隣り合ったｐ型の炭化ケイ素領域１３の間の第一距離Ｌ１よりも長くなっており、Ｌ２＞Ｌ１となっている。 Further, the second distance L 2 between the adjacent p-type silicon carbide regions 18 located below the second insulating layer 22 is equal to the adjacent p-type silicon carbide located below the first insulating layer 21. It is longer than the first distance L 1 between the region 13, and has a L 2> L 1.
　本実施の形態では、第一絶縁層２１の厚みからゲート電極３１の厚みを差し引いた厚みと第二絶縁層２２の厚みは同じ厚さとなっている。なお、本実施の形態に関する図１乃至図３（ａ）－（ｃ）及び第２の実施の形態に関する図５では、第一絶縁層２１の厚みと第二絶縁層２２の厚みが同じ厚みとなっているようにして示されているが、これは、これらの図面が構成の概略を示しているに過ぎないためである。実際には、第一絶縁層２１の厚みからゲート電極３１の厚みを差し引いた厚みと第二絶縁層２２の厚みは同じ厚さとなっている。また、本実施の形態では、第一絶縁層２１の幅と第二絶縁層２２の幅は同じ長さとなっている。 In the present embodiment, the thickness obtained by subtracting the thickness of the gate electrode 31 from the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. 1 to 3A to 3C relating to the present embodiment and FIG. 5 relating to the second embodiment, the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. This is because they are merely schematic representations of the arrangement. Actually, the thickness obtained by subtracting the thickness of the gate electrode 31 from the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. In the present embodiment, the width of the first insulating layer 21 and the width of the second insulating layer 22 are the same length.
　ところで、第二絶縁層２２の下方に位置する隣り合ったｐ型の炭化ケイ素領域１８の間の第二距離Ｌ２は、第一絶縁層２１の下方に位置する隣り合ったｐ型の炭化ケイ素領域１３の間の第一距離Ｌ１の例えば１．２５倍以上２倍以下となっていることが好ましい。 By the way, the second distance L 2 between the adjacent p-type silicon carbide regions 18 located below the second insulating layer 22 is equal to the adjacent p-type silicon carbide located below the first insulating layer 21. It is preferable that the first distance L 1 between the regions 13 is, for example, 1.25 times or more and 2 times or less.
　本実施の形態では、ｐ型の炭化ケイ素領域１３，１８のうちソース電極３２と接触する部分は、ｐ型の炭化ケイ素領域１３，１８のうちソース電極３２と接触しない部分と比較して不純物の濃度が高くなっている。つまり、ｐ型の炭化ケイ素領域１３，１８のうちソース電極３２と接触する部分は高濃度のｐ型の炭化ケイ素領域１８となり、ｐ型の炭化ケイ素領域１３，１８のうちソース電極３２と接触しない部分は低濃度のｐ型の炭化ケイ素領域１３となっている。また、ｎ型のソース領域１７における不純物の濃度は、ｎ型の炭化ケイ素層１２における不純物の濃度よりも高くなっている。 In the present embodiment, the portions of p-type silicon carbide regions 13 and 18 that are in contact with source electrode 32 have impurities compared to the portions of p-type silicon carbide regions 13 and 18 that are not in contact with source electrode 32. The concentration is high. That is, the portion of the p-type silicon carbide regions 13 and 18 that contacts the source electrode 32 becomes the high-concentration p-type silicon carbide region 18 and does not contact the source electrode 32 of the p-type silicon carbide regions 13 and 18. The portion is a low-concentration p-type silicon carbide region 13. Further, the impurity concentration in the n-type source region 17 is higher than the impurity concentration in the n-type silicon carbide layer 12.
　図４は、本実施の形態による炭化ケイ素半導体装置の第一絶縁層２１及び第二絶縁層２２を上方から見た上方平面図である。この図４に示すように、本実施の形態では、第一絶縁層２１及び第二絶縁層２２はストライプ形状となっている。
《製造工程》 FIG. 4 is an upper plan view of first insulating layer 21 and second insulating layer 22 of the silicon carbide semiconductor device according to the present embodiment as viewed from above. As shown in FIG. 4, in the present embodiment, the first insulating layer 21 and the second insulating layer 22 have a stripe shape.
"Manufacturing process"
　次に、上述した構成からなる本実施の形態の炭化ケイ素半導体装置の製造工程の一例について、主に図２（ａ）－（ｃ）及び図３（ａ）－（ｃ）を用いて説明する。 Next, an example of the manufacturing process of the silicon carbide semiconductor device of the present embodiment having the above-described configuration will be described mainly with reference to FIGS. 2 (a)-(c) and FIGS. 3 (a)-(c). .
　まず、高濃度のｎ型の炭化ケイ素半導体基板１１を準備する（図２（ａ）参照）。 First, a high concentration n-type silicon carbide semiconductor substrate 11 is prepared (see FIG. 2A).
　次に、高濃度のｎ型の炭化ケイ素半導体基板１１上に、エピタキシャル成長によって低濃度のｎ型の炭化ケイ素層１２を形成する（図２（ａ）参照）。 Next, a low-concentration n-type silicon carbide layer 12 is formed by epitaxial growth on the high-concentration n-type silicon carbide semiconductor substrate 11 (see FIG. 2A).
　次に、例えば酸化膜等からなるマスクが低濃度のｎ型の炭化ケイ素層１２の表面一面に積層される。次に、このマスクの所定の箇所に開口が設けられ、この開口を介してＰ型不純物イオンを注入することによって低濃度のｐ型の炭化ケイ素領域１３が形成される（図２（ｂ）参照）。なお、この低濃度のｐ型の炭化ケイ素領域１３はストライプ形状で形成されており（図４参照）、後ほど形成される第二絶縁層２２の下方に位置することとなるｐ型の炭化ケイ素領域１３の間の第二距離Ｌ２は、後ほど形成される第一絶縁層２１の下方に位置することとなるｐ型の炭化ケイ素領域１３の間の第一距離Ｌ１よりも長くなっている。このように低濃度のｐ型の炭化ケイ素領域１３が形成されると、その後でマスクが除去される。 Next, a mask made of, for example, an oxide film is laminated on the entire surface of the low-concentration n-type silicon carbide layer 12. Next, an opening is provided at a predetermined portion of the mask, and p-type impurity ions are implanted through the opening to form a low-concentration p-type silicon carbide region 13 (see FIG. 2B). ). The low-concentration p-type silicon carbide region 13 is formed in a stripe shape (see FIG. 4), and the p-type silicon carbide region will be located below the second insulating layer 22 to be formed later. second distance L 2 between the 13 is longer than the first distance L 1 between the p-type silicon carbide region 13 to be positioned below the first insulating layer 21 to be later formed. When the low-concentration p-type silicon carbide region 13 is thus formed, the mask is thereafter removed.
　次に、例えば酸化膜等からなるマスクが低濃度のｎ型の炭化ケイ素層１２及び低濃度のｐ型の炭化ケイ素領域１３の表面一面に積層される。次に、このマスクの所定の箇所に開口が設けられ、この開口を介してｐ型の不純物イオンを注入することによって高濃度のｐ型の炭化ケイ素領域１８が形成される（図２（ｃ）参照）。なお、この高濃度のｐ型の炭化ケイ素領域１８は、第二絶縁層２２の下方に位置することとなるｐ型の炭化ケイ素領域１３に形成され、隣り合った高濃度のｐ型の炭化ケイ素領域１８の間の距離が第二距離Ｌ２となる。このように高濃度のｐ型の炭化ケイ素領域１８が形成されると、その後でマスクが除去される。 Next, a mask made of, for example, an oxide film is laminated on the entire surface of the low concentration n-type silicon carbide layer 12 and the low concentration p-type silicon carbide region 13. Next, an opening is provided in a predetermined portion of the mask, and p-type impurity ions are implanted through the opening, thereby forming a high-concentration p-type silicon carbide region 18 (FIG. 2C). reference). The high-concentration p-type silicon carbide region 18 is formed in the p-type silicon carbide region 13 located below the second insulating layer 22 and is adjacent to the high-concentration p-type silicon carbide region 18. the distance between the region 18 becomes the second distance L 2. When the high-concentration p-type silicon carbide region 18 is thus formed, the mask is removed thereafter.
　次に、例えば酸化膜等からなるマスクが低濃度のｎ型の炭化ケイ素層１２、高濃度のｐ型の炭化ケイ素領域１８及び低濃度のｐ型の炭化ケイ素領域１３の表面一面に積層される。次に、このマスクの所定の箇所に開口が設けられ、この開口を介してｎ型の不純物イオンを注入することによって高濃度のｎ型のソース領域１７が形成される（図２（ｃ）参照）。なお、この高濃度のｎ型のソース領域１７は高濃度のｐ型の炭化ケイ素領域１８に隣接するように形成される。このように高濃度のｎ型のソース領域１７が形成されると、その後でマスクが除去される。 Next, for example, a mask made of an oxide film or the like is laminated on the entire surface of the low-concentration n-type silicon carbide layer 12, the high-concentration p-type silicon carbide region 18, and the low-concentration p-type silicon carbide region 13. . Next, an opening is provided at a predetermined portion of the mask, and n-type impurity ions are implanted through the opening to form a high-concentration n-type source region 17 (see FIG. 2C). ). The high-concentration n-type source region 17 is formed adjacent to the high-concentration p-type silicon carbide region 18. When the high-concentration n-type source region 17 is thus formed, the mask is removed thereafter.
　次に、例えばアルゴン等の不活性ガスの雰囲気内で活性化アニールが行われる。 Next, activation annealing is performed in an atmosphere of an inert gas such as argon.
　次に、図２（ｃ）に示された低濃度のｎ型の炭化ケイ素層１２、高濃度のｎ型の炭化ケイ素層１７及び高濃度のｐ型の炭化ケイ素領域１８の表面一面に酸化膜２９が積層される。 Next, an oxide film is formed on the entire surface of the low-concentration n-type silicon carbide layer 12, the high-concentration n-type silicon carbide layer 17 and the high-concentration p-type silicon carbide region 18 shown in FIG. 29 are stacked.
　次に、ポリシリコンを酸化膜２９の表面に積層し、その後で、パターニングして、ゲート電極３１となる箇所のポリシリコンのみを残す（図３（ａ）参照）。 Next, polysilicon is stacked on the surface of the oxide film 29, and then patterned to leave only the polysilicon at the location to be the gate electrode 31 (see FIG. 3A).
　次に、酸化膜２９及びゲート電極３１の表面一面に酸化膜を積層し、その後で、パターニングして第一絶縁層２１及び第二絶縁層２２が配置される箇所の酸化膜のみを残す（図３（ｂ）参照）。このことによって、第一絶縁層２１及び第二絶縁層２２が形成される。 Next, an oxide film is stacked on the entire surface of the oxide film 29 and the gate electrode 31, and then patterned to leave only the oxide film where the first insulating layer 21 and the second insulating layer 22 are disposed (FIG. 3 (b)). Thereby, the first insulating layer 21 and the second insulating layer 22 are formed.
　次に、第一絶縁層２１、第二絶縁層２２、高濃度のｎ型の炭化ケイ素層１７及び高濃度のｐ型の炭化ケイ素領域１８の表面一面に、ソース電極３２を積層し、高濃度のｎ型の炭化ケイ素半導体基板１１の裏面にドレイン電極３６を設ける（図３（ｃ）参照）。以上のようにして炭化ケイ素半導体装置が製造される。 Next, a source electrode 32 is laminated on the entire surface of the first insulating layer 21, the second insulating layer 22, the high concentration n-type silicon carbide layer 17 and the high concentration p-type silicon carbide region 18, and the high concentration A drain electrode 36 is provided on the back surface of the n-type silicon carbide semiconductor substrate 11 (see FIG. 3C). A silicon carbide semiconductor device is manufactured as described above.
《効果》
　次に、上述した構成からなる本実施の形態によって達成される効果であって、まだ述べていない効果又はとりわけ重要な効果について説明する。 "effect"
Next, effects achieved by the present embodiment having the above-described configuration, which have not yet been described, or particularly important effects will be described.
　理解を助けるために、以下では、電気力線を電流に用いられる用語を用いて説明する。電圧をかけて電気力線がドレイン電極３６側（図１の下側）から流入した場合には、当該電気力線はｐ型の炭化ケイ素領域１３，１８に向かって流れる。そして、ｐ型の炭化ケイ素領域１３，１８が設けられていない箇所の下方から流入した電気力線は、ｐ型の炭化ケイ素領域１３，１８の下方側の角又はｐ型の炭化ケイ素領域１３，１８の側方からｐ型の炭化ケイ素領域１３，１８内に流入される。一般には、炭化ケイ素においては横方向（図１の横方向）に流れる電気力線に対して絶縁破壊が起きやすくなっている。この点、本実施の形態では、第二絶縁層２２の下方に位置するｐ型の炭化ケイ素領域１８の間の第二距離Ｌ２は、第一絶縁層２１の下方に位置するｐ型の炭化ケイ素領域１３の間の第一距離Ｌ１よりも長くなっていることから、第二絶縁層２２の下方に位置するｐ型の炭化ケイ素領域１８の間の下方から流入される電気力線の本数は、第一絶縁層２１の下方に位置するｐ型の炭化ケイ素領域１３の間の下方から流入される電気力線の本数よりも多くなる。以上述べたことから、本実施の形態の態様では、第二絶縁層２２の下方に位置するｐ型の炭化ケイ素領域１８の間の下方から流入される電気力線によって絶縁破壊が最も発生しやすくなる。 To facilitate understanding, the electric field lines will be described below using terms used for current. When electric lines of force flow from the drain electrode 36 side (lower side in FIG. 1) with voltage applied, the electric lines of force flow toward the p-type silicon carbide regions 13 and 18. And the electric lines of force that flowed from below the portion where the p-type silicon carbide regions 13, 18 are not provided are the corners on the lower side of the p-type silicon carbide regions 13, 18, 18 flows into the p-type silicon carbide regions 13, 18 from the side of 18. In general, in silicon carbide, dielectric breakdown tends to occur with respect to the lines of electric force flowing in the lateral direction (lateral direction in FIG. 1). In this regard, in the present embodiment, the second distance L 2 between the p-type silicon carbide regions 18 located below the second insulating layer 22 is the p-type carbonized located below the first insulating layer 21. Since it is longer than the first distance L 1 between the silicon regions 13, the number of electric lines of force that flow from below between the p-type silicon carbide regions 18 located below the second insulating layer 22. Is greater than the number of lines of electric force flowing from below between the p-type silicon carbide regions 13 located below the first insulating layer 21. As described above, in the aspect of the present embodiment, breakdown is most likely to occur due to the lines of electric force flowing from below between the p-type silicon carbide regions 18 located below the second insulating layer 22. Become.
　このため、本実施の形態によれば、ゲート電極３１の下方のゲート絶縁膜２１ａの電界が高くなる前に、第二絶縁層２２の下方に位置する高濃度のｐ型の炭化ケイ素領域１８でアバランシェ降伏を起こさせることができ、アバランシェ電流をｎ型のソース領域１７の下方を通らずにソース電極３２に流れ込ませることができる。このため、アバランシェ電流による低濃度のｐ型の炭化ケイ素領域１３での電圧降下が小さくなり、寄生バイポーラトランジスタの動作が抑制され、アバランシェ破壊耐量を向上させることができる。このように、本実施の形態によれば、ゲート電極３１の下方のゲート絶縁膜２１ａにかかる電界強度を緩和することができ、アバランシェ破壊耐量を向上させることができる。なお、本実施の形態によれば、従来技術のようにｐ型の炭化ケイ素領域の間隔を狭くしたりｐ型の炭化ケイ素領域を深くしたりする、必要がない。 Therefore, according to the present embodiment, before the electric field of the gate insulating film 21a below the gate electrode 31 is increased, the high-concentration p-type silicon carbide region 18 located below the second insulating layer 22 is used. An avalanche breakdown can occur, and an avalanche current can flow into the source electrode 32 without passing below the n-type source region 17. Therefore, the voltage drop in the low-concentration p-type silicon carbide region 13 due to the avalanche current is reduced, the operation of the parasitic bipolar transistor is suppressed, and the avalanche breakdown resistance can be improved. Thus, according to the present embodiment, the electric field strength applied to the gate insulating film 21a below the gate electrode 31 can be relaxed, and the avalanche breakdown resistance can be improved. According to the present embodiment, it is not necessary to narrow the interval between the p-type silicon carbide regions or deepen the p-type silicon carbide regions as in the prior art.
　また、本実施の形態では、水平方向において、第一絶縁層２１の隣に第二絶縁層２２が配置されている。このため、第一絶縁層２１の下方に位置するｐ型の炭化ケイ素領域１３ではなく第二絶縁層２２の下方に位置するｐ型の炭化ケイ素領域１８に電界を集中させることができる。特に本実施の形態では、水平方向において、第一絶縁層２１と第二絶縁層２２とが交互に配置されており、第一絶縁層２１の両隣には必ず第二絶縁層２２が配置されることとなる。このため、炭化ケイ素半導体装置に大きな電圧が加わった際に、ゲート電極３１が含まれる第一絶縁層２１ではなくゲート電極３１が含まれない第二絶縁層２２に電界をより確実に集中させることができる。したがって、ゲート絶縁膜２１ａにかかる電界強度をより確実に緩和することができ、アバランシェ破壊耐量をより確実に向上させることができる。 In the present embodiment, the second insulating layer 22 is disposed next to the first insulating layer 21 in the horizontal direction. For this reason, the electric field can be concentrated on the p-type silicon carbide region 18 located below the second insulating layer 22 instead of the p-type silicon carbide region 13 located below the first insulating layer 21. Particularly in the present embodiment, the first insulating layers 21 and the second insulating layers 22 are alternately arranged in the horizontal direction, and the second insulating layers 22 are always arranged on both sides of the first insulating layer 21. It will be. For this reason, when a large voltage is applied to the silicon carbide semiconductor device, the electric field is more reliably concentrated on the second insulating layer 22 not including the gate electrode 31 instead of the first insulating layer 21 including the gate electrode 31. Can do. Therefore, the electric field strength applied to the gate insulating film 21a can be more reliably alleviated, and the avalanche breakdown resistance can be more reliably improved.
　また、本実施の形態によれば、既に述べたように従来技術のようにｐ型の炭化ケイ素領域を深くする必要がないので、ゲート絶縁膜２１ａの下方に形成されるＪＦＥＴ構造（ジャンクションＦＥＴ構造）によるオン抵抗の増加を抑制することができ、オン抵抗を小さくすることができる。 Further, according to the present embodiment, as already described, it is not necessary to deepen the p-type silicon carbide region as in the prior art, so that a JFET structure (junction FET structure) formed below the gate insulating film 21a. ) Can be suppressed, and the on-resistance can be reduced.
　また、このようにｐ型の炭化ケイ素領域を深くする必要がないので、ｐ型不純物イオンを打ち込むために大きなエネルギーを必要としない。このため、本実施の形態によれば、結晶欠陥領域を少なくすることができ、リーク電流の増大を抑えることができる。 Also, since it is not necessary to deepen the p-type silicon carbide region in this way, no large energy is required to implant p-type impurity ions. For this reason, according to the present embodiment, the crystal defect region can be reduced, and an increase in leakage current can be suppressed.
　ちなみに、第二距離Ｌ２は第一距離Ｌ１の１．２５倍以上２倍以下となっていることが好ましい。仮に第一距離Ｌ１が２μｍであるとすると、第二距離Ｌ２は２．５μｍ～４．０μｍとなっていることが好ましい。第二距離Ｌ２の長さと第一距離Ｌ１の長さがあまりに近い長さとなっていると、ゲート電極３１が含まれる第一絶縁層２１ではなくゲート電極３１が含まれない第二絶縁層２２に電界を集中させるという効果を得にくいことから第二距離Ｌ２は第一距離Ｌ１の１．２５倍以上であることが好ましい。他方、第二距離Ｌ２の長さを長くすると必然的に第二絶縁層２２の幅を長くする必要がある。この点、第二絶縁層２２にはゲート電極３１が設けられないことから、電流を流すうえでは無駄な領域となる。したがって、第二絶縁層２２が占める領域の大きさは極力抑える方がよく、第二距離Ｌ２は第一距離Ｌ１の２倍以下であることが好ましい。 Incidentally, the second distance L 2 preferably is equal to or less than 2 times 1.25 times the first distance L 1. If the first distance L 1 is assumed to be 2 [mu] m, it is preferable that the second distance L 2 has a 2.5 [mu] m ~ 4.0 .mu.m. Second distance when the length and the length of the first distance L 1 L 2 has become too close length, the second insulating layer does not contain a gate electrode 31 instead of the first insulating layer 21 includes a gate electrode 31 The second distance L 2 is preferably 1.25 times or more of the first distance L 1 because the effect of concentrating the electric field on 22 is difficult to obtain. On the other hand, it is necessary to increase the width of the second distance L 2 Increasing the length inevitably second insulating layer 22. In this respect, since the gate electrode 31 is not provided in the second insulating layer 22, the second insulating layer 22 becomes a useless region for current flow. Therefore, the size of the region where the second insulating layer 22 is occupied is better to minimize, it is preferable that the second distance L 2 is less than twice the first distance L 1.
　また、本実施の形態では、第一絶縁層２１の厚みからゲート電極３１の厚みを差し引いた厚みと第二絶縁層２２の厚みは同じ厚さとなっている。これは、上述したように、第一絶縁層２１と第二絶縁層２２を同様の手法によって形成した結果である。このように第一絶縁層２１と第二絶縁層２２を同様の手法によって形成することによって、製造方法を簡便にすることができる。 In the present embodiment, the thickness obtained by subtracting the thickness of the gate electrode 31 from the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. This is a result of forming the first insulating layer 21 and the second insulating layer 22 by the same method as described above. Thus, the manufacturing method can be simplified by forming the first insulating layer 21 and the second insulating layer 22 in the same manner.
　また、本実施の形態では、隣り合った第一絶縁層２１と第二絶縁層２２との間の水平方向の距離の各々が等しくなっている。このため、炭化ケイ素半導体装置に大きな電圧が加わっても、発生した電界を均等に各第二絶縁層２２に集中させることができる。このため、ムラ無く確実に、ゲート絶縁膜２１ａにかかる電界強度を緩和することができる。 In the present embodiment, the horizontal distances between the first insulating layer 21 and the second insulating layer 22 adjacent to each other are equal. For this reason, even if a large voltage is applied to the silicon carbide semiconductor device, the generated electric field can be evenly concentrated on each second insulating layer 22. For this reason, the electric field strength applied to the gate insulating film 21a can be relaxed reliably and without unevenness.
　また、本実施の形態では、ソース電極３２と接触する部分は高濃度のｐ型の炭化ケイ素領域１８となっている。このため、この高濃度のｐ型の炭化ケイ素領域１８において、ソース電極３２とのオーミック接触を十分に取ることができる。また、ｎ型のソース領域１７における不純物の濃度が高くなっていることから、ｎ型のソース領域１７においても、ソース電極３２とのオーミック接触を十分に取ることができる。 In the present embodiment, the portion that contacts the source electrode 32 is a high-concentration p-type silicon carbide region 18. For this reason, in this high-concentration p-type silicon carbide region 18, sufficient ohmic contact with the source electrode 32 can be obtained. Further, since the impurity concentration in the n-type source region 17 is high, sufficient ohmic contact with the source electrode 32 can be obtained also in the n-type source region 17.
第２の実施の形態
　次に、主に図５及び図６を用いて、本発明の第２の実施の形態について説明する。 Second Embodiment Next, a second embodiment of the present invention will be described mainly with reference to FIGS.
　第１の実施の形態では、水平方向において、第一絶縁層２１の隣に第二絶縁層２２が配置されていることの一例として、第一絶縁層２１と第二絶縁層２２とが交互に配置される態様を用いて説明したが、第２の実施の形態では、図５及び図６に示すように、水平方向において、ある第一絶縁層２１の隣に第二絶縁層２２が配置され、当該第二絶縁層２２の隣に別の第一絶縁層２１が配置されるという周期で、第一絶縁層２１と第二絶縁層２２とが配置される態様を用いて説明する。 In the first embodiment, as an example in which the second insulating layer 22 is disposed next to the first insulating layer 21 in the horizontal direction, the first insulating layer 21 and the second insulating layer 22 are alternately arranged. In the second embodiment, the second insulating layer 22 is arranged next to a certain first insulating layer 21 in the horizontal direction as described in the second embodiment. A description will be given using a mode in which the first insulating layer 21 and the second insulating layer 22 are arranged at a period in which another first insulating layer 21 is arranged next to the second insulating layer 22.
　第２の実施の形態において、その他の構成は、第１の実施の形態と略同一の態様となっている。第２の実施の形態において、第１の実施の形態と同一部分には同一符号を付して詳細な説明は省略する。 In the second embodiment, the other configurations are substantially the same as those in the first embodiment. In the second embodiment, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
　本実施の形態でも、第１の実施の形態と同様の効果を奏することができる。第１の実施の形態で詳細に説明したことから、本実施の形態における効果の説明は固有な部分に留める。 Also in this embodiment, the same effects as in the first embodiment can be obtained. Since it has been described in detail in the first embodiment, the description of the effects in this embodiment will be limited to a specific part.
　本実施の形態では、水平方向において、ある第一絶縁層２１（例えば図５及び図６の左から２つ目の第一絶縁層２１）の隣に第二絶縁層２２が配置され、当該第二絶縁層２２の隣に別の第一絶縁層２１（例えば図５及び図６の最も右に位置する第一絶縁層２１）が配置されるという周期で、第一絶縁層２１と第二絶縁層２２とが配置される。つまり、以降、左から順番に、第一絶縁層２１、第二絶縁層２２、第一絶縁層２１、第一絶縁層２１、第二絶縁層２２、第一絶縁層２１、・・・と繰り返されることとなる。このため、各第一絶縁層２１の隣には必ず一つの第二絶縁層２２が配置されることとなる。この結果、炭化ケイ素半導体装置に大きな電圧が加わった際に、ゲート電極３１が含まれる第一絶縁層２１ではなくゲート電極３１が含まれない第二絶縁層２２に電界を集中させることができる。このため、各ゲート絶縁膜２１ａにかかる電界強度を緩和することができ、アバランシェ破壊耐量を向上させることを期待することができる。 In the present embodiment, in the horizontal direction, a second insulating layer 22 is disposed next to a certain first insulating layer 21 (for example, the second first insulating layer 21 from the left in FIGS. 5 and 6), and Next to the second insulating layer 22, another first insulating layer 21 (for example, the rightmost first insulating layer 21 in FIGS. 5 and 6) is arranged at a period, and the first insulating layer 21 and the second insulating layer Layer 22 is disposed. That is, the first insulating layer 21, the second insulating layer 22, the first insulating layer 21, the first insulating layer 21, the second insulating layer 22, the first insulating layer 21, and so on are repeated in order from the left. Will be. For this reason, one second insulating layer 22 is necessarily arranged next to each first insulating layer 21. As a result, when a large voltage is applied to the silicon carbide semiconductor device, the electric field can be concentrated on the second insulating layer 22 not including the gate electrode 31 instead of the first insulating layer 21 including the gate electrode 31. For this reason, the electric field intensity concerning each gate insulating film 21a can be relieved, and it can be expected to improve the avalanche breakdown resistance.
　また、本実施の形態によれば第二絶縁層２２の数を減らすことができる。上述したように、第二絶縁層２２にはゲート電極３１が設けられないことから、電流を流すうえでは無駄な領域となる。この点、本実施の形態によれば、第二絶縁層２２の占める領域を小さくすることができるので、電流を流すうえで無駄な領域を減らすことができる。 Further, according to the present embodiment, the number of second insulating layers 22 can be reduced. As described above, since the gate electrode 31 is not provided in the second insulating layer 22, it becomes a useless region for flowing current. In this regard, according to the present embodiment, since the area occupied by the second insulating layer 22 can be reduced, it is possible to reduce a useless area for flowing current.
　最後になったが、上述した各実施の形態の記載及び図面の開示は、特許請求の範囲に記載された発明を説明するための一例に過ぎず、上述した実施の形態の記載又は図面の開示によって特許請求の範囲に記載された発明が限定されることはない。 Lastly, the description of the embodiments and the disclosure of the drawings described above are merely examples for explaining the invention described in the claims, and the description of the embodiments or the disclosure of the drawings described above is included. The invention described in the scope of claims is not limited by this.
１１　　　　炭化ケイ素半導体基板（第一導電型炭化ケイ素基板）
１２　　　　ｎ型の炭化ケイ素層（第一導電型炭化ケイ素層）
１３　　　　ｐ型の炭化ケイ素領域（第二導電型炭化ケイ素層）
１７　　　　ｎ型のソース領域（第一導電型のソース領域）
１８　　　　高濃度のｐ型の炭化ケイ素領域（第二導電型炭化ケイ素層）
２１　　　　第一絶縁層
２１ａ　　　ゲート絶縁膜
２２　　　　第二絶縁層
３１　　　　ゲート電極
３２　　　　ソース電極
３６　　　　ドレイン電極 11 Silicon carbide semiconductor substrate (first conductivity type silicon carbide substrate)
12 n-type silicon carbide layer (first conductivity type silicon carbide layer)
13 p-type silicon carbide region (second conductivity type silicon carbide layer)
17 n-type source region (source region of first conductivity type)
18 High-concentration p-type silicon carbide region (second conductivity type silicon carbide layer)
21 First insulating layer 21a Gate insulating film 22 Second insulating layer 31 Gate electrode 32 Source electrode 36 Drain electrode

Claims (9)

  1. 　第一導電型炭化ケイ素層と、　　　　　　　　　　
    　前記第一導電型炭化ケイ素層上に、水平方向で複数設けられた第二導電型炭化ケイ素層と、
    　前記第二導電型炭化ケイ素層内に形成された第一導電型のソース領域と、
    　隣り合った第二導電型炭化ケイ素層の間に位置する前記第一導電型炭化ケイ素層上に設けられた絶縁層と、
    　を備え、
    　前記絶縁層は、前記第二導電型炭化ケイ素層及び前記ソース領域上に位置する第一絶縁層と、前記第二導電型炭化ケイ素層上に位置し、前記ソース領域上には位置しない第二絶縁層と、を有し、
    　前記第一絶縁層内にゲート電極が設けられ、
    　前記第二絶縁層内にはゲート電極が設けられておらず、
    　水平方向において、前記第一絶縁層の隣に前記第二絶縁層が配置され、
    　前記第二絶縁層の下方に位置する第二導電型炭化ケイ素層の間の第二距離Ｌ２は、前記第一絶縁層の下方に位置する第二導電型炭化ケイ素層の間の第一距離Ｌ１よりも長くなっていることを特徴とする炭化ケイ素半導体装置。     A first conductivity type silicon carbide layer;
    A plurality of second conductivity type silicon carbide layers provided in the horizontal direction on the first conductivity type silicon carbide layer;
    A first conductivity type source region formed in the second conductivity type silicon carbide layer;
    An insulating layer provided on the first conductivity type silicon carbide layer located between adjacent second conductivity type silicon carbide layers;
    With
    The insulating layer is positioned on the second conductivity type silicon carbide layer and the source region, and on the second conductivity type silicon carbide layer and not on the source region. An insulating layer,
    A gate electrode is provided in the first insulating layer;
    No gate electrode is provided in the second insulating layer,
    In the horizontal direction, the second insulating layer is disposed next to the first insulating layer,
    Second distance L 2 between the second conductivity type silicon carbide layer located below the second insulating layer, the first distance between the second conductivity type silicon carbide layer located below the first insulating layer silicon carbide semiconductor device which is characterized in that is longer than L 1.
  2. 　水平方向において、前記第一絶縁層と前記第二絶縁層とが交互に配置されることを特徴とする請求項１に記載の炭化ケイ素半導体装置。 2. The silicon carbide semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are alternately arranged in a horizontal direction.
  3. 　水平方向において、ある第一絶縁層の隣に前記第二絶縁層が配置され、当該第二絶縁層の隣に別の第一絶縁層が配置されるという周期で、前記第一絶縁層と前記第二絶縁層とが配置されることを特徴とする請求項１に記載の炭化ケイ素半導体装置。 In the horizontal direction, the second insulating layer is arranged next to a certain first insulating layer, and another first insulating layer is arranged next to the second insulating layer, and the first insulating layer and the The silicon carbide semiconductor device according to claim 1, further comprising a second insulating layer.
  4. 　前記第一絶縁層の厚みから前記ゲート電極の厚みを差し引いた厚みと前記第二絶縁層の厚みは同じ厚さとなっていることを特徴とする請求項１乃至３のいずれか１項に記載の炭化ケイ素半導体装置。 4. The thickness according to claim 1, wherein a thickness obtained by subtracting a thickness of the gate electrode from a thickness of the first insulating layer is equal to a thickness of the second insulating layer. 5. Silicon carbide semiconductor device.
  5. 　前記絶縁層が複数設けられ、
    　隣り合った前記絶縁層の間の水平方向の距離の各々が等しくなっていることを特徴とする請求項１乃至４のいずれか１項に記載の炭化ケイ素半導体装置。     A plurality of the insulating layers are provided,
    5. The silicon carbide semiconductor device according to claim 1, wherein horizontal distances between the adjacent insulating layers are equal to each other.
  6. 　前記第一絶縁層及び前記第二絶縁層が複数設けられ、
    　隣り合った前記第一絶縁層と前記第二絶縁層との間の水平方向の距離の各々が等しくなっていることを特徴とする請求項２に記載の炭化ケイ素半導体装置。     A plurality of the first insulating layer and the second insulating layer are provided,
    3. The silicon carbide semiconductor device according to claim 2, wherein each of horizontal distances between the adjacent first insulating layer and the second insulating layer is equal. 4.
  7. 　前記第二距離Ｌ２は、前記第一距離Ｌ１の１．２５倍以上２倍以下となっていることを特徴とする請求項１乃至６のいずれか１項に記載の炭化ケイ素半導体装置。 The second distance L 2 is a silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that is equal to or less than 2 times 1.25 times or more of the first distance L 1.
  8. 　前記第二導電型炭化ケイ素層のうち前記ソース電極と接触する部分は、前記第二導電型炭化ケイ素層のうち前記ソース電極と接触しない部分と比較して不純物の濃度が高くなっていることを特徴とする請求項１乃至７のいずれか１項に記載の炭化ケイ素半導体装置。 The portion of the second conductivity type silicon carbide layer that contacts the source electrode has a higher impurity concentration than the portion of the second conductivity type silicon carbide layer that does not contact the source electrode. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is a silicon carbide semiconductor device.
  9. 　前記第一導電型のソース領域における不純物の濃度は、前記第一導電型炭化ケイ素層における不純物の濃度よりも高くなっていることを特徴とする請求項１乃至８のいずれか１項に記載の炭化ケイ素半導体装置。 The impurity concentration in the first conductivity type source region is higher than the impurity concentration in the first conductivity type silicon carbide layer, according to any one of claims 1 to 8. Silicon carbide semiconductor device.
PCT/JP2014/075720 2014-09-26 2014-09-26 Silicon carbide semiconductor device WO2016046984A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02281662A (en) * 1989-04-21 1990-11-19 Mitsubishi Electric Corp Semiconductor device
JPH04767A (en) * 1990-04-02 1992-01-06 Fuji Electric Co Ltd Mos semiconductor element
JP2000294770A (en) * 1999-04-09 2000-10-20 Rohm Co Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02281662A (en) * 1989-04-21 1990-11-19 Mitsubishi Electric Corp Semiconductor device
JPH04767A (en) * 1990-04-02 1992-01-06 Fuji Electric Co Ltd Mos semiconductor element
JP2000294770A (en) * 1999-04-09 2000-10-20 Rohm Co Ltd Semiconductor device

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