JP6338134B2 - Silicon carbide vertical MOSFET and manufacturing method thereof - Google Patents
Silicon carbide vertical MOSFET and manufacturing method thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 21
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims description 177
- 239000004065 semiconductor Substances 0.000 claims description 108
- 239000000758 substrate Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 11
- 239000002344 surface layer Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- -1 aluminum ions Chemical class 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Description
本発明は、縦型ＭＯＳＦＥＴ及びその製造方法に関し、特に、素子耐圧向上とオン抵抗低減の両立を実現する縦型ＭＯＳＦＥＴの構造及びその製造方法に関する。 The present invention relates to a vertical MOSFET and a manufacturing method thereof, and more particularly, to a structure of a vertical MOSFET that realizes both improvement of device breakdown voltage and reduction of on-resistance and a manufacturing method thereof.
炭化珪素（以後、「ＳｉＣ」ともいう。）によるスイッチングデバイスであるＮチャネルのＭＯＳＦＥＴは、一例として、つぎのような手順で製造される。なお、この例では、第１の導電型をｎ型、第２の導電型をｐ型とし、高濃度を＋（プラス）、これに比べて低濃度を無印で示している。
（１）高濃度のｎ+型ＳｉＣ基板の表面に、低濃度のｎ型ＳｉＣ層（ｎ-耐圧領域 ドリフト層）がエピタキシャル成長により形成され、そのｎ型ＳｉＣ層の表面に、さらに複数のｐ+型領域が選択的に形成される。
（２）各ｐ+型領域の表面には、ｎ+型ソース領域とｐ型コンタクト領域が複数形成され、ｎ+型ソース領域とｐ型コンタクト領域との表面にソース電極が形成される。
（３）ｎ+型ソース領域の間のｐ型コンタクト領域と、ｎ型ＳｉＣ層表面にゲート絶縁膜を介してゲート電極が形成され、また、ｎ+型ＳｉＣ基板の裏面側にはドレイン電極が形成される。
An N-channel MOSFET which is a switching device made of silicon carbide (hereinafter also referred to as “SiC”) is manufactured by the following procedure as an example. In this example, the first conductivity type is n-type, the second conductivity type is p-type, the high concentration is + (plus), and the low concentration is not marked.
(1) A low-concentration n-type SiC layer (n − breakdown voltage region drift layer) is formed by epitaxial growth on the surface of a high-concentration n + -type SiC substrate, and a plurality of p + is further formed on the surface of the n-type SiC layer. A mold region is selectively formed.
(2) A plurality of n + type source regions and p type contact regions are formed on the surface of each p + type region, and a source electrode is formed on the surface of the n + type source region and the p type contact region.
(3) A gate electrode is formed on the p-type contact region between the n + -type source region and the n-type SiC layer via a gate insulating film, and a drain electrode is formed on the back side of the n + -type SiC substrate. It is formed.
こうしたＮチャネルのＳｉＣ―ＭＯＳＦＥＴは、高耐圧であることが知られているが、下記特許文献１には、こうしたＮチャネルのＳｉＣ―ＭＯＳＦＥＴのオン抵抗を低減するための製造方法が提案されている。
第１図は、この先行技術における炭化ケイ素縦型ＭＯＳＦＥＴの単位セルを説明するための模式断面図である。
Such an N-channel SiC-MOSFET is known to have a high breakdown voltage, but the following
FIG. 1 is a schematic cross-sectional view for explaining a unit cell of a silicon carbide vertical MOSFET in this prior art.
第１図において、窒素がドーピングされた（０００１）面を有する高濃度ｎ+型基板ａ表面上には、たとえば、窒素がドーピングされた、基板ａより低濃度のｎ型ドリフト層ｂが堆積されている。この低濃度ｎ型ドリフト層ｂの表面上には、アルミニウムがドーピングされた高濃度ｐ+型層ｃが堆積され、その上面には、アルミニウムがドーピングされた、ｐ+型層ｃより低濃度のｐ型層ｄが堆積されている。 In FIG. 1, for example, an n-type drift layer b doped with nitrogen and having a lower concentration than the substrate a is deposited on the surface of the high-concentration n + -type substrate a having a (0001) plane doped with nitrogen. ing. A high-concentration p + -type layer c doped with aluminum is deposited on the surface of the low-concentration n-type drift layer b, and a lower concentration than the p + -type layer c doped with aluminum is deposited on the upper surface thereof. A p-type layer d is deposited.
このｐ型層ｄの表面部分には、たとえば、選択的にリンがドーピングされた高濃度ｎ+型ソース領域ｅが形成されており、高濃度ｐ+型層ｃには、選択的に形成された切欠き部からなる第１の領域が設けられ、また、低濃度ｐ型層ｄには、切欠き部より幅の広い切欠き部からなる第２の領域が形成されている。 For example, a high-concentration n + type source region e selectively doped with phosphorus is formed on the surface portion of the p-type layer d, and is selectively formed in the high-concentration p + type layer c. A first region consisting of a notch is provided, and a second region consisting of a notch wider than the notch is formed in the low-concentration p-type layer d.
第１及び第２の領域には、窒素がドーピングされた、低濃度ｎ型ベース領域ｆがｎ型ドリフト層ｂに直接接して設けられており、低濃度ｐ型層ｄにおける幅の広い第２の領域は、チャネル抵抗成分が小さくなり、炭化ケイ素半導体装置のオン抵抗を低減することができる。
ｎ型ベース領域ｆと高濃度ｎ+型ソース領域ｅの中間部分には、高濃度ｐ+型層ｃの表面層に低濃度ベース領域ｇが形成され、その上面及びｎ型ベース領域ｆの表面上には、ゲート絶縁膜ｈを介してゲート電極ｉが設けられており、ゲート電極ｉ上には、層間絶縁膜ｊを介して、高濃度ｎ+型ソース領域ｅと低濃度ｐ型層ｄとのそれぞれの表面に低抵抗接続されたソース電極ｋが形成されている。
なお、ｐはドレイン電極である。
In the first and second regions, a low-concentration n-type base region f doped with nitrogen is provided in direct contact with the n-type drift layer b, and the second wide layer in the low-concentration p-type layer d is provided. In this region, the channel resistance component is reduced, and the on-resistance of the silicon carbide semiconductor device can be reduced.
A low-concentration base region g is formed on the surface layer of the high-concentration p + -type layer c at the intermediate portion between the n-type base region f and the high-concentration n + -type source region e, and its upper surface and the surface of the n-type base region f A gate electrode i is provided on the gate electrode i via a gate insulating film h. A high concentration n + type source region e and a low concentration p type layer d are provided on the gate electrode i via an interlayer insulating film j. A source electrode k connected to each other at low resistance is formed.
Note that p is a drain electrode.
このように、低濃度ｎ型ドリフト層ｂの一部の部分ｍが表面に露出しており、高濃度ｐ+型層ｃが、この低濃度ｎ型ドリフト層ｂに直接接して設けられており、低濃度ｎ型ドリフト層ｂの表面すべてが高濃度ｐ+型層ｃで覆われることなく、高濃度ｐ+型層ｃが、ｎ型不純物イオンを注入して低濃度ｎ型ベース領域ｆを形成する領域を除いて、すべて低濃度のｐ型層ｄで構成されているので、ｎ型不純物イオン注入を行った後、ｎ型ベース領域ｆのｎ型ドリフト層ｂと接する部分ｍを高濃度にでき、オン抵抗を低減することが可能となる。 Thus, a part m of the low-concentration n-type drift layer b is exposed on the surface, and the high-concentration p + -type layer c is provided in direct contact with the low-concentration n-type drift layer b. without any surface of the low concentration n-type drift layer b is covered with the high-concentration p + -type layer c, the high-concentration p + -type layer c is, by implanting n-type impurity ions of low concentration n-type base region f Except for the region to be formed, all are composed of a low-concentration p-type layer d. Therefore, after n-type impurity ion implantation, a portion m in contact with the n-type drift layer b of the n-type base region f is highly concentrated. Thus, the on-resistance can be reduced.
上記の先行技術により、ｎ型ベース領域ｆのｎ型ドリフト層ｂと接する部分ｍを高濃度にでき、オン抵抗を低減することが可能となるが、一般に、高濃度ｎ+型基板ａより低濃度のｎ型ＳｉＣ層（ｎ型耐圧領域）であるドリフト層ｂは、ソース・ドレイン電極間に電流が流れる際、ドリフト層ｂでの電位降下が大きく、その結果電流導通時の抵抗が大きくなってしまう。
これを防止するため、ドリフト層ｂの不純物濃度を上げると、低濃度ｐ型層ｍと低濃度ｎ型ドリフト層ｂとの接合部分から広がる空乏層が不十分となり、局所的なブレークダウンが発生し、耐圧が低下する。
According to the above-described prior art, the portion m in contact with the n-type drift layer b of the n-type base region f can be made high in concentration and the on-resistance can be reduced, but generally lower than that in the high-concentration n + -type substrate a. The drift layer b, which is an n-type SiC layer (n-type withstand voltage region), has a large potential drop in the drift layer b when a current flows between the source and drain electrodes. As a result, the resistance during current conduction increases. End up.
In order to prevent this, if the impurity concentration of the drift layer b is increased, the depletion layer extending from the junction between the low-concentration p-type layer m and the low-concentration n-type drift layer b becomes insufficient, and local breakdown occurs. However, the withstand voltage decreases.
このように、ＳｉＣ−ＭＯＳＦＥＴにおいては、ドリフト層ｂ自体が、さらなる素子耐圧向上とオン抵抗低減の両立を阻む要因となっており、素子耐圧を確保した上で、さらなるオン抵抗の低減を実現するため、ドリフト層ｂの改善が求められている。 As described above, in the SiC-MOSFET, the drift layer b itself is a factor that hinders both further improvement of the device breakdown voltage and reduction of the on-resistance, and further reduces the on-resistance after securing the device breakdown voltage. Therefore, improvement of the drift layer b is demanded.
素子耐圧の向上とオン抵抗の低減を両立させるため、上記特許文献２には、ＬＤＭＯＳトランジスタ（ラテラル二重拡散ＭＯＳトランジスタ）のｎ型拡散領域にｐ型拡散領域を形成し、ドレイン側のゲートエッジ周辺の領域の電界集中を緩和することが記載されている。また上記特許文献３には、横側ＭＯＳＦＥＴのｎ型ドレインドリフト層に、ｐ型埋め込み領域を形成し、高耐圧化、低オン抵抗化を図ることが記載されている。
しかし、これらはいずれも、ＬＤＭＯＳトランジスタ、横側ＭＯＳＦＥＴを前提としたもので、そのままでは、炭化ケイ素縦型ＭＯＳＦＥＴに適用できず、素子耐圧を確保した上で、さらなるオン抵抗の低減を実現することはできない。
In order to achieve both improvement in device breakdown voltage and reduction in on-resistance,
However, both of these are premised on LDMOS transistors and lateral MOSFETs, and cannot be applied to silicon carbide vertical MOSFETs as they are, and further reduce the on-resistance while ensuring the device breakdown voltage. I can't.
すなわち、縦型素子の場合電流が縦方向に流れるため、ｐ型埋め込み領域と垂直方向に流れる電流を妨げないように、高精度な前記ｐ型領域同志の合わせ精度が必要となる。
これに対し横型素子は、ｐ型埋め込み領域と平行に電流が流れるため高度な合わせ精度は全く必要ない。また横型素子の場合、素子内を流れる電流は表面に集中して流れるため、ｐ型埋め込み層を適用してことで達成されるｎ型層の高濃度化、低オン抵抗の効果が、電流が流れる表面層のみに限られるが、縦型素子の場合は電流が素子全体に均一に流れる構造であるため、ｐ型埋め込み層の適用によるｎ層の高濃度層の効果が素子全体に影響するため、低オン抵抗化の効果が横型素子に比べ格段に大きくなる。
That is, in the case of a vertical element, since the current flows in the vertical direction, a highly accurate alignment accuracy between the p-type regions is required so as not to disturb the current flowing in the direction perpendicular to the p-type buried region.
On the other hand, since a current flows in parallel with the p-type buried region, the lateral element does not require any high alignment accuracy. In the case of a lateral element, the current flowing in the element concentrates on the surface, so that the effect of increasing the concentration of the n-type layer and reducing the on-resistance achieved by applying the p-type buried layer Although it is limited to the flowing surface layer, in the case of a vertical element, since the current flows uniformly throughout the element, the effect of the high concentration layer of n layers due to the application of the p-type buried layer affects the entire element. As a result, the effect of reducing the on-resistance is remarkably greater than that of the lateral element.
そこで、本発明の目的は、炭化ケイ素縦型ＭＯＳＦＥＴのドリフト層に、高濃度ｎ+型ソース領域と同一の位置に、高濃度ｐ+型層を中間層として形成することにより、ドリフト層の不純物濃度を上げても、ｎ型耐圧領域であるドリフト層と高濃度ｐ+型層との接合面に空乏層を発生させ、その両端に印加される電圧がドレイン電極の電圧を増加させても変化しないことを利用して、素子耐圧向上とオン抵抗低減の両立を実現することにある。 Accordingly, an object of the present invention is to form an impurity in the drift layer by forming a high-concentration p + -type layer as an intermediate layer in the drift layer of the silicon carbide vertical MOSFET at the same position as the high-concentration n + -type source region. Even if the concentration is increased, a depletion layer is generated at the junction surface between the drift layer which is the n-type breakdown voltage region and the high concentration p + -type layer, and the voltage applied to both ends of the depletion layer changes even when the drain electrode voltage is increased. This is to realize both improvement in device breakdown voltage and reduction in on-resistance.
以上の目的を達成するため、本発明の縦型ＭＯＳＦＥＴにおいては、次のような技術的手段を講じた。すなわち、本発明の縦型ＭＯＳＦＥＴは、
（１）炭化珪素からなり、第１導電型の半導体基板（１）と、前記半導体基板（１）上に形成された、第１導電型で前記半導体基板（１）よりも低濃度の第１の半導体層（２）と、前記第１の半導体層（２）上に選択的に形成された、高濃度の第２導電型である第２の半導体層（３）と、前記第１の半導体層（２）及び前記第２の半導体層（３）上に、第１導電型で前記第１の半導体層（２）と同一の濃度で形成された第３の半導体層（２１）と、前記第３の半導体層（２１）の表面に、前記第２の半導体層（３）と同一の位置上に選択的に形成された、前記第２の半導体層（３）と同一膜厚の高濃度の第２導電型である第４の半導体層（３１）と、前記第４の半導体層（３１）の表面に形成された第２導電型で低濃度のベース層（４）と、当該ベース層（４）の表面層に選択的に形成された第２導電型のコンタクト領域（１２）及び第１導電型のソース領域（５）と、
表面から前記ベース層（４）を貫通して、前記第３の半導体層（２１）に達するように形成された第１導電型のウェル領域（６）と、前記ソース領域（５）と前記ウェル領域（６）とに挟まれた、前記ベース層（４）の表面露出部上の少なくとも一部にゲート絶縁膜（８）を介して設けられたゲート電極層（９）と、前記ソース領域（５）と前記コンタクト領域（１２）の表面に共通に接触するソース電極（１０）と、前記半導体基板（１）の裏面に設けられたドレイン電極（１１）と構成される。
In order to achieve the above object, the following technical means were taken in the vertical MOSFET of the present invention. That is, the vertical MOSFET of the present invention is
(1) A first conductive type semiconductor substrate (1) made of silicon carbide and formed on the semiconductor substrate (1) and having a first conductivity type and a lower concentration than the semiconductor substrate (1). A semiconductor layer (2), a second semiconductor layer (3) having a high concentration of the second conductivity type selectively formed on the first semiconductor layer (2), and the first semiconductor A third semiconductor layer (21) formed on the layer (2) and the second semiconductor layer (3) with the same conductivity type as the first semiconductor layer (2); A high concentration of the same film thickness as the second semiconductor layer (3) selectively formed on the surface of the third semiconductor layer (21) at the same position as the second semiconductor layer (3). A fourth semiconductor layer (31) of the second conductivity type, a second conductivity type low-concentration base layer (4) formed on the surface of the fourth semiconductor layer (31), The base layer selectively formed second conductivity type contact regions (12) and the first conductive type source region in the surface layer (4) (5),
A well region (6) of the first conductivity type formed so as to penetrate the base layer (4) from the surface and reach the third semiconductor layer (21), the source region (5), and the well A gate electrode layer (9) provided on at least a part of the exposed surface of the base layer (4) between the region (6) via a gate insulating film (8), and the source region ( 5) and a source electrode (10) in common contact with the surface of the contact region (12), and a drain electrode (11) provided on the back surface of the semiconductor substrate (1).
（２）上記の縦型ＭＯＳＦＥＴにおいて、前記第２の半導体層（３）及び前記第３の半導体層（２１）を交互に複数形成した。 (2) In the vertical MOSFET, a plurality of the second semiconductor layers (3) and the third semiconductor layers (21) are alternately formed.
また、上記の縦型ＭＯＳＦＥＴを効率よく製造するため、本発明の縦型ＭＯＳＦＥＴの製造方法は、次のような工程から構成した。すなわち、本発明の縦型ＭＯＳＦＥＴの製造方法は、
（３）炭化珪素からなり、第１導電型の半導体基板（１）上に、第１導電型で前記半導体基板（１）よりも低濃度の第１の半導体層（２）をエピタキシャル成長により形成する第１の工程と、前記第１の半導体層（２）上に、高濃度の第２導電型である第２の半導体層（３）を、マスクを用いたイオン注入により選択的に形成する第２の工程と、前記第１の半導体層（２）及び前記第２の半導体層（３）上に、前記第１の半導体層（２）と同一の濃度の第３の半導体層（２１）をエピタキシャル成長により形成する第３の工程と、前記第３の半導体層（２１）上に、前記第２の工程で形成した前記第２の半導体層（３）と同一の場所において、高濃度の第２導電型である、前記第２の半導体層（３）と同一膜厚の第４の半導体層（３１）を、マスクを用いたイオン注入により選択的に形成する第４の工程と、前記第４の半導体層（３１）の表面上に、第２導電型で低濃度のベース層（４）をエピタキシャル成長により形成する第５の工程と、前記ベース層（４）上に、前記第４の半導体層表面に直接達するよう、マスクを用いたイオン注入により第１導電型のウェル領域（６）を選択的に形成する第６の工程と、前記ベース層（４）上に、イオン注入により、第２導電型のコンタクト領域（１２）と、その内側に第１導電型のソース領域（５）を形成するとともに、前記ソース領域（５）と前記ウェル領域（６）とに挟まれた前記ベース層（４）の表面露出部の一部に、ゲート絶縁膜（８）を介して設けられたゲート電極層（９）を形成する第７の工程と、前記ソース領域（５）と前記コンタクト領域（１２）に共通して接触するようソース電極（１０）を形成するとともに、前記半導体基板（１）の裏面にドレイン電極（１１）を形成する第８の工程とから構成する。
In addition, in order to efficiently manufacture the vertical MOSFET, the vertical MOSFET manufacturing method of the present invention includes the following steps. That is, the manufacturing method of the vertical MOSFET of the present invention is as follows.
(3) A first semiconductor layer (2) of the first conductivity type and having a lower concentration than the semiconductor substrate (1) is formed on the first conductivity type semiconductor substrate (1) by epitaxial growth. A first step of selectively forming a second semiconductor layer (3) having a high concentration of the second conductivity type on the first semiconductor layer (2) by ion implantation using a mask; And a third semiconductor layer (21) having the same concentration as that of the first semiconductor layer (2) on the first semiconductor layer (2) and the second semiconductor layer (3). A third step formed by epitaxial growth and a second high-concentration second layer on the third semiconductor layer (21) at the same location as the second semiconductor layer (3) formed in the second step. A fourth semiconductor layer (31) having the same film thickness as the second semiconductor layer (3), which is of a conductive type, A fourth step of selective formation by ion implantation using a mask, and a low-concentration base layer (4) of the second conductivity type is formed by epitaxial growth on the surface of the fourth semiconductor layer (31). In the fifth step, the first conductivity type well region (6) is selectively formed on the base layer (4) by ion implantation using a mask so as to directly reach the surface of the fourth semiconductor layer. In the sixth step, a second conductivity type contact region (12) and a first conductivity type source region (5) are formed on the inside of the base layer (4) by ion implantation. A gate electrode layer (9) provided on a part of the exposed surface of the base layer (4) sandwiched between the source region (5) and the well region (6) via a gate insulating film (8) A seventh step of forming a source region and the source region (5) To form a source electrode (10) so as to contact common to serial contact region (12), constructed from the eighth step of forming a drain electrode (11) on the back surface of the semiconductor substrate (1).
（４）上記の縦型ＭＯＳＦＥＴの製造方法において、前記第３の工程の後に、再び前記第２の工程を行い、前記第３の工程を行う工程を、少なくとも１回繰り返すようにした。 (4) In the above vertical MOSFET manufacturing method, the second step is performed again after the third step, and the step of performing the third step is repeated at least once.
本発明によれば、ソース電極とドレイン電極との間に高電圧が印加された場合、第２の半導体層ならびに第４の半導体層が起点となって、横方向にも空乏層を広げることができる。
これにより、半導体層２の濃度を従来ＭＯＳＦＥＴよりも高く設定しても、空乏層が伸びやすいため、高耐圧が実現できるので、高耐圧特性と半導体層２の濃度を高くしたことによる低オン抵抗特性が両立できること可能となる。
According to the present invention, when a high voltage is applied between the source electrode and the drain electrode, the depletion layer can be expanded in the lateral direction starting from the second semiconductor layer and the fourth semiconductor layer. it can.
As a result, even if the concentration of the
以下、図面を参照しつつ本発明の実施例について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
本実施例による、スイッチングデバイスであるＳｉＣ−ＮチャネルのＭＯＳＦＥＴの製造の手順は、次のとおりである。
この実施例では、第１の導電型をＮ型、第２の導電型をＰ型とし、高濃度を＋（プラス）、低濃度を−（マイナス）で示しているが、第１の導電型をＰ型、第２の導電型をＮ型としてもよい。
The procedure for manufacturing a SiC-N channel MOSFET as a switching device according to the present embodiment is as follows.
In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, high concentration is indicated by + (plus), and low concentration is indicated by-(minus). May be P-type and the second conductivity type may be N-type.
（第１の工程）
図２に示すように、第１の導電型で、窒素がドーピングされた（０００-１）面を有する高濃度の半導体基板１（Ｎ+型ＳｉＣ基板）の表面に、第１の導電型で半導体基板１よりも低濃度な第１半導体層２（Ｎ-型ＳｉＣ層）をエピタキシャル成長により形成する。本実施例では不純物濃度６×１０16ｃｍ-3、厚さ４.５μｍとした。
(First step)
As shown in FIG. 2, on the surface of a high-concentration semiconductor substrate 1 (N + -type SiC substrate) having a first conductivity type and having a (000-1) plane doped with nitrogen, the first conductivity type is formed. A first semiconductor layer 2 (N − type SiC layer) having a lower concentration than that of the
（第２の工程）
図３に示すように、第１の半導体層２（Ｎ-型ＳｉＣ層）の表面上に減圧ＣＶＤ法により堆積された厚さ１.５μｍのＳｉＯ2膜をフォトリソグラフィによりパターン加工して形成し、これをマスクとして、アルミニウムあるいはボロンをイオン注入して、高濃度の第１導電型である第２の半導体層３（Ｐ+型領域）を選択的に形成する。このとき、半導体基板１は５００℃程度に加熱してイオン注入をする。その結果、０.５μｍ厚の第２の半導体層３が形成される。
(Second step)
As shown in FIG. 3, a 1.5 μm thick SiO 2 film deposited by low pressure CVD is formed on the surface of the first semiconductor layer 2 (N − -type SiC layer) by patterning by photolithography. Then, using this as a mask, ions of aluminum or boron are ion-implanted to selectively form the second semiconductor layer 3 (P + -type region) having a high concentration of the first conductivity type. At this time, the
（第３の工程）
図４に示すように、マスクとしたＳｉＯ2膜を除去した後、第２の半導体層３（Ｐ+型領域）が形成された第１の半導体層２（Ｎ-型ＳｉＣ層）の表面上に、第１の半導体層２とほぼ同一の濃度で形成された第３の半導体層２１をエピタキシャル成長により形成する。厚さは半導体層２と同じ４.５μｍとした。
(Third step)
As shown in FIG. 4, after removing the SiO 2 film used as a mask, on the surface of the first semiconductor layer 2 (N − type SiC layer) on which the second semiconductor layer 3 (P + type region) is formed. In addition, a
（第４の工程）
図５に示すように、第３の半導体層２１の表面に、第２の工程と同一の位置に、ＳｉＯ2膜をパターン加工したマスクを形成した後、第２の工程と同様の手順で、アルミニウムあるいはボロンをイオン注入することにより、軸方向（図２（ｄ）の第３の半導体層２１の表面側）からみて第２の半導体層３（Ｐ+型領域）とほぼ同一の位置に、高濃度の第１導電型である、第４の半導体層３１（Ｐ+型領域）を０.５μｍ厚さで形成する。
(Fourth process)
As shown in FIG. 5, after forming a mask obtained by patterning a SiO 2 film on the surface of the
（第５の工程）
図６に示すように、第４の半導体層３１（Ｐ+型領域）の表面に、第２導電型で５×１０15ｃｍ-3と比較的低濃度のベース層（４）をエピタキシャル成長により、厚さ０.５μｍで形成する。
(Fifth step)
As shown in FIG. 6, a base layer (4) having a relatively low concentration of 5 × 10 15 cm −3 of the second conductivity type is epitaxially grown on the surface of the fourth semiconductor layer 31 (P + -type region). It is formed with a thickness of 0.5 μm.
（第６の工程）
図７に示すように、ベース層４の表面に、第４の半導体層３１（Ｐ+型領域）を形成した位置を避け、このベース層４にマスクを用いたイオン注入により第１導電型ウェル領域６を選択的に形成する。この第１導電型ウェル領域６は、表面からベース層（４）を貫通して、第３の半導体層２１に達することになる。
(Sixth step)
As shown in FIG. 7, the position where the fourth semiconductor layer 31 (P + -type region) is formed on the surface of the
（第７の工程）
図８に示すように、ベース層４内にアルミニウムイオンを打ち込み、後述するソース電極１０と接触するコンタクト領域１２（Ｐ+部分）を形成するとともに、その内側にリンイオンを打ち込み、コンタクト領域１２（Ｐ+部分）とベース層４との表面に共通に接触するよう、高濃度の第１導電型であるソース領域５（ｎ+部分）を形成する。
そして、ベース層４の表面露出部の一部にゲート絶縁膜８を形成し、ゲートｐｏｌｙ−Ｓｉ９及び層間絶縁膜１３を形成する。
(Seventh step)
As shown in FIG. 8, aluminum ions are implanted into the
Then, the
（第８の工程）
図９に示すように、第８の工程により、この第１導電型ソース領域５とベース層４との表面に共通に接触するようソース電極１０を形成した後、半導体基板１の裏面にドレイン電極１１を形成する。
(Eighth step)
As shown in FIG. 9, after forming the
なお、第３の工程終了後、再び第２の工程に戻り、第３の半導体層２１を複数形成することも可能である。 Note that it is possible to return to the second step again after the third step and to form a plurality of third semiconductor layers 21.
このような工程で、図９に示されるような構造の炭化珪素縦型ＭＯＳＦＥＴが得られるが、ソース電極１０とドレイン電極１１との間に高電圧が印加された場合、第２の半導体層３ならびに第４の半導体層３１（Ｐ+型領域）が起点となって、横方向にも空乏層が広がることができる。これにより、半導体層２の濃度を従来ＭＯＳＦＥＴよりも高く設定しても、空乏層が伸びやすいため、高耐圧が実現できるので、高耐圧特性と半導体層２の濃度を高くしたことによる低オン抵抗特性が両立できることになる。
Through such a process, a silicon carbide vertical MOSFET having a structure as shown in FIG. 9 is obtained. When a high voltage is applied between the
以上説明したとおり、本発明の縦型ＭＯＳＦＥＴ構造によれば、従来の縦方向だけでなく横方向にも空乏層が伸びることになり、その結果、半導体層２の濃度を従来ＭＯＳＦＥＴよりも高く設定しても、空乏層は伸びやすいので、高耐圧が実現され、しかも、半導体層の濃度を高くしたことにより、低オン抵抗特性が両立できるので、高耐圧、低オン抵抗の縦型ＭＯＳＦＥＴに広く採用されることが期待できる。
As described above, according to the vertical MOSFET structure of the present invention, the depletion layer extends not only in the conventional vertical direction but also in the horizontal direction. As a result, the concentration of the
１ 半導体基板
２ 第１の半導体層
３ 第２の半導体層
４ 第６の半導体層
５ 第１導電型ソース領域
６ 第１導電型ウェル層
８ ゲートpoly-Si絶縁膜
１０ ソース電極
１１ ドレイン電極層
１２ コンタクト領域
１３ ゲート絶縁膜
２１ 第３の半導体層
３１ 第４の半導体層
DESCRIPTION OF
Claims (4)
前記半導体基板（１）上に形成された、第１導電型で前記半導体基板（１）よりも低濃度の第１の半導体層（２）と、
前記第１の半導体層（２）上に選択的に形成された、高濃度の第２導電型である第２の半導体層（３）と、
前記第１の半導体層（２）及び前記第２の半導体層（３）上に、第１導電型で前記第１の半導体層（２）と同一の濃度で形成された第３の半導体層（２１）と、
前記第３の半導体層（２１）の表面に、前記第２の半導体層（３）と同一の位置上に選択的に形成された、前記第２の半導体層（３）と同一膜厚の高濃度の第２導電型である第４の半導体層（３１）と、
前記第４の半導体層（３１）の表面に形成された第２導電型で低濃度のベース層（４）と、
当該ベース層（４）の表面層に選択的に形成された第２導電型のコンタクト領域（１２）及び第１導電型のソース領域（５）と、
表面から前記ベース層（４）を貫通して、前記第３の半導体層（２１）に達するように形成された第１導電型のウェル領域（６）と、
前記ソース領域（５）と前記ウェル領域（６）とに挟まれた、前記ベース層（４）の表面露出部上の少なくとも一部にゲート絶縁膜（８）を介して設けられたゲート電極層（９）と、
前記ソース領域（５）と前記コンタクト領域（１２）との表面に共通に接触するソース電極（１０）と、
前記半導体基板（１）の裏面に設けられたドレイン電極（１１）とからなる縦型ＭＯＳＦＥＴ。 A first conductivity type semiconductor substrate (1) made of silicon carbide;
A first conductivity type first semiconductor layer (2) formed on the semiconductor substrate (1) and having a lower concentration than the semiconductor substrate (1);
A second semiconductor layer (3), which is selectively formed on the first semiconductor layer (2) and has a second conductivity type of high concentration;
A third semiconductor layer (first conductivity type) formed on the first semiconductor layer (2) and the second semiconductor layer (3) at the same concentration as the first semiconductor layer (2). 21) and
The surface of the third semiconductor layer (21) is selectively formed on the same position as the second semiconductor layer (3) and has the same thickness as the second semiconductor layer (3). A fourth semiconductor layer (31) having a second conductivity type with a concentration;
A second conductivity type low-concentration base layer (4) formed on the surface of the fourth semiconductor layer (31);
A second conductivity type contact region (12) and a first conductivity type source region (5) selectively formed on the surface layer of the base layer (4);
A well region (6) of the first conductivity type formed so as to penetrate the base layer (4) from the surface and reach the third semiconductor layer (21);
A gate electrode layer provided at least partially on the surface exposed portion of the base layer (4) between the source region (5) and the well region (6) via a gate insulating film (8). (9) and
A source electrode (10) in common contact with the surfaces of the source region (5) and the contact region (12);
A vertical MOSFET comprising a drain electrode (11) provided on the back surface of the semiconductor substrate (1).
前記第１の半導体層（２）上に、高濃度の第２導電型である第２の半導体層（３）を、マスクを用いたイオン注入により選択的に形成する第２の工程と、
前記第１の半導体層（２）及び前記第２の半導体層（３）上に、前記第１の半導体層（２）と同一の濃度の第３の半導体層（２１）をエピタキシャル成長により形成する第３の工程と、
前記第３の半導体層（２１）上に、前記第２の工程で形成した前記第２の半導体層（３）と同一の場所において、高濃度の第２導電型である、前記第２の半導体層（３）と同一膜厚の第４の半導体層（３１）を、マスクを用いたイオン注入により選択的に形成する第４の工程と、
前記第４の半導体層（３１）の表面上に、第２導電型で低濃度のベース層（４）をエピタキシャル成長により形成する第５の工程と、
前記ベース層（４）上に、前記第４の半導体層表面に直接達するよう、マスクを用いたイオン注入により第１導電型のウェル領域（６）を選択的に形成する第６の工程と、
前記ベース層（４）上に、イオン注入により、第２導電型のコンタクト領域（１２）と、その内側に第１導電型のソース領域（５）を形成するとともに、前記ソース領域（５）と前記ウェル領域（６）とに挟まれた前記ベース層（４）の表面露出部の一部に、ゲート絶縁膜（８）を介して設けられたゲート電極層（９）を形成する第７の工程と、
前記ソース領域（５）と前記コンタクト領域（１２）に共通して接触するようソース電極（１０）を形成するとともに、前記半導体基板（１）の裏面にドレイン電極（１１）を形成する第８の工程とからなる縦型ＭＯＳＦＥＴの製造方法。 A first semiconductor layer (2) made of silicon carbide and having a first conductivity type and a lower concentration than the semiconductor substrate (1) is formed on the first conductivity type semiconductor substrate (1) by epitaxial growth. Process,
A second step of selectively forming, on the first semiconductor layer (2), a second semiconductor layer (3) having a high concentration of the second conductivity type by ion implantation using a mask;
A third semiconductor layer (21) having the same concentration as the first semiconductor layer (2) is formed on the first semiconductor layer (2) and the second semiconductor layer (3) by epitaxial growth. 3 steps,
On the third semiconductor layer (21), the second semiconductor having the second conductivity type of high concentration at the same location as the second semiconductor layer (3) formed in the second step. A fourth step of selectively forming a fourth semiconductor layer (31) having the same thickness as the layer (3) by ion implantation using a mask;
A fifth step of forming a second conductivity type low-concentration base layer (4) on the surface of the fourth semiconductor layer (31) by epitaxial growth;
A sixth step of selectively forming a first conductivity type well region (6) on the base layer (4) by ion implantation using a mask so as to directly reach the surface of the fourth semiconductor layer;
A second conductivity type contact region (12) and a first conductivity type source region (5) are formed therein by ion implantation on the base layer (4), and the source region (5) A gate electrode layer (9) provided via a gate insulating film (8) is formed on a part of the surface exposed portion of the base layer (4) sandwiched between the well regions (6). Process,
A source electrode (10) is formed so as to be in common contact with the source region (5) and the contact region (12), and a drain electrode (11) is formed on the back surface of the semiconductor substrate (1). A method of manufacturing a vertical MOSFET comprising the steps.
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