JP5776610B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device having a semiconductor switching element having a trench gate structure and a method for manufacturing the same.

  In a semiconductor device having a semiconductor switching element, it is effective to increase the channel density in order to flow a larger current. In a silicon transistor, a MOSFET having a trench gate structure is adopted and put into practical use in order to increase the channel density. Although this trench gate structure can be applied to a SiC semiconductor device, there is a big problem when applied to SiC. That is, since SiC has a breakdown electric field strength 10 times that of silicon, SiC semiconductor devices are used in a state where a voltage nearly 10 times that of silicon devices is applied. For this reason, there is a problem that an electric field 10 times stronger than that of the silicon device is applied to the gate insulating film formed in the trench, and the gate insulating film is easily broken at the corner of the trench.

  In order to solve such a problem, in Patent Document 1, an electric field relaxation layer made of a p-type layer is formed by ion-implanting p-type impurities below the bottom (bottom) of the trench constituting the trench gate structure. A structure has been proposed. By forming such an electric field relaxation layer, the electric field concentration at the bottom of the trench can be relaxed, and the gate insulating film can be prevented from being broken.

JP 2007-129259 A

  However, in the case of the structure described in Patent Document 1, since the electric field relaxation layer is in a floating state, there is a problem that the switching characteristics are deteriorated. For this reason, it is necessary to suppress the deterioration of switching characteristics by connecting the electric field relaxation layer formed at the bottom of the trench to the upper source electrode and fixing it to the source potential.

  However, as a process for forming the p-type connection layer for connecting the electric field relaxation layer at the bottom of the trench to the source electrode, an additional treatment such as ion implantation is required, which causes the manufacturing process to become complicated and There arises a problem that the cost increases.

  In view of the above, the present invention provides an SiC semiconductor device having a structure that does not require a separate step for forming a connection layer for connecting an electric field relaxation layer and a source electrode at the bottom of a trench, and a method for manufacturing the same. The purpose is to do.

In order to achieve the above object, according to the first aspect of the present invention, there is provided a method for manufacturing a silicon carbide semiconductor device provided with a semiconductor switching element, wherein the <11-20> direction is turned off as the semiconductor substrate (1 to 4). A step of preparing an off substrate having an off angle as a direction, and a line having an off direction as a longitudinal direction by etching and penetrating the source region (4) and the base region (3) to form a drift layer (2 ) , And the {11-20} surface, which is one of the two end surfaces in the longitudinal direction , is perpendicular to the off direction and inclined with respect to the main surface of the semiconductor substrate. A trench etching step for forming the trench (6) so that the second conductivity type impurity is ion-implanted from a direction perpendicular to the main surface of the semiconductor substrate, so that the bottom of the trench and one end of the trench are formed. A second conductivity type electric field relaxation layer (7) having a bottom layer (7a) located at the bottom of the trench and a tip layer (7b) located at one tip of the trench is implanted with the second conductivity type impurity at the end face. And a step of forming a).

  In this way, the electric field relaxation layer is formed by ion implantation from the vertical direction of the substrate while the one end surface of the trench is a surface perpendicular to the off direction, that is, a surface inclined with respect to the main surface of the semiconductor substrate. Try to form. As a result, a bottom layer can be formed at the bottom of the trench, and at the same time, ion implantation is also performed on the tip surface inclined with respect to the main surface of the semiconductor substrate, thereby forming the tip layer. Therefore, a tip layer as a connection layer for connecting the bottom layer to the source electrode (11) through the base region or the like can be formed simultaneously with the bottom layer. For this reason, it is not necessary to separately perform a step for forming the tip layer, and it is not necessary to perform complicated ion implantation such as oblique ion implantation. Thereby, it becomes possible to simplify the manufacturing process of the SiC semiconductor device.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is the perspective sectional view which extracted one cell of MOSFET of the trench gate structure concerning a 1st embodiment of the present invention. It is II-II sectional drawing of MOSFET shown in FIG. FIG. 2 is a perspective sectional view showing a state in a trench 6 of the MOSFET shown in FIG. 1. FIG. 5 is a perspective cross-sectional view showing a manufacturing process of the MOSFET having the trench gate structure shown in FIG. It is sectional drawing which showed the inclination of the side surface of the trench 6 in the case where the surface of a semiconductor substrate turns into Si surface and C surface. It is sectional drawing when the process of FIG.4 (d) is seen in a different cross section.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described. Here, an SiC semiconductor device in which an inversion MOSFET is formed as a semiconductor switching element having a trench gate structure will be described as an example.

As shown in FIG. 1, an n-channel type inversion MOSFET is formed in the SiC semiconductor device. A MOSFET having a plurality of cells is configured by arranging MOSFETs having the same structure as the MOSFET shown in FIG. Specifically, an n ⁺ type substrate 1 made of SiC is used, and MOSFETs are configured by forming each component of the MOSFET on the n ⁺ type substrate 1.

The n ⁺ type substrate 1 has a (0001) plane or a (000-1) plane, that is, a Si plane or a C plane as a main surface, for example, a predetermined off angle (for example, 3.11) with an off direction of <11-20>. 5 degrees). The concentration of n-type impurities such as nitrogen in the n ⁺ -type substrate 1 is, for example, 1.0 × 10 ¹⁹ / cm ^3, and the thickness is, for example, about 300 μm. On the main surface of the n ⁺ -type substrate 1, n ^{− made} of SiC having an n-type impurity concentration of, for example, nitrogen of 3.0 × 10 ^{15 to} 2.0 × 10 ¹⁶ / cm ³ and a thickness of about 10 to ¹⁵ μm. A type drift layer 2 is formed. The impurity concentration of the n ⁻ type drift layer 2 may be constant in the depth direction, but the concentration distribution is inclined, and the n ⁺ type substrate 1 side of the n ⁻ type drift layer 2 is n ⁺ type. The concentration can be higher than that on the side away from the substrate 1. In this way, since the internal resistance of the n ⁻ type drift layer 2 can be reduced, the on-resistance can be reduced.

A p-type base region 3 is formed in the surface layer portion of the n ⁻ -type drift layer 2, and an n ⁺ -type source region 4 and a p ⁺ -type contact layer 5 are formed in an upper layer portion of the p-type base region 3. Has been.

The p-type base region 3 has a p-type impurity concentration such as boron or aluminum of, for example, 1.0 × 10 ^{16 to} 2.0 × 10 ¹⁹ / cm ³ and a thickness of about 2.0 μm. The n ⁺ -type source region 4 is configured such that the n-type impurity concentration (surface concentration) such as nitrogen in the surface layer portion is, for example, 1.0 × 10 ²¹ / cm ³ and the thickness is about 0.3 μm. The p ⁺ -type contact layer 5 has a p-type impurity concentration (surface concentration) such as boron or aluminum in the surface layer portion of, for example, 1.0 × 10 ²¹ / cm ³ and a thickness of about 0.3 μm. The n ⁺ -type source region 4 is disposed on both sides of a trench gate structure described later, and the p ⁺ -type contact layer 5 is provided on the opposite side of the trench gate structure with the n ⁺ -type source region 4 interposed therebetween.

In addition, a structure in which the p-type base region 3 and the n ⁺ -type source region 4 are penetrated to the n ⁻ -type drift layer 2 and the bottom portion has a predetermined width, for example, the width is 0.5 to 2.0 μm and the depth is A trench 6 of 2.0 μm or more (for example, 2.4 μm) is formed. The p-type base region 3 and the n ⁺ -type source region 4 are arranged so as to be in contact with the side surface of the trench 6.

  The trench 6 is formed with the x direction in FIG. 1 as the width direction, the y direction as the longitudinal direction, and the z direction as the depth direction. Only one trench 6 is shown in FIG. The trenches 6 are arranged in parallel in the x direction to form a stripe shape in which the trenches 6 are arranged in parallel. 1 is the <11-20> direction, and as shown in FIGS. 2 and 3, one of the two end surfaces of the trench 6 is perpendicular to the off direction. A plane, that is, a {11-20} plane in which the normal direction of the side surface and the off direction coincide with each other. Then, both side surfaces of the trench 6 are {1-100} planes as shown in FIG. The inner wall surface including the corner portion at the bottom of the trench 6 is rounded by a rounding process.

As shown in FIGS. 1 to 3, p-type SiC is formed on the bottom surface of the trench 6 configured as described above and the front end surface of the both front end surfaces that are perpendicular to the off direction. A configured electric field relaxation layer 7 is formed. Specifically, the electric field relaxation layer 7 includes a bottom p-type layer 7 a formed at the bottom of the trench 6 and a tip p-type layer 7 b formed on one of the two tip surfaces of the trench 6. However, as will be described later, it is formed by a single ion implantation step from the direction perpendicular to the substrate surface. The p-type impurity concentration of the electric field relaxation layer 7 is set to 1 × 10 ¹⁷ / cm ³ or more, for example.

The electric field relaxation layer 7 is formed at the bottom of the trench 6 and one of the front end surfaces. However, except for the front end p-type layer 7 b formed at the front end surface of the trench 6, the electric field relaxation layer 7 and the p-type base region 3. N ⁻ type drift layer 2 is left between and p type base region 3. For this reason, the n ⁻ type drift layer 2 is exposed on the side surface of the trench 6. The tip p-type layer 7b is connected to at least the p-type base region 3, and the bottom p-type layer 7a is fixed to the same potential as the p-type base region 3 through the tip p-type layer 7b.

  Furthermore, the inner wall surface of the trench 6 is covered with a gate insulating film 8 made of an oxide film or the like, and a gate electrode 9 made of doped Poly-Si formed on the surface of the gate insulating film 8. The inside of the trench 6 is filled. The gate insulating film 8 is formed by thermally oxidizing the inner wall surface of the trench 6, and the thickness of the gate insulating film 8 is about 100 nm on both the side surface side and the bottom side of the trench 6. In this way, a trench gate structure is configured.

A source electrode 11 and a gate wiring (not shown) are formed on the surface of the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5 and the surface of the gate electrode 9 via an interlayer insulating film 10. The source electrode 11 and the gate wiring are composed of a plurality of metals (for example, Ni / Al, etc.), and at least n-type SiC (specifically, the n ⁺ -type source region 4 and the gate electrode 9 in the case of n doping) The portion in contact with n-type SiC is made of a metal capable of ohmic contact with n-type SiC, and the portion in contact with at least p-type SiC (specifically, p ⁺ -type contact layer 5 or gate electrode 9 in the case of p-doping) is p-type. It is made of a metal capable of ohmic contact with SiC. The source electrode 11 and the gate wiring are electrically insulated by being formed on the interlayer insulating film 10, and the source electrode 11 is connected to the n ⁺ type source region through the contact hole formed in the interlayer insulating film 10. 4 and the p ⁺ -type contact layer 5 are in electrical contact, and the gate wiring is in electrical contact with the gate electrode 9.

Then, on the back side of the n ⁺ -type substrate 1 n ⁺ -type substrate 1 and electrically connected to the drain electrode 12 are formed. With such a structure, an n-channel inversion type MOSFET having a trench gate structure is formed.

  Such an inverted MOSFET having a trench gate structure operates as follows. First, the inversion layer is not formed in the p-type base region 3 before the gate voltage is applied to the gate electrode 9. Therefore, even if a positive voltage is applied to the drain electrode 12, electrons cannot reach the p-type base region 3 from the n-type source region 4, and no current flows between the source electrode 11 and the drain electrode 12. Not flowing.

Next, when off (gate voltage = 0 V, drain voltage = 650 V, source voltage = 0 V), a reverse bias is applied even if a voltage is applied to the drain electrode 12, so the p-type base region 3 and the n ⁻ -type drift layer A depletion layer spreads between two. At this time, since the concentration of the p-type base region 3 is higher than that of the n ⁻ -type drift layer 2, the depletion layer extends almost to the n ⁻ -type drift layer 2 side. Since the depletion layer is wider than in the case of the drain 0 V, the region that behaves as an insulator further spreads, so that no current flows between the source electrode 11 and the drain electrode 12.

In addition, since the gate voltage is 0 V, an electric field is also applied between the drain and the gate. For this reason, electric field concentration can also occur at the bottom of the gate insulating film 8. However, since electric field relaxation layer 7 is provided at the bottom of trench 6, the depletion layer at the PN junction between electric field relaxation layer 7 and n ⁻ type drift layer 2 greatly extends toward n ⁻ type drift layer 2. Thus, a high voltage due to the influence of the drain voltage hardly enters the gate insulating film 8. As a result, the electric field concentration in the gate insulating film 8, particularly the electric field concentration at the bottom of the trench 6 in the gate insulating film 8 can be relaxed, and the gate insulating film 8 is prevented from being destroyed. Is possible.

On the other hand, when ON (gate voltage = 20 V, drain voltage = 1 V, source voltage = 0 V), 20 V is applied as the gate voltage to the gate electrode 9, so that it is in contact with the trench 6 in the p-type base region 3. A channel is formed on the surface. For this reason, electrons injected from the source electrode 11 pass through the channel formed in the p-type base region 3 from the n ⁺ -type source region 4 and then reach the n ⁻ -type drift layer 2. As a result, a current can flow between the source electrode 11 and the drain electrode 12.

In such a MOSFET having a trench gate structure, since the bottom p-type layer 7a is connected to the p-type base region 3 via the tip p-type layer 7b, the electric field relaxation layer 7 has the same potential as that of the p-type base region 3. It becomes. That is, since the p-type base region 3 is connected to the source electrode 12 via the p ⁺ -type contact layer 5, the electric field relaxation layer 7 is fixed at the source potential. For this reason, the electric field relaxation layer 7 can be prevented from being in a floating state, and the deterioration of switching characteristics can be further suppressed.

  Next, a manufacturing method of the MOSFET having the trench gate structure shown in FIG. 1 will be described with reference to FIG.

[Step shown in FIG. 4 (a)]
First, an n-type impurity such as nitrogen, which is composed of an off-substrate having a predetermined off angle (eg, 3.5 degrees) with the Si surface or C surface as the main surface and the off direction being <11-20>, for example. An n ⁺ type substrate 1 having a concentration of, for example, 1.0 × 10 ¹⁹ / cm ³ and a thickness of about 300 μm is prepared. On the surface of the n ⁺ type substrate 1, an n ⁻ type drift layer 2 made of SiC having an n type impurity concentration such as nitrogen of 3.0 × 10 ^{15 to} 2.0 × 10 ¹⁶ / cm ³ and a thickness of about 15 μm. Is prepared by epitaxial growth. Then, by ion implantation of p-type impurities such as boron or aluminum, the surface layer portion of the n ⁻ -type drift layer 2 has a thickness of about 1.0 × 10 ^{16 to} 2.0 × 10 ¹⁹ / cm ³ and a thickness of about 2.0 μm. A p-type base region 3 is formed.

[Step shown in FIG. 4B]
Subsequently, after forming a mask (not shown) made of, for example, LTO on the p-type base region 3, a mask is formed on the formation region of the n ⁺ -type source region 4 through a photolithography process. Open. Thereafter, n-type impurities (for example, nitrogen) are ion-implanted.

Further, after removing the previously used mask, a mask (not shown) is formed again, and the mask is opened on a region where the p ⁺ -type contact layer 5 is to be formed through a photolithography process. Thereafter, p-type impurities (for example, boron and aluminum) are ion-implanted.

Then, by activating the implanted ions, the n ⁺ -type source region 4 having an n-type impurity concentration (surface concentration) such as nitrogen of 1.0 × 10 ²¹ / cm ³ and a thickness of about 0.3 μm is formed. At the same time, the p ⁺ -type contact layer 5 having a p-type impurity concentration (surface concentration) such as boron or aluminum of 1.0 × 10 ²¹ / cm ³ and a thickness of about 0.3 μm is formed. Thereafter, the mask is removed.

[Step shown in FIG. 4 (c)]
After forming an etching mask (not shown) on the p-type base region 3, the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5, the etching mask is opened in a region where the trench 6 is to be formed. Specifically, an opening having the <11-20> direction as the off direction as a longitudinal direction is formed. And the trench 6 is formed by performing a trench etching process using an etching mask. Thus, the trench 6 is formed such that both side surfaces parallel to the longitudinal direction are surfaces parallel to the off direction, and one of the two end surfaces is a surface perpendicular to the off direction. The

  That is, as shown in FIG. 5, in the case where the trench 6 is formed on the SiC substrate whose surface has the <11-20> direction as the off-direction, based on the etching surface orientation dependency (11-20). A surface is easily formed, and the surface is a surface perpendicular to the off direction. Similarly, in the case where the trench 6 is formed on the SiC substrate whose surface is C-plane, the (-1-120) plane is likely to be formed on the basis of the surface orientation dependency of etching, and the plane is perpendicular to the off direction. It becomes. These surfaces are inclined with respect to the bottom surface of the trench 6 parallel to the surface of the SiC substrate. For example, when the off angle is 3.5 degrees, the angle θ formed by the tip surface with respect to the bottom surface of the trench 6 is about 87 degrees, and when the off angle is more than that, the angle θ is 87 degrees or less.

  In the trench etching process, the angle θ formed by one tip surface with respect to the bottom surface of the trench 6 is made smaller than the angle formed by the side surface of the trench 6 parallel to the longitudinal direction. That is, the side surface of the trench 6 where the channel is formed is substantially perpendicular to the substrate surface.

[Step shown in FIG. 4 (d)]
After removing the etching mask, an ion implantation mask (not shown) is formed, and a portion of the mask corresponding to the trench 6 is opened. Then, p-type impurities are ion-implanted from the direction perpendicular to the substrate. At this time, the p-type impurity is implanted into the bottom of the trench 6, but in addition to this, the p-type impurity is also implanted into one end face inclined with respect to the bottom surface of the trench 6 indicated by a broken line in FIG. Is done. On the other hand, the side surface of the trench 6 where the channel is formed is almost perpendicular to the substrate surface, so that the p-type impurity is hardly implanted and the p-type impurity is never made p-type. In this way, the electric field relaxation layer 7 having the bottom p-type layer 7a and the tip p-type layer 7b is formed.

Thereafter, the heat treatment for activating the implanted ions is performed alone, or the hydrogen etching is performed for both the trench etching and damage removal at the time of ion implantation and the activation heat treatment. Specifically, hydrogen etching is performed for 5 minutes by heat treatment in a hydrogen atmosphere under a reduced pressure of 1600 ° C. or more, for example, a high temperature hydrogen atmosphere of 1625 ° C. and 2.7 × 10 ⁴ Pa (200 Torr). As a result, the implanted ions are activated and the inner wall surface of the trench 6 is rounded, and the opening corners of the trench 6, the corners of the bottom and the convex portions of the side are rounded.

[Step shown in FIG. 4 (e)]
By performing a gate insulating film forming step by thermal oxidation or the like, the gate insulating film 8 is formed on the entire surface of the substrate including the inside of the trench 6. Specifically, the gate insulating film 8 is formed by gate oxidation (thermal oxidation) by a pyrogenic method using a wet atmosphere. Subsequently, after a polysilicon layer doped with n-type impurities is formed on the surface of the gate insulating film 8 at a temperature of about 440 nm, for example, at a temperature of 600 ° C., an etch back process or the like is performed, whereby the gate insulating film is formed in the trench 6. 8 and the gate electrode 9 are left.

After the interlayer insulating film 12 is formed, the interlayer insulating film 12 is patterned to form contact holes connected to the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5, and contact holes connected to the gate electrode 9 are formed. It is formed in another cross section. Subsequently, after depositing an electrode material so as to fill the contact hole, the source electrode 11 and the gate wiring are formed by patterning the electrode material.

Thereafter, although not shown, the drain electrode 12 is formed on the back surface side of the n ⁺ type substrate 1 to complete the MOSFET shown in FIG.

As described above, according to the SiC semiconductor device of the present embodiment, one of the electric field relaxation layers of the bottom portion and both end surfaces of the trench 6 is formed. For this reason, even if an electric field is applied between the drain and the gate when the MOSFET is turned off, the depletion layer at the PN junction between the electric field relaxation layer 7 and the n ⁻ type drift layer 2 greatly extends to the n ⁻ type drift layer 2 side. Therefore, a high voltage due to the influence of the drain voltage does not easily enter the gate insulating film 8. As a result, the electric field concentration in the gate insulating film 8, particularly the electric field concentration at the bottom of the trench 6 in the gate insulating film 8 can be relaxed, and the gate insulating film 8 is prevented from being destroyed. Is possible.

In the SiC semiconductor device having such a structure, the electric field relaxation layer 7 is made perpendicular to the substrate while one end surface of the trench 6 is a surface perpendicular to the off direction, that is, a surface inclined with respect to the substrate surface. This can be realized by ion implantation from the direction. That is, by performing ion implantation into the trench 6 from the vertical direction of the substrate, the bottom p-type layer 7a can be formed at the bottom of the trench 6, and at the same time, ion implantation is performed on a surface inclined with respect to the substrate surface. A p-type layer 7b can be formed. Therefore, the tip p-type layer 7b as a connection layer for connecting the bottom p-type layer 7a to the source electrode 11 through the p-type base region 3 and the p ⁺ -type contact layer 5 is formed simultaneously with the bottom p-type layer 7a. be able to. For this reason, it is not necessary to separately perform a step for forming the tip p-type layer 7b, and it is not necessary to perform complicated ion implantation such as oblique ion implantation. Thereby, it becomes possible to simplify the manufacturing process of the SiC semiconductor device.

(Other embodiments)
In the above embodiment, the p-type base region 3 is formed by ion-implanting p-type impurities into the surface layer portion of the n ⁻ -type drift layer 2, and the n-type impurities are ion-implanted into the surface layer portion of the p-type base region 3. The n ⁺ type source region 4 is used as a semiconductor substrate. On the other hand, the p-type base region 3 may be formed on the surface of the n ⁻ -type drift layer 2 by epitaxial growth, or the n ⁺ -type source region 4 may be formed on the surface of the p-type base region 3 by epitaxial growth. Alternatively, a triple epi substrate in which the n ⁻ type drift layer 2, the p type base region 3 and the n ⁺ type source region 4 are epitaxially grown on the surface of the n ⁺ type substrate 1 from the beginning may be used as the semiconductor substrate.

  In the above embodiment, the n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the p-channel in which the conductivity type of each component is inverted is described. The present invention can also be applied to a type of MOSFET. In the above description, a MOSFET having a trench gate structure has been described as an example. However, the present invention can also be applied to an IGBT having a similar trench gate structure. The IGBT only changes the conductivity type of the substrate 1 from the n-type to the p-type with respect to the above-described embodiment, and the other structures and manufacturing methods are the same as those in the above-described embodiment.

  In the above-described embodiment, an example in which the present invention is applied has been described. However, design changes can be made as appropriate. For example, in the above-described embodiment, an oxide film by thermal oxidation has been described as an example of the gate insulating film 8, but an oxide film or nitride film not by thermal oxidation may be included. Further, the process of forming the drain electrode 12 may be performed before the source electrode 11 is formed.

  Furthermore, in the above embodiment, when the trench 6 is formed using the off substrate whose main surface is the (0001) plane or the (000-1) plane and the off direction is the <11-20> direction. The front end face is made to be a {11-20} plane, that is, a plane perpendicular to the off direction. However, other off-substrates in the off direction may be used. Further, the case where the tip p-type layer 7b is formed over the entire area of one tip face of the trench 6 has been described. It should be.

  In addition, when indicating the orientation of a crystal, a bar (-) should be attached on a desired number, but there is a limitation on expression based on an electronic application. A bar shall be placed in front of the number.

1 n ⁺ type substrate 2 n ⁻ type drift layer 3 p type base region 4 n ⁺ type source region 5 p ⁺ type contact layer 6 trench 7 electric field relaxation layer 7a bottom p type layer 7b tip p type layer 8 gate insulating film 9 gate Electrode 11 Source electrode 12 Drain electrode

Claims (7)

A base region of the second conductivity type made of silicon carbide on the drift layer (2) made of silicon carbide formed on the main surface of the silicon carbide substrate (1) of the first or second conductivity type. (3) is formed, and a semiconductor substrate in which a first conductivity type source region (4) made of silicon carbide is formed on the base region is used, and a trench deeper than the base region ( 6) A gate insulating film (8) is formed within the gate insulating film and a gate electrode (9) is formed on the gate insulating film to form a trench gate structure. A method for manufacturing a silicon carbide semiconductor device comprising a semiconductor switching element having a source electrode (11) electrically connected and a drain electrode (12) electrically connected to the back surface of the silicon carbide substrate. ,
Preparing an off substrate having an off angle with the <11-20> direction as an off direction as the semiconductor substrate;
One tip surface of both tip surfaces in the longitudinal direction, which has a shape of a line having the off direction as a longitudinal direction by etching and a shape that reaches the drift layer through the source region and the base region A trench etching step of forming the trench so that the {11-20} plane is perpendicular to the off direction and inclined with respect to the main surface of the semiconductor substrate;
A second conductivity type impurity is implanted into the bottom of the trench and the one end surface by ion implantation of the second conductivity type impurity from a direction perpendicular to the main surface of the semiconductor substrate, and the bottom located at the bottom of the trench Forming a second conductivity type electric field relaxation layer (7) having a layer (7a) and a tip layer (7b) located on said one tip face. Device manufacturing method. In the step of preparing the semiconductor substrate, an off substrate in which the main surface is a (0001) plane and the off direction is a <11-20> direction is prepared,
2. The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein, in the trench etching step, the one end surface is a (11-20) surface. 3. In the step of preparing the semiconductor substrate, an off substrate in which the main surface is a (000-1) plane and the off direction is a <11-20> direction is prepared,
2. The method of manufacturing a silicon carbide semiconductor device according to claim 1 , wherein, in the trench etching step, the one end surface is a (−1-120) surface. In the trench etching step, an angle (θ) formed by the one end surface with respect to a bottom surface of the trench is made smaller than an angle formed by a side surface parallel to the longitudinal direction of the trench. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 3 . A first or second conductivity type substrate (1) made of silicon carbide and configured by an off substrate having an off angle with the <11-20> direction as an off direction;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate;
A base region (3) made of silicon carbide of the second conductivity type formed on the drift layer;
A source region (4) made of silicon carbide of the first conductivity type formed in the upper layer portion of the base region and having a higher impurity concentration than the drift layer;
It is a line shape with the off direction as the longitudinal direction, and a shape that reaches the drift layer through the source region and the base region, and is one of the distal end surfaces in the longitudinal direction { A trench (6) having an 11-20} plane perpendicular to the off direction and inclined with respect to the main surface of the semiconductor substrate;
A bottom layer (7a) formed at the bottom of the trench and formed at the bottom of the trench, and a tip layer (7b) formed at the tip of the trench. An electric field relaxation layer (7) made of silicon carbide of the second conductivity type constituted by:
A gate insulating film (8) formed on the inner wall surface of the trench on the electric field relaxation layer;
A gate electrode (9) formed on the gate insulating film in the trench;
A source electrode (11) electrically connected to the source region and the base region;
A drain electrode (12) formed on the back side of the substrate,
By controlling the voltage applied to the gate electrode, an inversion channel region is formed on the surface portion of the base region located on the side surface of the trench, and the source electrode and the drift layer are interposed through the source region and the drift layer. A silicon carbide semiconductor device comprising a semiconductor switching element having an inverted trench gate structure in which a current flows between the drain electrodes. The substrate is an off substrate in which the main surface is a (0001) plane and the off direction is a <11-20> direction,
The silicon carbide semiconductor device according to claim 4 , wherein the one end surface is a (11-20) surface. The substrate is an off substrate in which the main surface is a (000-1) plane and the off direction is a <11-20> direction,
The silicon carbide semiconductor device according to claim 4 , wherein the one end surface is a (−1−120) surface.

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