JP5790573B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device having a vertical semiconductor switching element and a method for manufacturing the same.

  An SiC semiconductor device having a MOS semiconductor switching element is used in a state where a voltage nearly 10 times that of a silicon device is applied since the breakdown electric field strength of SiC is 10 times that of silicon. Therefore, there is a problem that an electric field having a strength 10 times that of the silicon device is applied to the gate insulating film disposed below the gate electrode, and the dielectric breakdown occurs. This problem is conspicuous when a MOSFET having a trench gate structure with an increased channel density is applied as a semiconductor switching element. Electric field concentration occurs at the corner of the trench for forming the trench gate structure, and gate insulation is caused. The film is easily destroyed.

  In order to solve such a problem, Patent Document 1 proposes that the gate insulating film is formed thick at the bottom of the trench constituting the trench gate structure. Patent Document 2 proposes a structure in which a p-type layer is formed by ion-implanting p-type impurities below the bottom (bottom surface) of a trench constituting the trench gate structure. Further, Patent Document 2 proposes a structure in which a p-type deep layer is disposed so as to intersect with the longitudinal direction of the trench so that the bottom of the p-type deep layer is positioned deeper than the bottom of the trench. Yes.

  Thus, by thickening the gate insulating film at the bottom of the trench, forming a p-type layer at the bottom of the trench, or forming a p-type deep layer, the electric field concentration at the bottom of the trench can be reduced, and the gate It is possible to prevent the insulating film from being broken.

JP 9-199724 A Japanese Patent No. 4640439

  However, there is a demand for a structure that can further reduce electric field concentration than the structures proposed in Patent Documents 1 and 2 above. Moreover, the manufacturing process of the SiC semiconductor device having the above structure is complicated. In other words, the manufacturing of the SiC semiconductor device disclosed in Patent Document 1 requires a step of depositing an oxide film by a CVD method or the like in order to increase the thickness of the gate insulating film. In addition, in the manufacture of the SiC semiconductor device shown in Patent Document 2, p-type impurities are ion-implanted to form a p-type layer at the bottom of the trench, or a p-type layer is formed only to form a p-type deep layer. A step of epitaxial growth or a step of ion implantation of p-type impurities is required.

  In view of the above points, it is a first object of the present invention to provide a SiC semiconductor device including a semiconductor switching element having a structure capable of further reducing electric field concentration. It is a second object of the present invention to make it possible to manufacture a SiC semiconductor device including a semiconductor switching element having a structure capable of further reducing electric field concentration by a simpler manufacturing method.

  In order to achieve the above object, according to the first aspect of the present invention, the voltage applied to the gate electrode (8) is controlled so that the surface of the base region (3) facing the gate electrode is inverted. An inversion type semiconductor switching element configured to form a channel region and pass a current between a source electrode (11) and a drain electrode (12) through a source region (4) and a drift layer (2). The silicon carbide semiconductor device is provided with a deep layer (9) of a second conductivity type that is formed deeper than the base region and tapers as the depth increases.

  In this way, the tip of the deep layer formed deeper than the base region is tapered. Thereby, when breakdown occurs, it can be generated not at the bottom of the gate insulating film but at the tip of the deep layer, and it is possible to prevent the gate insulating film from being broken.

Such a structure, to ensure that preferably when applied to the semiconductor switching element is a SiC semiconductor device provided in the trench gate structures described 請 Motomeko 1, deep layer is formed deeper than the trench (6) Thus, the above effect can be obtained.

According to the invention of claim 5 , a trench is formed in the semiconductor substrate, and a sub-trench (6a) that protrudes downward from the bottom of the trench at both corners of the bottom of the trench and tapers as the depth increases is formed. And a step of rounding the inner wall of the trench by hydrogen etching and forming a second conductivity type deep layer by migrating the second conductivity type silicon carbide on the surface of the base region to fill the sub-trench. It is characterized by including.

  In this way, the sub-trench is formed when the trench is formed, and the deep layer can be formed by hydrogen etching when the inner wall of the trench is rounded. Thereby, a SiC semiconductor device in which deep layers are provided at both corners at the bottom of the trench can be manufactured without adding a process compared to the related art.

According to the sixth aspect of the present invention, the inner wall of the trench is rounded by a step of forming a taper shape that tapers as the trench becomes deeper with respect to the semiconductor substrate, and the second conductivity of the surface of the base region is formed by hydrogen etching. And a step of forming a second conductivity type deep layer by embedding type silicon carbide and embedding the tips of the trenches.

  In this way, the trench can be tapered when the trench is formed, and the deep layer can be formed by hydrogen etching when the inner wall of the trench is rounded. Thereby, a SiC semiconductor device in which deep layers are provided at both corners at the bottom of the trench can be manufactured without adding a process compared to the related art.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a perspective sectional view of a SiC semiconductor device including an n-channel type inversion MOSFET having a trench gate structure according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing the apex angle of p-type deep layer 9 in a MOSFET provided in the SiC semiconductor device shown in FIG. 1. It is the figure which showed the relationship between the vertex angle when applying 1200V as a drain voltage, and electric field strength. FIG. 3 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 1. It is a perspective sectional view of a SiC semiconductor device provided with n channel type inversion type MOSFET of a trench gate structure concerning a 2nd embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 5. It is a perspective sectional view of a SiC semiconductor device provided with n channel type inversion type MOSFET of a trench gate structure concerning a 2nd embodiment of the present invention. FIG. 8 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device shown in FIG. 7.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. Here, an n-channel type inversion MOSFET having a trench gate structure will be described as a semiconductor switching element provided in the SiC semiconductor device.

As shown in FIG. 1, an inverted MOSFET is formed in the SiC semiconductor device. A MOSFET having a plurality of cells is configured by arranging MOSFETs having the same structure as the MOSFET shown in FIG. Specifically, an n ⁺ type substrate 1 made of SiC is used as the semiconductor substrate, and MOSFETs are configured by forming each component of the MOSFET on the n ⁺ type substrate 1.

The n ⁺ -type substrate 1 has an n-type impurity concentration such as nitrogen of 1.0 × 10 ¹⁹ / cm ³ and a thickness of about 300 μm. On the surface of the n ⁺ type substrate 1, an n ⁻ type made of SiC having an n type impurity concentration of, eg, nitrogen of 3.0 × 10 ^{15 to} 2.0 × 10 ¹⁶ / cm ³ and a thickness of about 10 to ¹⁵ μm. A drift layer 2 is formed. The impurity concentration of the n ⁻ type drift layer 2 may be constant in the depth direction, but the concentration distribution is inclined, and the n ⁺ type substrate 1 side of the n ⁻ type drift layer 2 is n ⁺ type. It is also possible to make the concentration higher than the side away from the substrate 1. In this way, since the internal resistance of the n ⁻ type drift layer 2 can be reduced, the on-resistance can be reduced.

A p-type base region 3 is formed in the surface layer portion of the n ⁻ -type drift layer 2, and an n ⁺ -type source region 4 and a p ⁺ -type contact layer 5 are formed in an upper layer portion of the p-type base region 3. Has been.

The p-type base region 3 has a p-type impurity concentration such as boron or aluminum of, for example, 1.0 × 10 ^{16 to} 2.0 × 10 ¹⁹ / cm ³ and a thickness of about 2.0 μm. The n ⁺ -type source region 4 is configured such that the n-type impurity concentration (surface concentration) such as nitrogen in the surface layer portion is, for example, 1.0 × 10 ²¹ / cm ³ and the thickness is about 0.3 μm. The p ⁺ -type contact layer 5 has a p-type impurity concentration (surface concentration) such as boron or aluminum in the surface layer portion of, for example, 1.0 × 10 ²¹ / cm ³ and a thickness of about 0.3 μm. The n ⁺ -type source region 4 is disposed on both sides of a trench gate structure described later, and the p ⁺ -type contact layer 5 is provided on the opposite side of the trench gate structure with the n ⁺ -type source region 4 interposed therebetween.

One direction is a longitudinal direction so as to penetrate the p-type base region 3 and the n ⁺ -type source region 4 and reach the n ⁻ -type drift layer 2, for example, a width of 0.5 to 2.0 μm and a depth of A trench 6 having a thickness of 2.0 μm or more (for example, 2.4 μm) is formed. The p-type base region 3 and the n ⁺ -type source region 4 described above are arranged so as to be in contact with the side surface of the trench 6, and the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5 extend along the longitudinal direction of the trench 6. It is extended.

The inner wall surface of the trench 6 is covered with a gate insulating film 7, and the inside of the trench 6 is filled with the gate electrode 8 made of doped Poly-Si formed on the surface of the gate insulating film 7. . The gate insulating film 7 is formed by thermally oxidizing the inner wall surface of the trench 6, and is a portion of the p-type base region 3 sandwiched between the n ⁺ -type source region 4 and the n ⁻ -type drift layer 2. Formed on the entire inner wall surface of the trench 6 including the surface, the gate electrode 8 is disposed thereon. For example, the thickness of the gate insulating film 7 is about 100 nm on both the side surface side and the bottom side of the trench 6. In this way, a trench gate structure is configured.

Further, a p-type deep layer 9 is formed at a position below the p-type base region 3 in the n ⁻ -type drift layer 2. In the case of the present embodiment, the p-type deep layer 9 is formed at a position away from the trench 6, has a sharp shape that tapers off as it becomes deeper, and is connected to the p-type base region 3 to thereby form the p-type base region. 3 is fixed at the same potential.

In the case of the present embodiment, the p-type deep layer 9 has a triangular shape with a line shape having the same direction as the longitudinal direction of the trench gate structure as a longitudinal direction, and a plurality of the p-type deep layers 9 are arranged in parallel with the trench gate structure. Are laid out. The p-type deep layer 9 is formed deeper than the bottom of the trench 6, and the depth from the surface of the n ⁻ -type drift layer 2 is about 2.6 to 3.0 μm, for example (the bottom of the p-type base region 3 And the p-type impurity concentration of boron or aluminum is, for example, 1.0 × 10 ¹⁶ / cm ^{3 to} 2.0 × 10 ¹⁹ / cm ^3. Yes.

A source electrode 11 and a gate wiring (not shown) are formed on the surface of the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5 and the surface of the gate electrode 8 via an interlayer insulating film 10. The source electrode 11 and the gate wiring are composed of a plurality of metals (for example, Ni / Al, etc.), and at least n-type SiC (specifically, the n ⁺ -type source region 4 and the gate electrode 8 in the case of n doping) The portion in contact with n-type SiC is made of a metal capable of ohmic contact with n-type SiC, and the portion in contact with at least p-type SiC (specifically, p ⁺ -type contact layer 5 or gate electrode 8 in the case of p-doping) is p-type. It is made of a metal capable of ohmic contact with SiC. The source electrode 11 and the gate wiring are electrically insulated by being formed on the interlayer insulating film 10, and the source electrode 11 is connected to the n ⁺ type source region through the contact hole formed in the interlayer insulating film 10. 4 and the p ⁺ -type contact layer 5 are in electrical contact, and the gate wiring is in electrical contact with the gate electrode 8.

Then, on the back side of the n ⁺ -type substrate 1 n ⁺ -type substrate 1 and electrically connected to the drain electrode 12 are formed. With such a structure, an n-channel inversion type MOSFET having a trench gate structure is formed.

  Such an inverted MOSFET having a trench gate structure operates as follows. First, in the state before the gate voltage is applied to the gate electrode 8, the inversion layer is not formed in the p-type base region 3. Therefore, even if a positive voltage is applied to the drain electrode 12, electrons cannot reach the p-type base region 3 from the n-type source region 4, and no current flows between the source electrode 11 and the drain electrode 12. Not flowing.

Next, when off (gate voltage = 0 V, drain voltage = 650 V, source voltage = 0 V), a reverse bias is applied even if a voltage is applied to the drain electrode 12, so the p-type base region 3 and the n ⁻ -type drift layer A depletion layer spreads between two. At this time, since the concentration of the p-type base region 3 is higher than that of the n ⁻ -type drift layer 2, the depletion layer extends almost to the n ⁻ -type drift layer 2 side. For example, when the impurity concentration of the p-type base region 3 is 10 times the impurity concentration of the n ⁻ -type drift layer 2, the p-type base region 3 extends about 0.7 μm to the p-type base region 3 side and about 7 to the n ⁻ -type drift layer 2 side. Although it extends by 0.0 μm, since the thickness of the p-type base region 3 is 2.0 μm, which is larger than the extension amount of the depletion layer, punch-through can be prevented. Since the depletion layer is wider than in the case of the drain 0 V, the region that behaves as an insulator further spreads, so that no current flows between the source electrode 11 and the drain electrode 12.

In addition, since the gate voltage is 0 V, an electric field is also applied between the drain and the gate. For this reason, electric field concentration can also occur at the bottom of the gate insulating film 7. However, since the p-type deep layer 9 is deeper than the trench 6, the depletion layer at the PN junction between the p-type deep layer 9 and the n ⁻ -type drift layer 2 is on the n ⁻ -type drift layer 2 side. As a result, the high voltage due to the influence of the drain voltage hardly enters the gate insulating film 7. Even if breakdown occurs, the electric field strength is highest at the deepest tip position of the p-type deep layer 9, and breakdown can be preferentially generated at that position. Therefore, it is possible to alleviate the electric field concentration in the gate insulating film 7, particularly the electric field concentration at the bottom of the trench 6 in the gate insulating film 7, and even if breakdown occurs, the gate insulating film 7 It can be generated not at the bottom but at the tip of the p-type deep layer 9. This can prevent the gate insulating film 7 from being broken.

On the other hand, when ON (gate voltage = 20 V, drain voltage = 1 V, source voltage = 0 V), 20 V is applied as the gate voltage to the gate electrode 8, so that it is in contact with the trench 6 in the p-type base region 3. A channel is formed on the surface. For this reason, electrons injected from the source electrode 11 pass through the channel formed in the p-type base region 3 from the n ⁺ -type source region 4 and then reach the n ⁻ -type drift layer 2. As a result, a current can flow between the source electrode 11 and the drain electrode 12.

  As described above, in the SiC semiconductor device including the MOSFET having the trench gate structure according to this embodiment, the tip of the p-type deep layer 9 formed deeper than the trench 6 has a tapered shape. Thereby, when breakdown occurs, it can be generated not at the bottom of the gate insulating film 7 but at the tip position of the p-type deep layer 9, and it is possible to prevent the gate insulating film 7 from being broken. Become.

The tip shape of the p-type deep layer 9 may be a tapered shape, but it is preferable that the apex angle of the tapered portion is 90 ° or less. That is, when the angle formed by both sides of the p-type deep layer 9 when cut in the direction perpendicular to the longitudinal direction of the p-type deep layer 9 is a vertex angle as shown in FIG. When examined by experiment, the result shown in FIG. 3 was obtained. In this experiment, the curvature radius at the bottom of the p-type deep layer 9 is calculated as 5 nm.

As shown in this figure, when the vertex angle is 90 ° or less, the electric field strength at the tip position of the p-type deep layer 9 when the drain voltage is 1200 V is as high as 4.0 MV / cm. I understand. When the vertex angle exceeds 90 °, the electric field strength at the tip position of the p-type deep layer 9 gradually decreases. Therefore, by setting the apex angle of the p-type deep layer 9 to be 90 ° or less, the electric field strength at the tip position of the p-type deep layer 9 can be increased, and the break can be more reliably performed at that position. It becomes possible to cause down. Therefore, it becomes possible to prevent the gate insulating film 7 from being destroyed more reliably.

  Next, a manufacturing method of the MOSFET having the trench gate structure shown in FIG. 1 will be described with reference to FIG.

[Step shown in FIG. 4 (a)]
First, an n ⁺ -type substrate 1 having an n-type impurity concentration such as nitrogen of 1.0 × 10 ¹⁹ / cm ³ and a thickness of about 300 μm is prepared. On the surface of the n ⁺ type substrate 1, an n ⁻ type drift layer made of SiC having an n type impurity concentration such as nitrogen of 3.0 × 10 ^{15 to} 2.0 × 10 ¹⁶ / cm ³ and a thickness of about 10 to ¹⁵ μm. 2 is grown epitaxially.

[Steps shown in FIGS. 4B and 4C]
After a mask 20 made of, for example, an oxide film is formed on the surface of the n ⁻ type drift layer 2, the mask 20 is opened or recessed in a region where the p-type deep layer 9 is to be formed through a photolithography process. At this time, the side surface of the opening or the recess of the mask 20 is tapered. In order to make the side surface of the concave portion have a tapered shape, the mask 20 may be patterned by isotropic etching with reduced anisotropy. Then, etching is performed using this mask 20 to form a recess 2 a on the surface of the n ⁻ -type drift layer 2. At this time, like the p-type deep layer 9, the recess 2 a is formed in a sharp shape that tapers as the depth increases.

  That is, the mask 20 is also removed by etching at a predetermined selection ratio with respect to SiC. However, since the side surface of the opening or recess of the mask 20 has a tapered shape, the opening area increases as etching proceeds. Gradually increases. For this reason, although the etching area is in a small state at the initial stage of etching, the etching area becomes larger as the etching progresses, and finally, as the shape of the recess 2a becomes deeper as shown in FIG. It becomes a pointed shape.

  In addition, it is preferable to make the opening of the mask 20 small or to form a concave portion having a triangular cross section in the mask 20 so that the tip of the concave portion 2a is as sharp as possible. However, even if the tip of the recess 2a is flat to some extent and has a trapezoidal cross section, the breakdown can be preferentially generated at the tip of the p-type deep layer 9, so that the above effect can be obtained. .

[Step shown in FIG. 4 (d)]
A p-type impurity layer having a p-type impurity concentration such as boron or aluminum of about 1.0 × 10 ^{16 to} 2.0 × 10 ¹⁹ / cm ³ and a thickness of about 2.0 μm is formed on the surface of the n ⁻ type drift layer 2. Are epitaxially grown to form the p-type deep layer 9 and the p-type base region 3.

[Step shown in FIG. 4 (e)]
Subsequently, after the n ⁺ type source region 4 is epitaxially grown on the p type base region 3, a mask (not shown) made of LTO or the like is formed, and then through a photolithography process, p ⁺ A mask is opened on a region where the mold contact layer 5 is to be formed. Thereafter, p-type impurities (for example, boron and aluminum) are ion-implanted.

Alternatively, after forming a mask (not shown) made of LTO or the like, for example, a mask (not shown) is opened on a region where the n ⁺ -type source region 4 is to be formed through a photolithography process. Thereafter, n-type impurities (for example, nitrogen) are ion-implanted. Further, after removing the previously used mask, a mask (not shown) is formed again, and the mask is opened on a region where the p ⁺ -type contact layer 5 is to be formed through a photolithography process. Thereafter, p-type impurities (for example, boron and aluminum) are ion-implanted.

Then, by activating the implanted ions, the n ⁺ -type source region 4 having an n-type impurity concentration (surface concentration) such as nitrogen of 1.0 × 10 ²¹ / cm ³ and a thickness of about 0.3 μm is formed. At the same time, the p ⁺ -type contact layer 5 having a p-type impurity concentration (surface concentration) such as boron or aluminum of 1.0 × 10 ²¹ / cm ³ and a thickness of about 0.3 μm is formed. Thereafter, the mask is removed.

[Step shown in FIG. 4 (f)]
After forming an etching mask (not shown) on the p-type base region 3, the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5, the etching mask is opened in a region where the trench 6 is to be formed. Then, after performing etching using an etching mask, a sacrificial oxidation process or a hydrogen etching process is performed as necessary, for example, a width of 0.5 to 2.0 μm and a depth of 2.0 μm or more. A trench 6 (for example, 2.4 μm) is formed. Thereafter, the etching mask is removed.

[Step shown in FIG. 4 (g)]
By performing the gate insulating film forming step, the gate insulating film 7 is formed on the entire surface of the substrate including the inside of the trench 6. Specifically, the gate insulating film 7 is formed by gate oxidation (thermal oxidation) by a pyrogenic method using a wet atmosphere. Subsequently, a polysilicon layer doped with an n-type impurity is formed on the surface of the gate insulating film 7 at a temperature of about 440 nm, for example, at a temperature of 600.degree. 7 and the gate electrode 8 are left.

Although the subsequent steps are the same as in the prior art and are not shown, after the interlayer insulating film 10 is formed, the interlayer insulating film 10 is patterned to be connected to the n ⁺ type source region 4 and the p ⁺ type contact layer 5. A contact hole is formed and a contact hole connected to the gate electrode 8 is formed in another cross section. Subsequently, after depositing an electrode material so as to fill the contact hole, the source electrode 11 and the gate wiring are formed by patterning the electrode material. Further, the drain electrode 12 is formed on the back surface side of the n ⁺ type substrate 1. Thereby, the MOSFET shown in FIG. 1 is completed.

As described above, the p-type deep layer 9 is formed by epitaxially growing the p-type base layer 3 after forming the recess 2a on the surface of the n ⁻ -type drift layer 2 first. It can be formed simultaneously with the forming process. For this reason, it becomes possible to make the formation process of the p-type base region 3 and the p-type deep layer 9 common, and it becomes possible to simplify the manufacturing process.

(Second Embodiment)
A second embodiment of the present invention will be described. The SiC semiconductor device of the present embodiment is obtained by changing the configuration of the p-type deep layer 9 with respect to the first embodiment, and is otherwise the same as that of the first embodiment, and therefore different from the first embodiment. Only will be described.

  As shown in FIG. 5, in this embodiment, the p-type deep layer 9 is formed below the bottom surface of the trench 6 in the lower part of the trench gate structure. The p-type deep layer 9 is formed at both corners of the trench 6 and has a sharp shape that tapers as the depth increases. Even with the p-type deep layer 9 having such a structure, when breakdown occurs, breakdown can be preferentially generated at the tip of the p-type deep layer 9. For this reason, the effect similar to 1st Embodiment can be acquired.

  Next, a manufacturing method of the MOSFET having the trench gate structure shown in FIG. 5 will be described with reference to FIG. However, since this manufacturing method is the same as that of the first embodiment except for the step of forming the p-type base region 9, only the parts different from the first embodiment are shown in FIG.

[Step shown in FIG. 6A]
First, after performing the step shown in FIG. 4A shown in the first embodiment, the step of forming the recess 2a on the surface of the n ⁻ type drift layer 2 as shown in FIGS. 4B and 4C. The p-type base region 3 is formed on the n ⁻ -type drift layer 2 as in the step shown in FIG. At this time, the p-type base region 3 can be formed by epitaxial growth, but may be formed by ion implantation of p-type impurities. Subsequently, as in the step shown in FIG. 4E, an n ⁺ type source region 4 and a p ⁺ type contact layer 5 are formed.

[Step shown in FIG. 6B]
A trench 6 is formed by trench etching as in the step shown in FIG. At this time, for example, sub-trench 6 a having a depth of 0.1 μm is formed at both corners of trench 6. Since it is generally well known that the sub-trench 6a is formed in the trench etching, the sub-trench 6a can be formed by applying such etching conditions. If the etching conditions are employed such that the etching rate is higher in the vicinity of the side wall of the trench 6 than in the central position of the trench 6, the sub-trench 6a can be formed deeper.

[Step shown in FIG. 6 (c)]
Hydrogen etching is performed by heat treatment in a hydrogen atmosphere under a reduced pressure of 1600 ° C. or more, for example, a high temperature hydrogen atmosphere at 1625 ° C. and 2.7 × 10 ⁴ Pa (200 Torr). By this hydrogen etching, the inner wall surface of the trench 6 is rounded, and the opening entrance and corner of the trench 6 are rounded and the damage of the trench etching is removed. At this time, the p-type SiC on the surface of the p-type base region 3 is migrated to the bottom of the trench 6. As a result, p-type SiC enters the sub-trench 6 a and the p-type deep layer 9 is formed at the bottom of the trench 6.

  After this, the MOSFET shown in FIG. 5 is completed by performing the steps after FIG. 4G described in the first embodiment. As described above, after the trench 6 is formed under the condition that the sub-trench 6a is formed, the sub-trench 6a is filled with p-type SiC by hydrogen etching that also serves as a rounding process for the inner wall of the trench 6 to form the p-type deep layer 9. Can be formed. Thereby, the SiC semiconductor device concerning this embodiment can be manufactured without an additional process compared with the past.

(Third embodiment)
A third embodiment of the present invention will be described. The SiC semiconductor device of the present embodiment is also the same as the first embodiment except that the configuration of the p-type deep layer 9 is changed with respect to the first embodiment. Only will be described.

  As shown in FIG. 7, also in this embodiment, the p-type deep layer 9 is formed below the bottom surface of the trench 6 in the lower part of the trench gate structure. The p-type deep layer 9 is formed at the center of the trench 6 and has a sharp shape that tapers as the depth increases. Even with the p-type deep layer 9 having such a structure, when breakdown occurs, breakdown can be preferentially generated at the tip of the p-type deep layer 9. For this reason, the effect similar to 1st Embodiment can be acquired.

  Next, a manufacturing method of the MOSFET having the trench gate structure shown in FIG. 7 will be described with reference to FIG. However, since this manufacturing method is the same as that of the first embodiment except for the step of forming the p-type base region 9, only the parts different from the first embodiment are shown in FIG.

[Step shown in FIG. 8 (a)]
First, by performing the same steps as FIG. 6 shown in the second embodiment (a), n on the surface of the n ⁺ -type substrate 1 ^- -type drift layer 2 and the p-type base region 3, further n ⁺ A type source region 4 and a p ⁺ type contact layer 5 are formed.

[Step shown in FIG. 8B]
A trench 6 is formed by trench etching as in the step shown in FIG. At this time, the tip of the trench 6 is tapered. In order to make the tip of the trench 6 taper, a method of performing isotropic etching while reducing anisotropy at the beginning of etching, and then performing etching while increasing the anisotropy is performed. Should be adopted.

[Step shown in FIG. 8C]
Hydrogen etching is performed by heat treatment in a hydrogen atmosphere under a reduced pressure of 1600 ° C. or more, for example, a high temperature hydrogen atmosphere at 1625 ° C. and 2.7 × 10 ⁴ Pa (200 Torr). By this hydrogen etching, the inner wall surface of the trench 6 is rounded, and the opening entrance and corner of the trench 6 are rounded and the damage of the trench etching is removed. At this time, the p-type SiC on the surface of the p-type base region 3 is migrated to the bottom of the trench 6. Thereby, p-type SiC enters the tapered portion at the tip of the bottom of the trench 6, and the p-type deep layer 9 is formed at the bottom of the trench 6.

  After this, the MOSFET shown in FIG. 7 is completed by performing the steps after FIG. 4G described in the first embodiment. As described above, after the trench 6 is formed in a tapered shape at the time of forming the trench 6, p-type SiC is formed on the tapered portion at the tip of the trench 6 by hydrogen etching that also serves as a rounding process for the inner wall of the trench 6. The p-type deep layer 9 can be formed by embedding. Thereby, the SiC semiconductor device concerning this embodiment can be manufactured without an additional process compared with the past.

(Other embodiments)
In each of the above-described embodiments, an example in which the present invention is applied has been described. However, a design change or the like can be made as appropriate. For example, in each of the above-described embodiments, an oxide film by thermal oxidation is given as an example of the gate insulating film 8, but an oxide film or nitride film not by thermal oxidation may be included. Further, the process of forming the drain electrode 12 may be performed before the source electrode 11 is formed.

  Further, in each of the embodiments described above, the case where the p-type deep layer 9 is formed in a line shape having a triangular cross section and having the longitudinal direction as the longitudinal direction of the trench gate structure is not necessarily a linear shape. . For example, the p-type deep layer 9 may be a polygonal pyramid shape such as a triangular pyramid, a quadrangular pyramid, or a hexagonal pyramid, or a conical shape. It may be a polygonal frustum shape such as a table or a truncated cone shape. In that case, the shape or the shape of the p-type deep layer 9 in which the opening or recess of the mask 20 for forming the recess 2a is to be formed (for example, a triangle is a triangular pyramid), and the side surfaces constituting each side are tapered. What is necessary is just to make it.

In the first embodiment, the inversion type MOSFET having the trench gate structure has been described as an example. However, the p type deep layer 9 having the structure of the first embodiment is also applied to the planar inversion type MOSFET. Can be provided. In the case of a planar inverting MOSFET, a gate insulating film 7 is formed on the surface of the p-type base region 3 in a portion sandwiched between the n ⁺ -type source region 4 and the n ⁻ -type drift layer 2, and a gate is formed thereon. The electrode 8 is formed. In that case, the p-type deep layer 9 may be formed deeper than the p-type base region 3 and have a shape that tapers as the depth increases.

  In each of the above-described embodiments, an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. The present invention can also be applied to a channel type MOSFET. In the above description, the MOSFET has been described as an example. However, the present invention can be applied to an IGBT having a similar structure. The IGBT only changes the conductivity type of the substrate 1 from the n-type to the p-type with respect to the above-described embodiments, and the other structures and manufacturing methods are the same as those of the above-described embodiments.

1 n ⁺ type substrate 2 n ⁻ type drift layer 3 p type base region 4 n ⁺ type source region 5 p ⁺ type contact layer 6 trench 7 gate insulating film 8 gate electrode 9 p type deep layer 11 source electrode 12 drain electrode

Claims (6)

A first or second conductivity type substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate;
A base region (3) made of silicon carbide of the second conductivity type formed on the drift layer;
A source region (4) made of silicon carbide of the first conductivity type formed in the upper layer portion of the base region and having a higher impurity concentration than the drift layer;
A contact region (5) formed of an upper layer portion of the base region and made of silicon carbide of the second conductivity type having a higher concentration than the base layer;
A gate insulating film (7) formed on the surface of the base region sandwiched between the source region and the drift layer; a gate electrode (8) formed on the gate insulating film;
A deep layer (9) of the second conductivity type formed deeper than the base region and tapered toward the depth;
A source electrode (11) electrically connected to the base region via the source region and the contact region;
A drain electrode ( 12 ) formed on the back side of the substrate,
By controlling the voltage applied to the gate electrode, an inversion channel region is formed on the surface portion of the base region facing the gate electrode, and the source region is provided via the source region and the drift layer. An inversion type semiconductor switching element configured to pass a current between an electrode and the drain electrode ,
The gate insulating film and the gate electrode are formed from the surface of the source region to deeper than the base region, and are formed in the trench (6) to constitute a trench gate structure.
The deep layer is formed deeper than the trench and is formed at both corners of the bottom of the trench, and the vertex angle of the cross section of the deep layer is 90 ° or less. . A first or second conductivity type substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate;
A base region (3) made of silicon carbide of the second conductivity type formed on the drift layer;
A source region (4) made of silicon carbide of the first conductivity type formed in the upper layer portion of the base region and having a higher impurity concentration than the drift layer;
A contact region (5) formed of an upper layer portion of the base region and made of silicon carbide of the second conductivity type having a higher concentration than the base layer;
A gate insulating film (7) formed on the surface of the base region sandwiched between the source region and the drift layer; a gate electrode (8) formed on the gate insulating film;
A deep layer (9) of the second conductivity type formed deeper than the base region and tapered toward the depth;
A source electrode (11) electrically connected to the base region via the source region and the contact region;
A drain electrode ( 12 ) formed on the back side of the substrate,
By controlling the voltage applied to the gate electrode, an inversion channel region is formed on the surface portion of the base region facing the gate electrode, and the source region is provided via the source region and the drift layer. An inversion type semiconductor switching element configured to pass a current between an electrode and the drain electrode ,
The gate insulating film and the gate electrode are formed from the surface of the source region to deeper than the base region, and are formed in the trench (6) to constitute a trench gate structure.
The deep layer is formed deeper than the trench and is formed at the center of the bottom of the trench, and the vertex angle of the cross section of the deep layer is 90 ° or less . The deep layer is a cross-sectional triangular or trapezoidal, silicon carbide according to claim 1 or 2, characterized in that the longitudinal direction in the same direction of the trench gate structure is formed in a line shape whose longitudinal direction Semiconductor device. The deep layer, pyramid, truncated pyramid, the silicon carbide semiconductor device according to claim 1 or 2, characterized in that either a conical or frustoconical. A base region of the second conductivity type made of silicon carbide on the drift layer (2) made of silicon carbide formed on the main surface of the silicon carbide substrate (1) of the first or second conductivity type. (3) is used, and a semiconductor substrate in which a source region (4) of the first conductivity type made of silicon carbide is formed on the base region is used,
A gate insulating film (7) is formed in the trench (6) deeper than the base region and a gate electrode (8) is formed on the gate insulating film, thereby forming a trench gate structure.
A source electrode (11) electrically connected to the base region via the source region or the second conductivity type region and a drain electrode (12) electrically connected to the back surface of the silicon carbide substrate; A method for manufacturing a silicon carbide semiconductor device comprising a semiconductor switching element having:
Forming the trench with respect to the semiconductor substrate, and forming a sub-trench (6a) that protrudes downward from the bottom of the trench at both corners of the bottom of the trench and tapers as the depth increases.
The inner wall of the trench is rounded by hydrogen etching, and the second conductivity type silicon carbide on the surface of the base region is migrated to fill the sub-trench to form the second conductivity type deep layer (9). And a process for manufacturing the silicon carbide semiconductor device. A base region of the second conductivity type made of silicon carbide on the drift layer (2) made of silicon carbide formed on the main surface of the silicon carbide substrate (1) of the first or second conductivity type. (3) is used, and a semiconductor substrate in which a source region (4) of the first conductivity type made of silicon carbide is formed on the base region is used,
A gate insulating film (7) is formed in the trench (6) deeper than the base region and a gate electrode (8) is formed on the gate insulating film, thereby forming a trench gate structure.
A source electrode (11) electrically connected to the base region via the source region or the second conductivity type region and a drain electrode (12) electrically connected to the back surface of the silicon carbide substrate; A method for manufacturing a silicon carbide semiconductor device comprising a semiconductor switching element having:
Forming the taper shape to be tapered as the trench becomes deeper with respect to the semiconductor substrate;
The inner wall of the trench is rounded by hydrogen etching, and the second conductivity type silicon carbide on the surface of the base region is migrated to bury the tip of the trench, thereby forming a second conductivity type deep layer (9). And a process for manufacturing the silicon carbide semiconductor device.

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