JP2017092364A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves a highly reliable withstand voltage structure without increase in chip size; and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device comprises: a silicon carbide base substance 40 with a surface where a stepped part 21 obtained by forming an edge termination region 20 to be lower than an active region 10; an ntype silicon carbide layer 2 exposed from a bottom face 21a of the stepped part 21; a trench 22 selectively provided in the ntype silicon carbide layer 2 at a portion exposed from the bottom face 21a of the stepped part 21 in a depth direction at a depth of not reaching an nsilicon carbide substrate 1; a first JTE 31 which is provided inside the trench 22 and away from the trench 22 and contacts an outermost first p type base region 3 at the bottom face 21a of the stepped part 21; a second JTE region 32 provided along an inner wall of the trench 22; and an insulation film 33 which is embedded inside the trench 22 and covered with the second JTE region 32. A JTE structure 30 of the first and second JTE regions 31, 32 and the insulation film 33 embedded inside the trench 22 compose a withstand voltage structure.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltage and large current. There are multiple types of power semiconductor devices such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used according to the application. It has been.

  For example, a bipolar transistor or IGBT has a higher current density than a MOSFET and can increase the current, but cannot be switched at high speed. Specifically, the bipolar transistor is limited in use at a switching frequency of about several kHz, and the IGBT is limited in use at a switching frequency of about several tens of kHz. On the other hand, a power MOSFET has a lower current density than a bipolar transistor or IGBT and is difficult to increase in current, but can perform a high-speed switching operation up to several MHz.

  In the market, there is a strong demand for power semiconductor devices having both high current and high speed, and IGBTs and power MOSFETs have been focused on improving them, and are currently being developed to almost the material limit. For this reason, a semiconductor material that replaces silicon has been studied from the viewpoint of a power semiconductor device, and silicon carbide as a semiconductor material capable of producing (manufacturing) a next-generation power semiconductor device excellent in low on-voltage, high-speed characteristics, and high-temperature characteristics. (SiC) is attracting attention (for example, see Non-Patent Document 1 below).

  Silicon carbide is a chemically stable semiconductor material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. Silicon carbide is also expected as a semiconductor material that can sufficiently reduce the on-resistance because the maximum electric field strength is one digit or more larger than that of silicon. Such a feature of silicon carbide similarly applies to other semiconductors having a wider band gap than silicon (hereinafter referred to as a wide band gap semiconductor) such as gallium nitride (GaN). For this reason, by using a wide band gap semiconductor, it is possible to increase the breakdown voltage of the semiconductor device (see, for example, Non-Patent Document 2 below).

  In such a high withstand voltage semiconductor device, a high voltage is applied not only to the active region in which the element structure is formed and the current flows when it is in the on state, but also to the edge termination region that surrounds the active region and holds the withstand voltage, The electric field concentrates on the edge termination region. The breakdown voltage of the high breakdown voltage semiconductor device is determined by the impurity concentration, thickness, and electric field strength of the semiconductor, and the breakdown resistance determined by the characteristic features of the semiconductor is equal from the active region to the edge termination region. For this reason, there is a possibility that an electric load exceeding the breakdown tolerance is applied to the edge termination region due to electric field concentration in the edge termination region, leading to destruction. That is, the breakdown voltage of the high breakdown voltage semiconductor device is limited by the breakdown tolerance in the edge termination region.

  As a device that improves the breakdown voltage of the entire high breakdown voltage semiconductor device by relaxing or dispersing the electric field in the edge termination region, a junction termination (JTE) structure or a field limiting ring (FLR) structure is used. A device in which a pressure-resistant structure such as the above is arranged in the edge termination region is known (for example, see Patent Documents 1 and 2 below). In Patent Document 1 below, a floating metal electrode in contact with the FLR is arranged as a field plate (FP: Field Plate), and the charge generated in the edge termination region is released to improve the reliability.

The breakdown voltage structure of a conventional high voltage semiconductor device will be described by taking a MOSFET having a JTE structure as an example. FIG. 5 is a cross-sectional view showing the structure of a conventional semiconductor device. The conventional semiconductor device shown in FIG. 5 has a semiconductor substrate (hereinafter referred to as a silicon carbide substrate (semiconductor chip)) 140 made of silicon carbide, an active region 110, an edge termination region 120 surrounding the periphery of the active region 110, Is provided. Silicon carbide substrate 140, n ⁺ -type supporting substrate made of silicon carbide (hereinafter referred to as n ⁺ -type silicon carbide substrate) on 101 of the front side, made of silicon carbide n ^- type semiconductor layer (hereinafter, n ^- And a p-type semiconductor layer (hereinafter referred to as a p-type silicon carbide layer) 104 made of silicon carbide.

In active region 110, a MOS gate (insulated gate made of metal-oxide film-semiconductor) structure is provided on the front surface (surface on the p-type silicon carbide layer 104 side) side of silicon carbide substrate 140. The p-type silicon carbide layer 104 is removed over the entire area of the edge termination region 120, and a step 121 is formed on the front surface of the silicon carbide substrate 140 so that the edge termination region 120 is lower than the active region 110 (recessed on the drain side). The n ⁻ -type silicon carbide layer 102 is exposed on the bottom surface 121 a of the step 121. Further, the edge termination region 120 has a plurality of p ⁻ type low concentration regions (two in this case, p ⁻ type and p ⁻ type from the inside) whose impurity concentration is lower as they are arranged on the outer side (chip end side). JTE structure 130 arranged adjacent to each other is provided.

A p ⁻ type low concentration region (hereinafter referred to as a first JTE region) 131 and a p ⁻ type low concentration region (hereinafter referred to as a second JTE region) 132 are respectively formed on the step 121 of the n ⁻ type silicon carbide layer 102. It is selectively provided in the portion exposed to the bottom surface 121a. The first JTE region 131 is in contact with the outermost p-type base region 103 at the bottom surface 121 a of the step 121. A drain electrode 115 is provided in contact with the back surface of silicon carbide substrate 140 (the back surface of n ⁺ -type silicon carbide substrate 101). Reference numerals 105 to 109 and 111 to 114 denote an n ⁺ type source region, a p ⁺ type contact region, an n type JFET region, a gate insulating film, a gate electrode, a field oxide film, an interlayer insulating film, a source electrode, and a passivation film, respectively. .

In the MOSFET having the configuration shown in FIG. 5, when a positive voltage is applied to the drain electrode 115 with respect to the source electrode 113 and a voltage lower than the threshold voltage is applied to the gate electrode 109, the p-type base region Since the pn junction between 104a and the n-type JFET region 107 is reverse-biased, the reverse breakdown voltage of the active region is secured and no current flows. The p-type base region 104 a is a part of the p-type silicon carbide layer 104 other than the n ⁺ -type source region 105 and the p ⁺ -type contact region 106.

On the other hand, when a voltage higher than the threshold voltage is applied to the gate electrode 109, an n-type inversion layer (channel) is formed in the surface layer of the p-type base region 104a immediately below the gate electrode 109 (drain side). The Thereby, a current flows through the path of n ⁺ type silicon carbide substrate 101, n ⁻ type silicon carbide layer 102, n type JFET region 107, surface inversion layer of p type base region 104 a and n ⁺ type source region 105. As described above, the known MOSFET switching operation can be performed by controlling the gate voltage.

In the MOSFET having the configuration shown in FIG. 5, when a voltage is applied, the depletion layer extends outward from the pn junction between the p-type base region 103 and the n ⁻ -type drift layer, and the first and second JTEs It extends to both areas 131 and 132. The n ⁻ type drift layer is a part of the n ⁻ type silicon carbide layer 102 other than the p type base region 103 and the first and second JTE regions 131 and 132. The breakdown voltage in the edge termination region is ensured at the pn junction between the first and second JTE regions 131 and 132 and the n ⁻ type drift layer.

As another high breakdown voltage semiconductor device, a groove reaching the n ⁻ -type drift region through the outer end (edge termination region side) end of the p-type base region extending from the active region to the edge termination region in the depth direction Has been proposed (see, for example, Patent Document 3 (FIG. 13) below). In Patent Document 3 below, an n-type channel stopper is provided at the boundary between the n ⁻ -type drift region and the insulating film at the bottom surface of the groove provided in the edge termination region, and the p-type base is formed by the p-type region provided along the inner wall of the groove. The region and the n-type channel stopper are connected.

JP 2010-50147 A JP 2006-165225 A US Patent Application Publication No. 2014/167143

K. Shenai, two others, Optim Semiconductors for High-Power Electronics, I Triple E Transactions on Electron Devices (IEEEs TransD) September, Vol. 36, No. 9, p. 1811-1823 By B. Jayant Baliga, Silicon Carbide Power Devices (USA), World Scientific Publishing Co. (World Science Publishing Co.), 30th March, 200 p. . 61

However, in the breakdown voltage structure shown in Patent Documents 1 and 2, the width of the edge termination region 120 (the length from the boundary between the active region 110 and the edge termination region 120 to the end of the chip) is as long as 100 μm or more. There is a problem that the size increases. In the breakdown voltage structure shown in Patent Document 3, an n-type channel stopper is provided at the bottom of the groove at the boundary with the insulating film of the n ⁻ -type drift region, and the n-type channel stopper is cut at that position. Thus, there is a problem that the pressure-resistant structure must be determined only by the side surface of the groove.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a highly reliable breakdown voltage structure and a method for manufacturing the semiconductor device without increasing the chip size in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics. An active region through which a main current flows and a termination region surrounding the active region are provided on a first conductivity type semiconductor substrate made of a semiconductor having a wider band gap than silicon. The termination region is provided on a front surface of the semiconductor substrate, and a plurality of second conductivity type semiconductor regions provided in a concentric circle surrounding the periphery of the active region and with a lower impurity concentration as it is disposed on the outer side. And an insulating film embedded in the groove. The outermost second conductivity type semiconductor region of the plurality of second conductivity type semiconductor regions is provided along the inner wall of the groove and covers the insulating film.

  In the semiconductor device according to the present invention, in the above-described invention, a step is formed on the front surface of the semiconductor substrate in which the termination region is lower than the active region. The groove and the second conductive type semiconductor region are provided on a surface formed in the termination region by the step.

  In the semiconductor device according to the present invention, in the above-described invention, the active region is selectively provided with a first semiconductor region of a second conductivity type on the front surface side of the semiconductor substrate. The first semiconductor region extends to a surface formed in the termination region by the step, and is in contact with the innermost second conductive semiconductor region among the plurality of second conductive semiconductor regions. And

  The semiconductor device according to the present invention further has the following characteristics in the above-described invention. A second semiconductor region of a first conductivity type is selectively provided inside the first semiconductor region. A gate insulating film is provided in contact with a region of the first semiconductor region between the second semiconductor region and the semiconductor substrate. A gate electrode is provided on the opposite side of the first semiconductor region across the gate insulating film. The first electrode is in contact with the first semiconductor region and the second semiconductor region. The second electrode is in contact with the back surface of the semiconductor substrate.

  The semiconductor device according to the present invention further has the following characteristics in the above-described invention. A trench reaching the semiconductor substrate through the second semiconductor region and the first semiconductor region is provided. A trench gate structure in which the gate electrode is provided inside the trench through the gate insulating film is provided. A second conductive type third semiconductor region is provided to cover the bottom surface of the trench.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the semiconductor having a wider band gap than silicon is silicon carbide.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention is provided on a first conductivity type semiconductor substrate made of a semiconductor having a wider band gap than silicon. A method for manufacturing a semiconductor device comprising an active region and a termination region surrounding the periphery of the active region, having the following characteristics. First, a first step of forming a groove provided on the front surface of the semiconductor substrate in the termination region is performed. Next, a second step of forming a plurality of second conductivity type semiconductor regions provided in a concentric circle surrounding the periphery of the active region and with a lower impurity concentration as it is arranged outside is performed. Next, a third step of filling an insulating film in the trench is performed. In the second step, first, a first forming step of forming the outermost second conductive type semiconductor region among the plurality of second conductive type semiconductor regions along the inner wall of the groove is performed. Next, an insulating film mask is formed on the front surface of the semiconductor substrate. The insulating film mask has an opening corresponding to a formation region of another second conductivity type semiconductor region among the plurality of second conductivity type semiconductor regions. A 2nd formation process is performed. Next, a third forming step of forming the other second conductivity type semiconductor region by ion implantation is performed using the insulating film mask as a mask. In the third step, after the third forming step, a portion other than a portion embedded in the groove of the insulating film mask is removed, and the insulating film mask remaining in the groove is removed from the insulating film. And

  In the semiconductor device manufacturing method according to the present invention, in the above-described invention, after the first forming step, at least one of forming an element structure on a surface layer of the front surface of the semiconductor substrate in the active region. A fourth step of selectively forming the diffusion region. In the fourth step, a fourth forming step of forming another insulating film mask having an opening corresponding to the formation region of the diffusion region on the front surface of the semiconductor substrate; and the other insulating film mask As a mask, a process including a fifth forming step of forming the diffusion region by ion implantation is repeated as many times as the number of the diffusion regions. In the third step, each time the fourth step is performed, the other insulating film remaining in the groove is removed by removing a portion other than the portion embedded in the groove of the other insulating film mask. The mask is the insulating film, and the inside of the groove is completely filled with the insulating film.

  According to the above-described invention, when a voltage is applied, the depletion layer extending from the active region side spreads to the plurality of second conductivity type semiconductor regions, so that the concentration of the electric field in the active region can be suppressed. According to the above-described invention, the outermost second conductive type semiconductor region is provided along the inner wall of the groove, and the insulating film is embedded in the groove so that the second is applied when a voltage is applied. An electric field can be shared between the conductive semiconductor region and the insulating film inside the trench. As a result, a high breakdown voltage can be maintained with a breakdown voltage structure of about several μm composed of the JTE structure and the insulating film inside the trench. In addition, since the electric field is shared between the second conductive type semiconductor region and the insulating film in the trench, the electric field in the second conductive type semiconductor region is relaxed, and the breakdown voltage distribution in the termination region can be stabilized.

  According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to realize a highly reliable breakdown voltage structure that ensures a stable breakdown voltage distribution without increasing the chip size.

1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment; 6 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment; FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device according to a third embodiment. It is a characteristic view which shows the pressure | voltage resistant characteristic of the semiconductor device concerning an Example. It is sectional drawing which shows the structure of the conventional semiconductor device.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. In the present specification, in the Miller index notation, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index.

(Embodiment 1)
The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the first embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described using a planar gate MOSFET as an example. FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device according to the first embodiment. As shown in FIG. 1, the silicon carbide semiconductor device according to the first embodiment includes an active region 10 on a semiconductor substrate 40 (hereinafter referred to as a silicon carbide substrate (semiconductor substrate (semiconductor chip))) made of silicon carbide. And an edge termination region 20 surrounding the periphery of the active region 10. The active region 10 is a region through which current flows when in the on state. The edge termination region 20 is a region that relaxes the electric field on the substrate front surface side of the drift region and maintains a withstand voltage.

A silicon carbide substrate 40 is formed on an n ⁺ type support substrate (n ⁺ type silicon carbide substrate) 1 made of silicon carbide on an n ⁻ type semiconductor layer (n ⁻ type silicon carbide layer) 2 made of silicon carbide. And a p-type semiconductor layer (p-type silicon carbide layer) 4 made of silicon carbide. N ⁺ type silicon carbide substrate 1 functions as a drain region. In the active region 10, a p-type base region (first semiconductor region) is formed on the surface layer of the n ⁻ -type silicon carbide layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side (base surface side). 3) is selectively provided. The outermost (chip end side) p-type base region 3 extends from the active region 10 side to a bottom surface 21a of a step 21 described later, and a part of the p-type base region 3 is exposed to the bottom surface 21a of the step 21. The bottom surface 21 a of the step 21 is a front surface of the silicon carbide substrate 40 newly formed in the edge termination region 20 by forming the step 21. The exposure to the bottom surface 21a of the step 21 means that the step 21 is disposed so as to be in contact with the field oxide film 11 described later. A portion of n ⁻ -type silicon carbide layer 2 other than p-type base region 3 and first and second JTE regions 31 and 32 described later is a drift region.

A p-type silicon carbide layer 4 is provided on the surface of n ⁻ -type silicon carbide layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 so as to cover p-type base region 3. The impurity concentration of p-type silicon carbide layer 4 may be lower than the impurity concentration of p-type base region 3. Inside the p-type silicon carbide layer 4, an n ⁺ -type source region (second semiconductor region) 5 and a p ⁺ -type contact region 6 are selectively provided in a portion facing the p-type base region 3 in the depth direction. Is provided. Inside p-type silicon carbide layer 4, an n-type semiconductor region 7 that penetrates p-type silicon carbide layer 4 in the depth direction and reaches n ⁻ -type silicon carbide layer 2 is provided. n-type semiconductor region 7 is disposed apart from the n ⁺ -type source region 5 with respect to the n ⁺ -type source region 5 to the opposite side of the p ⁺ -type contact region 6.

A portion (hereinafter referred to as a second p-type base region (first semiconductor region)) 4a of the p-type silicon carbide layer 4 other than the n ⁺ -type source region 5, the p ⁺ -type contact region 6 and the n-type semiconductor region 7 is It functions as a base region together with a p-type base region (hereinafter referred to as a first p-type base region) 3. An n-type semiconductor region (hereinafter referred to as an n-type JFET region) 7 is a JFET (Junction FET) region sandwiched between adjacent base regions, and functions as a drift region together with the n ⁻ -type silicon carbide layer 2. By making the impurity concentration of the n-type JFET region 7 sandwiched between adjacent base regions higher than the impurity concentration of the n ⁻ -type silicon carbide layer 2, the JFET resistance is reduced.

Of the 2p-type base region 4a, on a surface of a portion held with n ⁺ -type source region 5 and the n-type JFET region 7, a gate insulating film 8 over the n-type JFET region 7 of n ⁺ -type source region 5 A gate electrode 9 is provided therethrough. The first and second p-type base regions 3 and 4a, the n ⁺ -type source region 5, the p ⁺ -type contact region 6, the gate insulating film 8 and the gate electrode 9 are formed on the front surface of the silicon carbide substrate 40 (p-type silicon carbide). A MOS gate structure is formed on the side of the layer 4 side. Source electrode (first electrode) 13 is in contact with n ⁺ -type source region 5 and p ⁺ -type contact region 6 and is electrically insulated from gate electrode 9 by interlayer insulating film 12.

The p-type silicon carbide layer 4 is removed over the entire area of the edge termination region 20, and a step 21 is formed on the front surface of the silicon carbide substrate 40 so that the edge termination region 20 is lower than the active region 10 (recessed on the drain side). Is formed. That is, n ⁻ type silicon carbide layer 2 is exposed at bottom surface 21 a of step 21. The side wall 21b of the step 21 is located at the boundary between the active region 10 and the edge termination region 20, for example. The side wall 21b of the step 21 is located between the bottom surface 21a of the step 21 and the substrate front surface on the active region 10 side with respect to the step 21, and has an obtuse angle θ with respect to the bottom surface 21a of the step 21. This is the front surface of silicon carbide substrate 40 having a degree. The side wall 21 b of the step 21 may be located slightly closer to the edge termination region 20 than the boundary between the active region 10 and the edge termination region 20. The p-type silicon carbide layer 4 is exposed on the side wall 21b of the step. When step 21 is deeper than p-type silicon carbide layer 4, p-type silicon carbide layer 4 and first p-type base region 3 are exposed at side wall 21 b of step 21.

The bottom surface 21a and side wall 21b of the step 21 and the boundary (hereinafter referred to as the bottom surface corner portion of the step 21) 21c are on the drain side with respect to the boundary between the p-type silicon carbide layer 4 and the outermost first p-type base region 3. And it is located in the depth position which does not penetrate the outermost first p-type base region 3. That is, the bottom corner portion 21c of the step 21 is covered with the first p-type base region 3 at the outermost side at least on the drain side. A groove 22 is selectively provided in a depth of the n ⁻ type silicon carbide layer 2 exposed at the bottom surface 21a of the step 21 so as not to reach the n ⁺ type silicon carbide substrate 1 in the depth direction. The groove 22 is disposed away from the bottom corner 21 c of the step 21. The step 21 and the groove 22 are arranged in a substantially annular plane layout surrounding the periphery of the active region 10.

Further, the edge termination region 20 includes a plurality of p ⁻ type low concentration regions (second conductivity type semiconductor regions: two here, p from the inner side (active region 10 side)) whose impurity concentration is lower as they are arranged on the outer side. ^- type, p ^- JTE structure 30 is provided with a mold and to reference numeral 31, 32) arranged adjacently. The JTE structure 30 is arranged in a substantially annular plane layout surrounding the periphery of the active region 10. The p ⁻ type low concentration region (hereinafter referred to as the first JTE region) 31 is disposed between the bottom corner portion 21c of the step 21 and the groove 22 and separated from the bottom corner portion 21c and the groove 22 of the step 21, and The bottom surface 21a of the step 21 is exposed. The first JTE region 31 is in contact with the outermost first p-type base region 3 on the bottom surface 21 a of the step 21.

The p 2 ⁻ type low concentration region (hereinafter referred to as the second JTE region) 32 is provided along the inner wall (side wall and bottom surface) of the groove 22 and is exposed on the entire inner wall of the groove 22. The second JTE region 32 is in contact with the first JTE region 31 at a portion provided along the inner side wall of the groove 22. Second JTE region 32 has a predetermined thickness t2 that does not contact n ⁺ -type silicon carbide substrate 1 at a portion provided along the bottom surface of groove 22. The thickness t2 of the second JTE region 32 may be smaller than the thickness t1 of the first JTE region 31 (t2 <t1). The first and second JTE regions 31 and 32 are arranged in a concentric planar layout. An insulating film 33 is embedded in the trench 22. That is, the insulating film 33 is covered with the second JTE region 32.

  The first and second JTE regions 31 and 32 and the insulating film 33 form a breakdown voltage structure in the edge termination region 20. The breakdown voltage of the edge termination region 20 is set by variously changing the depth d of the groove 22 and the impurity concentration of the second JTE region 32. Specifically, the breakdown voltage of the edge termination region 20 increases as the depth d of the groove 22 increases. For example, when the depth d of the groove 22 is about 1 μm, the withstand voltage of the edge termination region 20 is secured about 1200V. In addition, the withstand voltage of the edge termination region 20 increases as the impurity concentration of the second JTE region 32 decreases. The deeper the depth d of the groove 22, the higher the withstand voltage of the edge termination region 20 due to the impurity concentration of the second JTE region 32.

For example, when the depth d of the groove 22 is about 1 μm, the withstand voltage of the edge termination region 20 is about 1200 V as described above, and the withstand voltage difference of the edge termination region 20 due to the impurity concentration of the second JTE region 32 hardly occurs. . On the other hand, for example, when the depth d of the trench 22 is about 6 μm, the withstand voltage of the edge termination region 20 is about 1600 V when the impurity concentration of the second JTE region 32 is 1.50 × 10 ¹⁶ / cm ^3. On the other hand, when the impurity concentration of the second JTE region 32 is 6.00 × 10 ¹⁶ / cm ³ , the withstand voltage of the edge termination region 20 exceeds 2200V. The width (width between the inner and outer side walls) w of the groove 22 may be about 5 μm, for example.

Interlayer insulating film 12 extends from the active region 10 side on the front surface of silicon carbide substrate 40 in edge termination region 20 to cover first and second JTE regions 31 and 32 and insulating film 33. Field oxide film 11 may be provided between the front surface of silicon carbide substrate 40 and interlayer insulating film 12 in edge termination region 20. Further, a protective film 14 made of polyimide, such as a passivation film, is provided on the interlayer insulating film 12 in the edge termination region 20. The protective film 14 has a function of preventing discharge. The protective film 14 may extend on the end portion of the source electrode 13. Drain electrode 15 is provided on the back surface of silicon carbide substrate 40 (the back surface of n ⁺ -type silicon carbide substrate 1).

Next, the method for manufacturing the semiconductor device according to the first embodiment will be described by taking as an example the case of manufacturing a MOSFET with a breakdown voltage class of 1200 V, for example. First, a silicon carbide single crystal n ⁺ -type silicon carbide substrate (semiconductor wafer) 1 doped with an n-type impurity (dopant) such as nitrogen (N) so as to have an impurity concentration of 2.0 × 10 ¹⁹ / cm ³ , for example. Prepare. The front surface of n ⁺ -type silicon carbide substrate 1 may be, for example, a (000-1) plane having an off angle of about 4 degrees in the <11-20> direction. Next, on the front surface of the n ⁺ type silicon carbide substrate 1, an n ⁻ type silicon carbide layer 2 doped with an n type impurity such as nitrogen so as to have an impurity concentration of 1.0 × 10 ¹⁶ / cm ³ , for example. Is epitaxially grown to a thickness of 10 μm, for example.

Next, first p-type base region 3 is selectively formed on the surface layer of n ⁻ -type silicon carbide layer 2 by photolithography and ion implantation. In this ion implantation, a p-type impurity (dopant) such as aluminum (Al) may be implanted so that the impurity concentration of the first p-type base region 3 is, for example, 1.0 × 10 ¹⁸ / cm ³ . For example, the first p-type base region 3 may be arranged in a striped planar layout, and the width (stripe width) and depth may be 13 μm and 0.5 μm, respectively. Next, the p-type silicon carbide layer 4 doped with p-type impurities such as aluminum on the surface of the n ⁻ -type silicon carbide layer 2 to have an impurity concentration of 2.0 × 10 ¹⁶ / cm ³ , for example, Epitaxial growth is performed with a thickness of 5 μm.

Through the steps so far, a silicon carbide substrate 40 is manufactured, in which n ⁻ type silicon carbide layer 2 and p type silicon carbide layer 4 are sequentially laminated on the front surface of n ⁺ type silicon carbide substrate 1. Next, the n-type JFET region 7 is selectively formed by inverting the conductivity type of a part of the p-type silicon carbide layer 4 by photolithography and ion implantation. In this ion implantation, an n-type impurity such as nitrogen may be implanted so that the impurity concentration of the n-type JFET region 7 is, for example, 5.0 × 10 ¹⁶ / cm ³ . The width and depth of the n-type JFET region 7 may be, for example, 2.0 μm and 0.6 μm, respectively. The n-type JFET region 7 may be formed after the formation of the second JTE region 32 described later.

Next, a step 21 is formed at a depth of, for example, 0.7 μm on the front surface of the silicon carbide substrate 40 by photolithography and etching, and the p-type silicon carbide layer 4 is removed over the entire edge termination region 20. The n ⁻ type silicon carbide layer 2 is exposed. Next, groove 22 is selectively formed in the portion exposed to bottom surface 21a of step 21 of n ⁻ type silicon carbide layer 2 by photolithography and etching. Next, the second JTE region 32 is formed along the inner wall of the groove 22 by photolithography and ion implantation. The ion implantation for forming the second JTE region 32 is performed, for example, from a direction oblique to the front surface of the silicon carbide substrate 40 and from a direction orthogonal to the front surface of the silicon carbide substrate 40. These ion implantations may be combined.

Next, the process of forming a mask for ion implantation by photolithography and etching, ion implantation using the mask for ion implantation, and removal of the mask for ion implantation is repeated under different ion implantation conditions. Thus, the first JTE region 31, the n ⁺ type source region 5 and the p ⁺ type contact region 6 are formed. The order in which the first JTE region 31, the n ⁺ type source region 5 and the p ⁺ type contact region 6 are formed can be variously changed. As an ion implantation mask used for each ion implantation for forming the first JTE region 31, the n ⁺ type source region 5 and the p ⁺ type contact region 6, for example, an insulating film (insulating film mask) is used. The thickness of the insulating film serving as the ion implantation mask may be about 1.5 μm, for example. When the ion implantation mask is removed, the portion embedded in the groove 22 of the ion implantation mask is left without being removed. The ion implantation mask remaining inside the groove 22 becomes the insulating film 33. It is preferable to set the thickness of each ion implantation mask such that the total thickness of the ion implantation mask for each ion implantation is such that the inside of the groove 22 can be completely filled with the insulating film 33.

Next, a heat treatment (annealing) for activating the first p-type base region 3, the n ⁺ -type source region 5, the p ⁺ -type contact region 6, the n-type JFET region 7 and the first and second JTE regions 31 and 32 is performed, for example. It is performed at a temperature of about 1620 ° C. for about 2 minutes. Next, for example, the front surface of the silicon carbide substrate 40 is thermally oxidized by heat treatment at a temperature of about 1000 ° C. in a mixed gas atmosphere of oxygen (O ₂ ) gas and hydrogen (H ₂ ) gas, for example, about 100 nm. The gate insulating film 8 is formed with a thickness of Thereby, the entire front surface of silicon carbide substrate 40 is covered with gate insulating film 8.

Next, a polysilicon (poly-Si) layer doped with, for example, phosphorus (P) is formed on the gate insulating film 8. Next, this polysilicon layer is selectively removed by patterning, leaving a portion on the surface of the second p-type base region 4a sandwiched between the n ⁺ -type source region 5 and the n-type JFET region 7. . The polysilicon layer remaining on the gate insulating film 8 becomes the gate electrode 9. Even if the polysilicon layer to be the gate electrode 9 is left over the surface of the portion of the second p-type base region 4 a sandwiched between the n ⁺ -type source region 5 and the n-type JFET region 7 and over the n-type JFET region 7. Good.

Next, an interlayer insulating film 12 made of, for example, phosphorous glass (PSG) is formed on the entire front surface of the silicon carbide substrate 40 so as to cover the gate electrode 9 with a thickness of, for example, 1.0 μm. (Form. Next, the interlayer insulating film 12 and the gate insulating film 8 are patterned by photolithography and etching to form contact holes, and the n ⁺ type source region 5 and the p ⁺ type contact region 6 are exposed. Field oxide film 11 may be formed on the front surface of silicon carbide substrate 40 in edge termination region 20 after formation of gate electrode 9 and before formation of interlayer insulating film 12.

  Next, the interlayer insulating film 12 is planarized by heat treatment (reflow). Next, source electrode 13 is formed on the front surface of silicon carbide substrate 40 so as to be embedded in the contact hole, for example, by sputtering. Next, the source electrode 13 is patterned by photolithography and etching. The thickness of the source electrode 13 may be 5 μm, for example. The material of the source electrode 13 may be aluminum (Al—Si) containing silicon (Si) at a rate of 1%, for example.

Next, a nickel (Ni) film, for example, is formed as the drain electrode 15 on the back surface of the silicon carbide substrate 40 (the back surface of the n ⁺ -type silicon carbide substrate 1). Then, for example, an ohmic junction between the drain electrode 15 and the silicon carbide substrate 40 is formed by heat treatment at a temperature of 970 ° C. Next, for example, a titanium (Ti) film, a nickel film, and a gold (Au) film are sequentially formed on the surface of the nickel film as the drain electrode 15. Next, protective film 14 is formed on the front surface of silicon carbide substrate 40. Thereafter, the silicon carbide substrate 40 is cut (diced) into chips to obtain individual pieces, thereby completing the MOSFET shown in FIG.

As described above, according to the first embodiment, by arranging the JTE structure in the edge termination region, the pn between the p-type base region and the n ⁻ -type drift layer when a voltage is applied is applied. A depletion layer extending from the junction extends to a plurality of JTE regions constituting the JTE structure. For this reason, the depletion layer can be expanded in the edge termination region earlier than when the JTE structure is not disposed in the edge termination region, and the concentration of the electric field in the active region can be suppressed. Further, according to the first embodiment, the second JTE region is provided along the inner wall of the groove, and the insulating film is embedded in the groove, whereby the second JTE is formed in the insulating film inside the groove when a voltage is applied. A potential is transmitted from the region, and the electric field can be shared between the first and second JTE regions and the insulating film inside the trench. As a result, a high breakdown voltage can be maintained with a breakdown voltage structure of about several μm composed of the JTE structure and the insulating film inside the trench. That is, a high breakdown voltage can be realized and an increase in chip size can be prevented. In addition, since the electric field is shared between the first and second JTE regions and the insulating film in the trench, the electric field in the first and second JTE regions is relaxed, and the breakdown voltage distribution in the edge termination region can be stabilized. Therefore, it is possible to obtain a highly reliable breakdown voltage structure that ensures a stable breakdown voltage distribution without increasing the chip size. In addition, according to the first embodiment, the breakdown voltage structure composed of the JTE structure and the insulating film inside the trench is arranged in the edge termination region, and when the voltage is applied, the outermost unit cell ( By allowing an avalanche current (current rapidly increased by avalanche) to flow through the MOSFET in the functional unit of the element, avalanche can be reliably generated in the active region. Thereby, the electric field in the edge termination region is relaxed, and a stable breakdown voltage distribution can be maintained. Further, according to the first embodiment, since no n-type region such as an n-type channel stopper region is provided along the inner wall of the groove as in, for example, Patent Document 3, the side surface and the bottom surface of the groove are used. A structure can be constructed.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 2 is a cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is obtained by applying the semiconductor device according to the first embodiment to a trench gate type MOSFET.

Specifically, as shown in FIG. 2, in Embodiment 2, silicon carbide substrate 40 is formed by laminating n ⁻ type silicon carbide layer 2 on the front surface of n ⁺ type silicon carbide substrate 1. . A p-type base region 41 is provided on the surface layer of n ⁻ -type silicon carbide layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side. A portion of n ⁻ -type silicon carbide layer 2 other than p-type base region 41 and first and second JET regions 31 and 32 is a drift region. The p-type base region 41 extends from the active region 10 side to the bottom surface 21 a of the step 21, and a part of the p-type base region 41 is exposed on the bottom surface 21 a of the step 21. The p-type base region 41 is in contact with the first JET region 31 at the bottom surface 21 a of the step 21. The impurity concentration of the p-type base region 41 may be the same as the impurity concentration of the first p-type base region of the first embodiment, for example.

An n ⁺ type source region 42 and a p ⁺ type contact region 43 are selectively provided inside the p type base region 41, respectively. A trench 44 that penetrates n ⁺ type source region 42 and p type base region 41 and reaches n ⁻ type silicon carbide layer 2 is provided. Inside the trench 44, a gate insulating film 45 is provided along the inner wall of the trench 44, and a gate electrode 46 is provided inside the gate insulating film 45. These p-type base region 41, n ⁺ -type source region 42, p ⁺ -type contact region 43, trench 44, gate insulating film 45 and gate electrode 46 constitute a trench gate type MOS gate structure. The depth of the step 21 is shallower than the thickness of the p-type base region 41, for example. The breakdown voltage structure of the edge termination region 20 is the same as the breakdown voltage structure of the first embodiment.

The manufacturing method of the semiconductor device according to the second embodiment is that the trench gate type MOS gate structure is formed in the manufacturing method of the semiconductor device according to the first embodiment. At this time, the p-type base region 41 may be formed before the step 21 is formed, or may be formed after the step 21 is formed. The first JTE region 31, the n ⁺ -type source region 42 and the p ⁺ -type contact region 43 may be formed after the formation of the second JTE region 32, and the formation order can be variously changed. The trench 44, the gate insulating film 45, and the gate electrode 46 are formed by a general method after the formation of the n ⁻ -type silicon carbide layer 2 and before the formation of the interlayer insulating film 12, for example.

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
Next, the structure of the semiconductor device according to the third embodiment will be described. FIG. 3 is a cross-sectional view illustrating the structure of the semiconductor device according to the third embodiment. The semiconductor device according to the third embodiment is different from the semiconductor device according to the second embodiment in that a p-type region (third semiconductor region) 47 is provided so as to cover the bottom surface of the trench 44 constituting the MOS gate structure. It is. Specifically, p type region 47 is selectively provided inside n ⁻ type silicon carbide layer 2 so as to cover the bottom surface of trench 44 and away from p type base region 41. The p-type region 47 may be provided from the bottom surface of the trench 44 to the bottom surface corner portion so as to cover the boundary between the bottom surface and the side wall of the trench 44 (the bottom surface corner portion of the trench).

  The semiconductor device manufacturing method according to the third embodiment may be performed by adding a step of forming the p-type region 47 to the semiconductor device manufacturing method according to the second embodiment. Specifically, for example, after the formation of the trench 44 and before the formation of the gate insulating film 45, an etching mask for forming the trench 44 is used to form p from the direction perpendicular to the front surface of the silicon carbide substrate 40. The p-type region 47 may be formed by ion implantation of a type impurity.

  As described above, according to the third embodiment, the same effect as in the first and second embodiments can be obtained. Further, according to the third embodiment, when the present invention is applied to a trench gate type MOS gate structure, it is possible to prevent the electric field from concentrating on the bottom surface and the bottom corner portion of the trench constituting the MOS gate structure. it can. This can prevent the breakdown voltage of the active region from being lowered.

(Example)
Next, the width w and depth d of the groove 22 were verified. FIG. 4 is a characteristic diagram illustrating a withstand voltage characteristic of the semiconductor device according to the example. The horizontal axis of FIG. 4 indicates the depth d of the groove 22, and the vertical axis indicates the breakdown voltage of the edge termination region 20. The annotation in FIG. 4 shows the impurity concentration (second JTE concentration) of the second JTE region 32. In accordance with the structure of the semiconductor device according to the first embodiment described above, a plurality of MOSFETs having different depths d of the trenches 22 and different impurity concentrations in the second JTE regions 32 were produced (hereinafter referred to as examples). In the embodiment, the JTE structure 30 is a double zone JTE structure including first and second JTE concentrations 31 and 32. The width w of the groove 22 was 5 μm. The depth d of the groove 22 is variously changed in the range of 1 μm to 6 μm. The impurity concentration of the second JTE region 32 is variously changed in the range of 1.50 × 10 ¹⁶ / cm ^{3 to} 6.00 × 10 ¹⁶ / cm ³ . The results of measuring the breakdown voltage of the edge termination region 20 in these samples are shown in FIG.

  From the results shown in FIG. 4, it was confirmed that the withstand voltage of the edge termination region 20 can be increased as the depth d of the groove 22 is increased. Further, it was confirmed that the breakdown voltage of the edge termination region 20 can be increased as the impurity concentration of the second JTE region 32 is decreased. It was confirmed that the withstand voltage difference of the edge termination region 20 due to the impurity concentration of the second JTE region 32 increases as the depth d of the groove 22 increases.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, in each of the above-described embodiments, the MOSFET is described as an example. However, the present invention is not limited to the above-described embodiment, and can be applied to semiconductor devices having various element structures such as a bipolar transistor and an IGBT. Various dimensions and impurity concentrations are set in accordance with required specifications. Further, in each of the above-described embodiments, the case where two JTE regions are arranged adjacent to each other is described as an example of the configuration of the JTE structure. JTE regions may be placed adjacent to each other. In this case, it is only necessary that the outermost JTE region is provided along the inner wall of the groove. As the number of JTE regions increases, the chip size increases, but the electric field concentration in each JET structure is further relaxed. Therefore, it is preferable to set the number of JTE regions as small as possible to achieve a desired breakdown voltage in the edge termination region.

  The present invention also has the same effect in a semiconductor device using another wide band gap semiconductor such as gallium nitride (GaN) or a semiconductor device using silicon. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a semiconductor device used as a switching device, and are particularly suitable for a vertical MOSFET using a wide band gap semiconductor.

1 n ⁺ type silicon carbide substrate 2 n ⁻ type silicon carbide layer 3, 4a, 41 p type base region 4 p type silicon carbide layer 5, 42 n ⁺ type source region 6, 43 p ⁺ type contact region 7 n type JFET region 8, 45 Gate insulating film 9, 46 Gate electrode 10 Active region 11 Field oxide film 12 Interlayer insulating film 13 Source electrode 14 Protective film 15 Drain electrode 20 Edge termination region 21 Step 21a Step bottom 21b Step side wall 21c Step bottom corner Part 22 Groove 30 JTE structure 31 First JTE region (p ⁻ type low concentration region)
32 2nd JTE region (p ^- type low concentration region)
33 Insulating film 40 Silicon carbide substrate 44 Trench 47 p-type region d Groove depth t1 First JTE region thickness t2 Second JTE region thickness w Groove width

Claims (8)

An active region through which a main current flows provided in a semiconductor substrate of a first conductivity type made of a semiconductor having a wider band gap than silicon;
A termination region surrounding the periphery of the active region;
With
The termination region is
A plurality of second conductivity type semiconductor regions provided in a concentric circle surrounding the periphery of the active region and at a lower impurity concentration so as to be disposed on the outside;
A groove provided on the front surface of the semiconductor substrate;
An insulating film embedded in the groove,
The outermost second conductivity type semiconductor region of the plurality of second conductivity type semiconductor regions is provided along an inner wall of the groove and covers the insulating film. On the front surface of the semiconductor substrate, a step is formed by making the termination region lower than the active region,
The semiconductor device according to claim 1, wherein the groove and the second conductive semiconductor region are provided on a surface formed in the termination region by the step. In the active region, a first semiconductor region of a second conductivity type is selectively provided on the front surface side of the semiconductor substrate,
The first semiconductor region extends to a surface formed in the termination region by the step, and is in contact with the innermost second conductive semiconductor region among the plurality of second conductive semiconductor regions. The semiconductor device according to claim 2. A second semiconductor region of a first conductivity type selectively provided inside the first semiconductor region;
A gate insulating film provided in contact with a region of the first semiconductor region between the second semiconductor region and the semiconductor substrate;
A gate electrode provided on the opposite side of the first semiconductor region across the gate insulating film;
A first electrode in contact with the first semiconductor region and the second semiconductor region;
A second electrode in contact with the back surface of the semiconductor substrate;
The semiconductor device according to claim 3, further comprising: A trench reaching the semiconductor substrate through the second semiconductor region and the first semiconductor region;
A trench gate structure in which the gate electrode is provided inside the trench through the gate insulating film;
A third semiconductor region of a second conductivity type covering the bottom surface of the trench;
The semiconductor device according to claim 4, further comprising:   6. The semiconductor device according to claim 1, wherein the semiconductor having a wider band gap than silicon is silicon carbide. A method for manufacturing a semiconductor device, comprising: an active region provided on a first conductivity type semiconductor substrate made of a semiconductor having a wider bandgap than silicon; and a termination region surrounding the periphery of the active region,
A first step of forming a groove in the front surface of the semiconductor substrate in the termination region;
A second step of forming a plurality of second-conductivity-type semiconductor regions provided in a concentric circle surrounding the periphery of the active region and with a lower impurity concentration so as to be disposed on the outside;
A third step of embedding an insulating film in the groove;
Including
In the second step,
A first forming step of forming the outermost second conductive type semiconductor region of the plurality of second conductive type semiconductor regions along the inner wall of the groove;
After the first forming step, the insulating surface in which a portion corresponding to the formation region of the other second conductivity type semiconductor region among the plurality of second conductivity type semiconductor regions is opened on the front surface of the semiconductor substrate. A second forming step of forming a film mask;
A third forming step of forming the other second conductive type semiconductor region by ion implantation using the insulating film mask as a mask,
In the third step, after the third forming step, a portion other than a portion embedded in the groove of the insulating film mask is removed, and the insulating film mask remaining in the groove is removed from the insulating film. A method for manufacturing a semiconductor device, comprising: After the first formation step, the method further includes a fourth step of selectively forming one or more diffusion regions constituting an element structure in a surface layer of the front surface of the semiconductor substrate in the active region,
In the fourth step,
A fourth forming step of forming, on the front surface of the semiconductor substrate, another insulating film mask having an opening corresponding to the formation region of the diffusion region;
Using the other insulating film mask as a mask, a step of forming a set of the fifth forming step of forming the diffusion region by ion implantation is repeated for the number of the diffusion regions,
In the third step, each time the fourth step is performed, the other insulating film remaining in the groove is removed by removing a portion other than the portion embedded in the groove of the other insulating film mask. 8. The method of manufacturing a semiconductor device according to claim 7, wherein a mask is used as the insulating film, and the inside of the groove is completely filled with the insulating film.

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