JP2021002652A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

To provide a planar type semiconductor device employing trench structure in which a gate insulating film electric field is reduced, energization of a parasitic pn diode is reduced, and on-resistance is reduced, and a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device comprises: a semiconductor substrate 1 of a first conductivity type; a first semiconductor layer 3 of the first conductivity type; a second semiconductor layer 4 of a second conductivity type; a first semiconductor region 14 of the first conductivity type; a second semiconductor region 8 of the first conductivity type; a third semiconductor region 12 of the first conductivity type; a trench 11; a gate insulating film 5; a gate electrode 6; a fourth semiconductor region 13 of the second conductivity type; and an inter-layer insulating film 9. The gate electrode 6 is separately provided in a region on the first semiconductor region 14.SELECTED DRAWING: Figure 3

Description

The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices.

Conventionally, silicon (Si) has been used as a constituent material of a power semiconductor device that controls a high voltage or a large current. There are multiple types of power semiconductor devices, such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors: Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: Insulated Gate Field Effect Transistors), which can be used according to the application. Has been done.

For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can increase the current, but they cannot be switched at high speed. Specifically, the bipolar transistor is limited to use at a switching frequency of about several kHz, and the IGBT is limited to use at a switching frequency of about several tens of kHz. On the other hand, the power MOSFET has a lower current density than the bipolar transistor and the IGBT, and it is difficult to increase the current, but high-speed switching operation up to about several MHz is possible.

However, there is a strong demand in the market for power semiconductor devices that have both large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs, and development is now progressing to near the material limit. .. Silicon carbide (SiC) is being studied as a semiconductor material that can replace silicon from the viewpoint of power semiconductor devices, and can manufacture (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. Is attracting attention.

The background to this is that SiC is a chemically stable material, has a wide bandgap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. This is also because the maximum electric field strength is one order of magnitude higher than that of silicon. Since SiC has a high possibility of exceeding the material limit of silicon, future growth is expected in power semiconductor applications, especially MOSFETs. In particular, it is expected that the on-resistance is small. A vertical SiC-MOSFET having a lower on-resistance while maintaining high withstand voltage characteristics can be expected.

The structure of a conventional silicon carbide semiconductor device will be described by taking a vertical MOSFET as an example. FIG. 26 is a cross-sectional view showing the structure of a conventional planar type silicon carbide semiconductor device. As shown in FIG. 26, the vertical MOSFET150 is, n on the front surface of the n ⁺ -type silicon carbide substrate 101 ^- -type silicon carbide epitaxial layer 103 is deposited, n ^- p on the surface of the -type silicon carbide epitaxial layer 103 ⁺ The mold base layer 104 is selectively provided. Further, the n ⁺ type source region 108 and the p ⁺ type contact region 107 are selectively provided on the surface layer of the p ⁺ type base layer 104.

Further, the p ⁺ -type base layer 104, the n ^- -type in part on the silicon carbide epitaxial layer 103, through the p ⁺ -type base layer 104 in the depth direction n ^- -type silicon carbide n-type to reach the epitaxial layer 103 A JFET (Juncion FET) region 114 is provided. A gate electrode 106 is provided on the surfaces of the p ⁺ type base layer 104 and the n ⁺ type source region 108 via a gate insulating film 105. Further, a source electrode 110 is provided on the surfaces of the n ^- type silicon carbide epitaxial layer 103, the p ⁺ type contact region 107, and the n ⁺ type source region 108. Further, a drain electrode (not shown) is provided on the back surface of the n ⁺ type silicon carbide substrate 101.

Further, in order to reduce the electric field strength and energy loss of the vertical MOSFET, a planar type silicon carbide semiconductor device (TED (Trench-Etched Double-diffused) MOSFET) using a trench structure is known (the following, patent documents). See 1-3).

FIG. 27 is a perspective view showing the structure of a planar type silicon carbide semiconductor device using a conventional trench structure. FIG. 28 is a cross-sectional view taken along the line AA'of FIG. 27 showing the structure of a planar type silicon carbide semiconductor device using a conventional trench structure. FIG. 29 is a cross-sectional view taken along the line BB'of FIG. 27 showing the structure of a planar type silicon carbide semiconductor device using a conventional trench structure. In FIG. 27, the structure from the gate insulating film 105 described below to the source electrode 110 described below is omitted.

As shown in FIGS. 27 to 29, the vertical MOSFET151 is, n on the front surface of the n ⁺ -type silicon carbide substrate 101 ^- -type silicon carbide epitaxial layer 103 is deposited, n ^- surface of -type silicon carbide epitaxial layer 103 The p ⁺ type base layer 104 is selectively provided on the surface. Further, the n ⁺ type source region 108, the p ⁺ type contact region 107, and the n ⁺ type current diffusion layer 112 are selectively provided on the surface layer of the p ⁺ type base layer 104.

Further, the p ⁺ -type base layer 104, the n ^- -type in part on the silicon carbide epitaxial layer 103, through the p ⁺ -type base layer 104 in the depth direction n ^- -type silicon carbide n-type to reach the epitaxial layer 103 A JFET region 114 is provided, and a p ^- type electric field relaxation layer 113 is provided on the JFET region 114. By covering the entire JFET region 114 with the p ^- type electric field relaxation layer 113, it is possible to reduce the gate insulating film electric field applied at the time of off.

Further, a trench 111 which is shallower than the n ⁺ type current diffusion layer 112 and whose bottom surface is in contact with the p ⁺ type base layer 104 is selectively provided. FIG. 28 is a cross-sectional view of a portion where the trench 111 is not provided, and FIG. 29 is a cross-sectional view of a portion where the trench 111 is provided. A gate electrode 106 is provided on the inner wall of the trench 111, the surface of the n ⁺ type current diffusion layer 112, the p ⁺ type base layer 104, and the n ⁺ type source region 108 via the gate insulating film 105, and the interlayer insulating film 109 is formed. It is provided so as to cover the gate electrode 106. Further, a source electrode 110 is provided on the surfaces of the p ⁺ type contact region 107 and the n ⁺ type source region 108. Further, a drain electrode (not shown) is provided on the back surface of the n ⁺ type silicon carbide substrate 101.

In such a structure, since the side surface of the trench 111 is a channel region, high channel mobility can be realized as compared with the channel region of the planar type silicon carbide semiconductor device (see FIG. 26). Further, by forming the trench 111, the channel width becomes large, and a higher current density than that of the planar type silicon carbide semiconductor device can be realized.

Japanese Patent No. 6290457 Japanese Patent No. 6309656 Japanese Patent No. 6336055

However, in the planar type silicon carbide semiconductor device using the conventional trench structure, the p ^- type electric field relaxation layer 113 for reducing the gate insulating film electric field becomes a resistance component, and the JFET resistance (resistance in the JFET region 114) becomes. There is a problem that it becomes high and the on-resistance becomes high.

Further, the vertical MOSFETs 150 and 151 have a parasitic pn diode composed of an n ^- type silicon carbide epitaxial layer 103 and a p ⁺ type base layer 104. When a current flows through the parasitic pn diode, holes are injected from the p ⁺ type base layer 104, and electron and hole recombination occurs in the n ^- type silicon carbide epitaxial layer 103 or the n ⁺ type silicon carbide substrate 101. The recombination energy (3 eV) corresponding to the band gap generated at this time moves the basal plane dislocations, which are a kind of crystal defects existing in the silicon carbide substrate, and expands the stacking defects sandwiched between the two basal plane dislocations. When the stacking defect expands, it is difficult for the stacking defect to pass a current, so that there is a problem that the on-resistance of the vertical MOSFETs 150 and 151 and the forward voltage of the parasitic pn diode increase. Further, since the parasitic pn diode is a bipolar device, there is a problem that the loss (Qrr) at the time of switching is large.

In order to solve the problems caused by the above-mentioned prior art, the present invention is a planar semiconductor device and a semiconductor using a trench structure in which the gate insulating film electric field is reduced, the energization of a parasitic pn diode is reduced, and the on-resistance is reduced. It is an object of the present invention to provide a method for manufacturing an apparatus.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is provided on the first conductive type semiconductor substrate. A second conductive type second semiconductor layer is provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate. A first conductive type first semiconductor region is provided that penetrates the second semiconductor layer from the surface of the second semiconductor layer and reaches the first semiconductor layer. The surface layer of the second semiconductor layer opposite to the first semiconductor layer is selectively provided with a first conductive type second semiconductor region having a higher impurity concentration than the semiconductor substrate. A first conductive type third semiconductor that is selectively separated from the second semiconductor region and is in contact with the first semiconductor region on the surface layer of the second semiconductor layer opposite to the first semiconductor layer. An area is provided. From the surface of the second semiconductor layer, a trench is provided which is sandwiched between the second semiconductor region and the third semiconductor region and does not reach the first semiconductor layer. It is provided from the first semiconductor region to the second semiconductor region, and a gate insulating film is provided on the inner wall of the trench. A gate electrode is provided on the gate insulating film. A second conductive type fourth semiconductor region in contact with the inner wall of the trench is provided between the third semiconductor region and the gate electrode. An interlayer insulating film is provided on the gate electrode. The gate electrode is separated in a region on the first semiconductor region.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the width of the separated region is wider than the thickness of the interlayer insulating film.

Further, in the semiconductor device according to the present invention, in the above-described invention, the first semiconductor region includes a lower first semiconductor region deeper than the surface of the third semiconductor region on the semiconductor substrate side and the third semiconductor region. It is composed of an upper first semiconductor region shallower than the surface on the semiconductor substrate side, and the upper first semiconductor region has the same impurity concentration as the third semiconductor region and a higher impurity concentration than the lower first semiconductor region. It is a feature.

Further, in the semiconductor device according to the present invention, in the above-described invention, the first semiconductor region is provided on the lower first semiconductor region provided on the first semiconductor layer and the lower first semiconductor region. It is composed of an upper first semiconductor region, the interface between the lower first semiconductor region and the upper first semiconductor region is deeper than the surface of the third semiconductor region on the semiconductor substrate side, and the upper first semiconductor region is The impurity concentration is the same as that of the third semiconductor region, and the impurity concentration is higher than that of the lower first semiconductor region.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the first semiconductor region has the same impurity concentration as the third semiconductor region.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor device according to the present invention has the following features. First, a first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is performed on the first conductive type semiconductor substrate. Next, a second conductive type second semiconductor layer is formed on the opposite side of the first semiconductor layer with respect to the semiconductor substrate, and the second semiconductor layer is penetrated from the surface of the second semiconductor layer. The second step of forming the first conductive type first semiconductor region reaching the first semiconductor layer is performed. Next, a third conductive type second semiconductor region having a higher impurity concentration than the semiconductor substrate is selectively formed on the surface layer of the second semiconductor layer opposite to the first semiconductor layer. Perform the process. Next, the first conductive type of the second semiconductor layer, which is selectively separated from the second semiconductor region and is in contact with the first semiconductor region, on the surface layer opposite to the first semiconductor layer. The fourth step of forming the third semiconductor region is performed. Next, a fifth step of forming the second conductive type fourth semiconductor region on the surface layer of the third semiconductor region is performed. Next, a sixth step is performed from the surface of the second semiconductor layer to form a trench sandwiched between the second semiconductor region and the third semiconductor region and not reaching the first semiconductor layer. Next, a seventh step is performed in which a gate insulating film is formed from the first semiconductor region to the second semiconductor region, and a gate insulating film is formed on the inner wall of the trench. Next, the eighth step of forming the gate electrode on the gate insulating film is performed. Next, a ninth step of forming an interlayer insulating film on the gate electrode is performed. In the fifth step, the fourth semiconductor region is formed between the third semiconductor region and the gate electrode so as to be in contact with the inner wall of the trench. The eighth step includes a step of removing the gate electrode in a region on the first semiconductor region.

Further, in the above-described invention, the semiconductor device according to the present invention includes the second semiconductor layer and the first electrode provided on the surface side of the second semiconductor region, and the region in which the gate electrode is separated is described. An interlayer insulating film is opened, a Schottky metal is arranged in the opening, and the first electrode is Schottky connected to the first semiconductor region.

Further, in the above-described invention, the semiconductor device according to the present invention includes a second trench provided from the surface of the fourth semiconductor region in the region where the gate electrode is separated and reaches the first semiconductor region. A Schottky metal is arranged on the side wall and the bottom of the second trench, and the first electrode is Schottky-connected to the first semiconductor region.

Further, in the above-described invention, the semiconductor device according to the present invention is characterized in that the trench has a rectangular shape in a plan view and the second trench has a striped shape in a plan view.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the trench is rectangular in plan view and the second trench is rectangular in plan view.

Further, in the above-described invention, the semiconductor device according to the present invention is provided with the trench and the second trench having the same cross section in the direction in which the second semiconductor layer and the first semiconductor region are aligned. It is characterized by the absence.

According to the invention described above, the gate electrode is removed in the region on the JFET region. In this way, by removing the gate electrode on the JFET region where the electric field tends to concentrate, the electric field applied to the gate insulating film can be relaxed. As the electric field is relaxed, the impurity concentration in the JFET region can be increased and the on-resistance can be reduced.

Further, an interlayer insulating film is opened on the JFET region, a Schottky metal is arranged in the opening, and an SBD is built in. As a result, a current flows through the SBD at the time of commutation, and the current flows through the parasitic pn diode is reduced. Therefore, it is possible to prevent the on-resistance of the vertical MOSFET from increasing. Further, since the SBD has a unipolar operation, the Qrr is reduced as compared with the parasitic pn diode in the bipolar operation, and the switching loss can be reduced.

According to the semiconductor device and the method for manufacturing the semiconductor device according to the present invention, there is provided a planar type semiconductor device using a trench structure in which the gate insulating film electric field is reduced, the energization of a parasitic pn diode is reduced, and the on-resistance is reduced. It has the effect of being able to do it.

It is a perspective view which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. FIG. 5 is a sectional view taken along the line AA'in FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. It is sectional drawing BB'of FIG. 1 which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is a top view which shows the structure of the gate electrode of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 1). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 2). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 3). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 4). FIG. 5 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 5). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 1). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 2 (the 2). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 3 (the 1). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 3 (the 2). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 4 (the 1). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 4 (the 2). It is another cross-sectional view which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 1 (the 1). FIG. 2 is another cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment (No. 2). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 5 (the 1). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 5 (the 2). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 6 (the 1). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 6 (the 2). It is a top view which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 6. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 7 (the 1). It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 7 (the 2). It is a top view which shows the structure of the silicon carbide semiconductor device which concerns on Embodiment 7. It is sectional drawing which shows the structure of the conventional planar type silicon carbide semiconductor device. It is a perspective view which shows the structure of the planar type silicon carbide semiconductor device which used the conventional trench structure. FIG. 27 is a cross-sectional view taken along the line AA'in FIG. 27 showing the structure of a planar type silicon carbide semiconductor device using a conventional trench structure. FIG. 27 is a cross-sectional view taken along the line BB'in FIG. 27 showing the structure of a planar type silicon carbide semiconductor device using a conventional trench structure.

Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted. Further, in the present specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after that, and "-" is added before the index to represent a negative index. The description of the same or equivalent should be included up to 5% in consideration of variations in production.

(Embodiment 1)
The semiconductor device according to the present invention is configured by using a wide bandgap semiconductor. In the first embodiment, a silicon carbide semiconductor device manufactured by using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described by taking the MOSFET 50 as an example. FIG. 1 is a perspective view showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along the line AA'of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view taken along the line BB'of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. In FIG. 1, the structure from the gate insulating film 5 described below to the source electrode 10 described below is omitted.

As shown in FIGS. 1 to 3, the silicon carbide semiconductor device according to the first embodiment is n on the main surface (front surface) of the n ⁺ type silicon carbide substrate (first conductive type semiconductor substrate) 1. ^- type silicon carbide epitaxial layer (first conductivity type first semiconductor layer of) 3 is deposited.

The n ⁺ type silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The n ^- type silicon carbide epitaxial layer 3 is a low-concentration n-type drift layer in which, for example, nitrogen is doped with an impurity concentration lower than that of the n ⁺ type silicon carbide substrate 1. Hereinafter, the n ⁺ type silicon carbide substrate 1 alone, or the n ⁺ type silicon carbide substrate 1 and the n ^- type silicon carbide epitaxial layer 3 are combined to form a silicon carbide semiconductor substrate.

Further, the silicon carbide semiconductor device according to the first embodiment has a surface opposite to the n ^- type silicon carbide epitaxial layer 3 side of the n ⁺ type silicon carbide substrate 1 serving as a drain region (back surface of the silicon carbide semiconductor substrate). Is provided with a drain electrode (not shown). In addition, a drain electrode pad (not shown) for connecting to an external device is provided.

A MOS (insulated gate made of metal-oxide film-semiconductor) structure (element structure) is formed on the front surface side of the silicon carbide semiconductor substrate. Specifically, n ^- the surface layer opposite to the mold n ⁺ -type silicon carbide substrate 1 side of the silicon carbide epitaxial layer 3 (the front surface side of the silicon carbide semiconductor substrate), p ⁺ -type base layer (Second conductive type second semiconductor layer) 4 is selectively provided. The p ⁺ type base layer 4 is doped with, for example, aluminum (Al).

The surface layer of the p ⁺ type base layer 4 is provided with an n ⁺ type source region (first conductive type second semiconductor region) 8. Further, the p ⁺ type contact region 7 may be provided. Further, the n ⁺ type source region 8 and the p ⁺ type contact region 7 are in contact with each other. The n ⁺ type source region 8 is arranged on the JFET region 14 side described below from the p ⁺ type contact region 7.

Further, on the surface of the surface layer of the n ^- type silicon carbide epitaxial layer 3 opposite to the n ⁺ type silicon carbide substrate 1 side, the portion where the p ⁺ type base layer 4 is not provided is in the depth direction ( the -type silicon carbide epitaxial layer 3 ^- through the p ⁺ -type base layer 4 from the p ⁺ -type base layer 4 of the surface to be described later source electrode direction (first electrode) 10 to n ⁺ -type silicon carbide substrate 1) n An n-type JFET (Junction FET) region (first conductive type first semiconductor region) 14 that reaches is provided. The JFET region 14 constitutes a drift region together with the n ^- type silicon carbide epitaxial layer 3. Further, the surface layer of the p ⁺ type base layer 4 is provided with an n ⁺ type current diffusion layer (first conductive type third semiconductor region) 12 which is separated from the n ⁺ type source region 8 and is in contact with the JFET region 14. There is. The n ⁺ type current diffusion layer 12 is a so-called current diffusion layer (Curent Spreading Layer: CSL) that reduces the spreading resistance of carriers.

A trench structure is selectively provided on the first main surface side (p ⁺ type base layer 4 side) of the silicon carbide semiconductor substrate. Specifically, the trench 11 is n ^- type silicon carbide epitaxial from the surface of the p ⁺ type base layer 4 opposite to the n ⁺ type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate). It is provided at a depth that does not reach layer 3. Further, it is preferable that the trench 11 is provided at a position shallower than the interface between the n ⁺ type current diffusion layer 12 and the p ⁺ type base layer 4. This is because when the trench 11 reaches a position deeper than the interface between the n ⁺ type current diffusion layer 12 and the p ⁺ type base layer 4, no channel is formed at the bottom of the trench 11. FIG. 2 is a cross-sectional view of a portion not provided with a trench structure, and FIG. 3 is a cross-sectional view of a portion provided with a trench structure.

A gate insulating film 5 is provided on the bottom and side walls of the trench 11 along the inner wall of the trench 11, and a gate electrode 6 is provided inside the gate insulating film 5 in the trench 11. A gate electrode 6 is also provided on the surface of the portion of the p ⁺ type base layer 4 sandwiched between the n ⁺ type source region 8 and the JFET region 14 via the gate insulating film 5. The gate electrode 6 may be provided on the surface of the n ⁺ type current diffusion layer 12 via the gate insulating film 5 and the p ^- type electric field relaxation layer 13 described later. The gate electrode 6 is insulated from the JFET region 14 and the p ⁺ type base layer 4 by the gate insulating film 5.

As shown in FIGS. 2 and 3, the gate electrode 6 is not provided in the region on the JFET region 14. Therefore, in the cross-sectional view, the gate electrode 6 is divided into two regions. The gate electrode 6 may be provided at least in the region from the surface where the n ⁺ type source region 8 and the p ⁺ type base layer 4 are in contact to the surface where the n ⁺ type current diffusion layer 12 and the JFET region 14 are in contact. It may be removed in all regions on the JFET region 14. In this way, by removing the gate electrode 6 on the JFET region 14 where the electric field tends to concentrate, the electric field applied to the gate insulating film 5 can be relaxed. Here, the impurity concentration in the JFET region 14 can be increased by the amount of relaxation of the electric field, and the on-resistance can be reduced.

Further, the width of the removed separation region, that is, the distance w between the gate electrodes 6 divided into the two regions is preferably wider than the height h of the interlayer insulating film 9 (w> h). This is because when the height is narrower than h, the effect of electric field relaxation is reduced.

FIG. 4 is a top view showing the structure of the gate electrode of the silicon carbide semiconductor device according to the first embodiment. The gate electrode 6 is divided into two regions in the cross-sectional view. For example, in the edge end region 30, it is preferable that the dispersed gate electrodes 6 are connected to have the same potential. In FIG. 4, the gate electrodes 6 in the same cell are connected, but the gate electrodes 6 in other cells may be connected. The edge end region 30 has a function of surrounding the active region 40 through which a current flows when the current is turned on, relaxing the electric field concentration at the end of the active region 40, and maintaining a predetermined withstand voltage (withstand voltage).

Further, a p ^- type electric field relaxation layer (second conductive type fourth semiconductor region) 13 in contact with the inner wall of the trench 11 is provided between the n ⁺ type current diffusion layer 12 and the gate electrode 6. The p ^- type electric field relaxation layer 13 may be provided between the JFET region 14 and the gate insulating film 5. The p ^- type electric field relaxation layer 13 makes it possible to reduce the electrical capacitance between the gate electrode 6 and the n ^- type silicon carbide epitaxial layer 3 without contacting the JFET region 14 and the gate electrode 6.

Although only one MOS structure is shown in FIG. 1, a plurality of MOS structures may be arranged in parallel.

The interlayer insulating film 9 is provided on the entire surface of the silicon carbide semiconductor substrate on the front surface side so as to cover the gate electrode 6. The source electrode 10 is in contact with the n ⁺ type source region 8 and the p ⁺ type base layer 4 through a contact hole opened in the interlayer insulating film 9. When the p ⁺ type contact region 7 is provided, it is in contact with the n ⁺ type source region 8 and the p ⁺ type contact region 7. The source electrode 10 is electrically insulated from the gate electrode 6 by an interlayer insulating film 9. An electrode pad (not shown) is provided on the source electrode 10.

(Manufacturing method of silicon carbide semiconductor device according to the first embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described. 5 to 9 are cross-sectional views showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment. First, for example, an n ⁺ type silicon carbide substrate 1 doped with nitrogen at an impurity concentration of about 2 × 10 ¹⁹ / cm ³ is prepared. The main surface of the n ⁺ type silicon carbide substrate 1 may be, for example, a (000-1) surface having an off angle of about 4 degrees in the <11-20> direction. Next, an n ^- type silicon carbide epitaxial layer having a thickness of about 10 μm and nitrogen-doped with an impurity concentration of 1.0 × 10 ¹⁶ / cm ³ on the (000-1) surface of the n ⁺ type silicon carbide substrate 1. Grow 3 Here, the structure is as shown in FIG.

Next, an oxide film mask for ion implantation is formed by photolithography and etching, and a p ⁺ type base layer 4 is selectively formed on the surface layer of the n ^- type silicon carbide epitaxial layer 3 by ion implantation. The region of the n ^- type silicon carbide epitaxial layer 3 sandwiched between the p ⁺ type base layers 4 is the JFET region 14. In this ion implantation, for example, the dopant may be aluminum, and the dose amount may be set so that the impurity concentration of the p ⁺ type base layer 4 is 2.0 × 10 ¹⁶ / cm ³ . Here, the structure is as shown in FIG.

Next, the n ⁺ type source region 8 is selectively formed on the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation. Next, by photolithography and ion implantation, the surface layer of the p ⁺ -type base layer 4 may be selectively formed p ⁺ -type contact region 7. Next, the n ⁺ type current diffusion layer 12 is selectively formed on the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation. Next, the p ^- type electric field relaxation layer 13 is selectively formed on the surface layers of the n ⁺ type current diffusion layer 12 and the JFET region 14 by photolithography and ion implantation. Here, the structure is as shown in FIG.

Heat treatment (annealing) is performed to activate the p ⁺ type base layer 4, the n ⁺ type source region 8, the p ⁺ type contact region 7, the n ⁺ type current diffusion layer 12 and the p ^- type electric field relaxation layer 13. The heat treatment temperature and heat treatment time at this time may be 1620 ° C. and 10 minutes, respectively.

The order in which the p ⁺ type base layer 4, the n ⁺ type source region 8, the p ⁺ type contact region 7, the n ⁺ type current diffusion layer 12 and the p ⁻ type electric field relaxation layer 13 are formed can be changed in various ways. The p ^- type electric field relaxation layer 13 can also be formed by epitaxial growth.

Next, on the surface of the p ⁺ type base layer 4, a trench forming mask having a predetermined opening is formed by photolithography, for example, with an oxide film. Next, the surface of the p ⁺ -type base layer 4 by dry etching, to a position shallower than the interface between the n ⁺ -type current diffusion layer 12 and the p ⁺ -type base layer 4, n ^- does not reach the -type silicon carbide epitaxial layer 3 trench 11 is selectively formed.

Next, the front surface side of the silicon carbide semiconductor substrate is thermally oxidized to form the gate insulating film 5 having a thickness of 100 nm. This thermal oxidation may be carried out by heat treatment at a temperature of about 1000 ° C. in a mixed atmosphere of oxygen (O ₂ ) and hydrogen (H ₂ ). As a result, each region formed on the surface of the p ⁺ type base layer 4, the surface of the p ⁻ type electric field relaxation layer 13, and the bottom and side walls of the trench 11 are covered with the gate insulating film 5. Here, the structure is as shown in FIG. FIG. 8 shows a cross-sectional view taken along the line BB'of FIG. 1 in which the trench 11 is formed. The same applies to FIG. 9 below.

Next, a polycrystalline silicon layer (polysilicon (poly-Si) layer) doped with phosphorus (P) or boron (B), for example, is formed on the gate insulating film 5 as the gate electrode 6. Next, the polycrystalline silicon layer is patterned and selectively removed to form the inside of the gate insulating film 5 in the trench 11 and the n ⁺ type source region 8 and the JFET region 14 of the p ⁺ type base layer 4. A polycrystalline silicon layer is left on the sandwiched portion. At this time, the polycrystalline silicon layer is not left on the JFET region 14. Here, the structure is as shown in FIG.

Next, for example, phosphorus glass (PSG: Phospho Silicate Glass) is formed as the interlayer insulating film 9 so as to cover the gate insulating film 5. The thickness of the interlayer insulating film 9 may be 1.0 μm. Next, the interlayer insulating film 9 and the gate insulating film 5 are patterned and selectively removed to form a contact hole, and the n ⁺ type source region 8 and the p ⁺ type contact region 7 are exposed. Next, a heat treatment (reflow) is performed to flatten the interlayer insulating film 9.

Next, the source electrode 10 is formed on the surface of the interlayer insulating film 9. At this time, the source electrode 10 is also embedded in the contact hole, and the n ⁺ type source region 8 and the p ⁺ type contact region 7 are brought into contact with the source electrode 10. The thickness of the portion of the source electrode 10 on the interlayer insulating film 9 may be, for example, 5 μm. The source electrode 10 may be formed of, for example, aluminum (Al—Si) containing 1 wt% silicon.

Next, for example, a nickel film is formed on the surface of the n ⁺ type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate) as a drain electrode (not shown). Then, for example, heat treatment is performed at a temperature of 970 ° C. to form an ohmic contact between the n ⁺ type silicon carbide substrate 1 and the drain electrode. Next, for example, by a sputtering method, an electrode pad is deposited so as to cover the source electrode 10 and the interlayer insulating film 9 on the entire front surface of the silicon carbide semiconductor substrate. The thickness of the portion of the electrode pad on the interlayer insulating film may be, for example, 5 μm. The electrode pad may be formed of, for example, aluminum (Al—Si) containing silicon at a ratio of 1 wt%. Next, the electrode pads are selectively removed.

Next, for example, titanium (Ti), nickel (Ni) and gold (Au) are formed on the surface of the drain electrode in this order as drain electrode pads. Next, a protective film may be formed on the surface. As a result, the MOSFET 50 shown in FIGS. 1 to 3 is completed.

As described above, according to the first embodiment, the gate electrode is removed in the region on the JFET region. In this way, by removing the gate electrode on the JFET region where the electric field tends to concentrate, the electric field applied to the gate insulating film can be relaxed. As the electric field is relaxed, the impurity concentration in the JFET region can be increased and the on-resistance can be reduced.

(Embodiment 2)
10 and 11 are cross-sectional views showing the structure of the silicon carbide semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view of a portion corresponding to FIG. 2 of the first embodiment, and FIG. 11 is a cross-sectional view of a portion corresponding to FIG. 3 of the first embodiment.

The silicon carbide semiconductor device according to the second embodiment is different from the silicon carbide semiconductor device according to the first embodiment in that the JFET region 14 is a lower JFET region (lower first semiconductor region) 14a and an upper JFET region (upper first). (Semiconductor region) 14b. As shown in FIGS. 10 and 11, the lower JFET region 14a is a region deeper than the surface of the n ⁺ type current diffusion layer 12 on the n ⁺ type silicon carbide substrate 1 side (closer to the n ⁺ type silicon carbide substrate 1 than the surface). The upper JFET region 14b is provided in a region shallower than the surface of the n ⁺ type current diffusion layer 12 on the n ⁺ type silicon carbide substrate 1 side (a region closer to the source electrode 10 than the surface).

Further, the lower JFET region 14a has an impurity concentration similar to that of the n ^- type silicon carbide epitaxial layer 3, and the upper JFET region 14b has a higher impurity concentration than the n ^- type silicon carbide epitaxial layer 3 and n ⁺ type current diffusion. The impurity concentration is about the same as that of layer 12. By providing the upper JFET region 14b having a high impurity concentration in this way, the JFET resistance can be lowered as compared with the first embodiment, and the on-resistance can be further reduced. Further, in the second embodiment as well as in the first embodiment, the gate electrode 6 is removed in the region on the JFET region 14. Therefore, it has the same effect as that of the first embodiment.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment 2)
The silicon carbide semiconductor device according to the second embodiment is an n ⁺ type current diffusion to the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. When the layer 12 is selectively formed, it can be manufactured by forming the upper JFET region 14b on the surface layer of the JFET region 14.

As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained. Further, in the second embodiment, an upper JFET region having an impurity concentration similar to that of the n ⁺ type current diffusion layer is provided in a region shallower than the surface of the n ⁺ type current diffusion layer on the n ⁺ type silicon carbide substrate side. .. As a result, the JFET resistance can be lowered as compared with the first embodiment, and the on-resistance can be further reduced.

(Embodiment 3)
12 and 13 are cross-sectional views showing the structure of the silicon carbide semiconductor device according to the third embodiment. FIG. 12 is a cross-sectional view of a portion of the first embodiment corresponding to FIG. 2, and FIG. 13 is a cross-sectional view of the portion of the first embodiment corresponding to FIG.

Such differs from the silicon carbide semiconductor device in a silicon carbide semiconductor device according to the second embodiment according to the third embodiment, the interface between the lower JFET region 14a and the upper JFET region 14b is of n ⁺ -type current spreading layer 12 n ⁺ It is deeper than the surface of the type silicon carbide substrate 1 side. That is, the film thickness of the upper JFET region 14b is thicker than that of the second embodiment.

Further, the impurity concentrations in the lower JFET region 14a and the upper JFET region 14b are the same as those in the second embodiment. As described above, by providing the upper JFET region 14b having a film thickness thicker than that of the second embodiment, the JFET resistance can be lowered as compared with the second embodiment, and the on-resistance can be further reduced. Further, in the third embodiment as in the first embodiment, the gate electrode 6 is removed in the region on the JFET region 14. Therefore, it has the same effect as that of the first embodiment.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment 3)
The silicon carbide semiconductor device according to the third embodiment is an n ⁺ type current diffusion to the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It can be manufactured by selectively forming the layer 12 and then forming the upper JFET region 14b on the surface layer of the JFET region 14 by photolithography and ion implantation.

As described above, according to the third embodiment, the same effect as that of the first embodiment can be obtained. Further, in the third embodiment, the film thickness of the upper JFET region is thicker than that of the second embodiment. As a result, the JFET resistance can be lowered as compared with the second embodiment, and the on-resistance can be further reduced.

(Embodiment 4)
14 and 15 are cross-sectional views showing the structure of the silicon carbide semiconductor device according to the fourth embodiment. FIG. 14 is a cross-sectional view of a portion of the first embodiment corresponding to FIG. 2, and FIG. 15 is a cross-sectional view of the portion of the first embodiment corresponding to FIG.

The silicon carbide semiconductor device according to the fourth embodiment is different from the silicon carbide semiconductor device according to the first embodiment in that the JFET region 14 has the same impurity concentration as the n ⁺ type current diffusion layer 12. The JFET region 14 is replaced with the upper JFET region 14b of the second embodiment and the third embodiment. In the following, the same impurity concentration means, for example, the impurity concentration including manufacturing variations formed at the same time, that is, substantially the same.

By providing the JFET region 14 having a thickness thicker than the upper JFET region 14b of the second embodiment and the third embodiment and having the same impurity concentration as the n ⁺ type current diffusion layer 12, the JFET resistance is provided in the second embodiment and the third embodiment. It can be lowered as compared with the third form, and the on-resistance can be further reduced. Further, in the fourth embodiment as in the first embodiment, the gate electrode 6 is removed in the region on the JFET region 14. Therefore, it has the same effect as that of the first embodiment.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment 4)
The silicon carbide semiconductor device according to the fourth embodiment is an n ⁺ type current diffusion to the surface layer of the p ⁺ type base layer 4 by photolithography and ion implantation in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. After the layer 12 is selectively formed, it can be produced by making the impurity concentration of the JFET region 14 the same as the impurity concentration of the n ⁺ type current diffusion layer 12 by photolithography and ion implantation.

As described above, according to the fourth embodiment, the same effect as that of the first embodiment can be obtained. Further, in the fourth embodiment, the JFET region has the same impurity concentration as the n ⁺ type current diffusion layer 12, and the JFET region has a thicker film thickness than the upper JFET region of the second and third embodiments. It has become. As a result, the JFET resistance can be lowered as compared with the second embodiment, and the on-resistance can be further reduced.

In the first to fourth embodiments, the n ⁺ type current diffusion layer 12 and the p ^- type electric field relaxation layer 13 can have other shapes. 16 and 17 are other cross-sectional views showing the structure of the silicon carbide semiconductor device according to the first embodiment. 16 and 17 show the structures of the n ⁺ type current diffusion layer 12 and the p ^- type electric field relaxation layer 13 in the JFET region 14 of the first embodiment, but also in the JFET region 14 of the second to fourth embodiments. It is also possible to use an n ⁺ type current diffusion layer 12 and a p ^- type electric field relaxation layer 13 having the same shape.

For example, as shown in FIG. 16, n ⁺ -type current diffusion layer 12, p ^- -type width of the field relaxation layer 13 is wide, the width of the n ⁺ -type silicon carbide substrate 1 side may be a narrow shape. Also can alleviate electric field concentration in this shape, p ^- compared with the case and the width of the type field relaxation layer 13 side in the width and the n ⁺ -type silicon carbide substrate 1 side is comparable, n ⁺ -type high impurity concentration The region of the current diffusion layer 12 can be narrowed. Therefore, the trade-off between the on-resistance and the gate insulating film electric field can be improved, and the gate insulating film electric field can be reduced with a low on-resistance.

Further, as shown in FIG. 17, the p ^- type electric field relaxation layer 13 may be removed in a region where the gate electrode 6 is not provided. Therefore, the distance w'between the p ^- type electric field relaxation layers 13 is equal to or narrower than the distance w of the gate electrodes 6 (w'≤ w). This is because the p ^- type electric field relaxation layer 13 is provided to reduce the gate insulating film electric field applied when the gate electrode 6 is off, and therefore may not be provided in the region where the gate electrode 6 is not provided.

Further, by combining FIGS. 16 and 17, the n ⁺ type current diffusion layer 12 has a shape in which the width on the p ^- type electric field relaxation layer 13 side is wide and the width on the n ⁺ type silicon carbide substrate 1 side is narrow. ^The -type electric field relaxation layer 13 may be removed in a region where the gate electrode 6 is not provided.

(Embodiment 5)
18 and 19 are cross-sectional views showing the structure of the silicon carbide semiconductor device according to the fifth embodiment. FIG. 18 is a cross-sectional view of a portion corresponding to FIG. 2 of the first embodiment, and FIG. 19 is a cross-sectional view of a portion corresponding to FIG. 3 of the first embodiment.

The silicon carbide semiconductor device according to the fifth embodiment is different from the silicon carbide semiconductor device according to the first embodiment in that the interlayer insulating film 9 is opened on the JFET region 14 and the Schottky metal 15 is arranged in the opening. The point is that it has a built-in SBD (Schottky Barrier Diode).

In the region where the gate electrode 6 is separated, the interlayer insulating film 9 is opened to the surface of the JFET region 14, and metals such as Ti (titanium) and Mo (molybdenum) that are shotkey connected to SiC are embedded in the opening. As a result, a shotkey connection between the source electrode 10 and the JFET region 14 is formed.

Since the forward voltage Vf of the SBD is lower than that of the parasitic pn diode, the SBD is turned on at a lower voltage than the parasitic pn diode. As a result, at the time of commutation, a current flows through the SBD, and the current flows through the parasitic pn diode is reduced. Therefore, it is possible to prevent the on-resistance of the vertical MOSFET from increasing. Further, since the SBD has a unipolar operation, the Qrr is reduced as compared with the parasitic pn diode in the bipolar operation, and the switching loss can be reduced.

Further, it is preferable that the width of the Schottky metal 15 is narrower than the width of the opening of the interlayer insulating film 9, and the p ^- type electric field relaxation layer 13 protrudes from the opening. Since the end of the JFET region 14 is a place where leakage is likely to occur, a p ^- type electric field relaxation layer 13 can be provided to relax the electric field at the Schottky interface and reduce the leakage current.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment 5)
The silicon carbide semiconductor device according to the fifth embodiment can be manufactured by adding the following processing to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. First, the interlayer insulating film 9 is opened to the surface of the JFET region 14 in the region where the gate electrode 6 is separated. When the p ^- type electric field relaxation layer 13 is formed, it is not formed on the opening of the JFET region 14. Next, a metal film is formed of, for example, Ti or Mo along the surface of the JFET region 14 of the opening. Next, a Schottky connection between the metal film and the semiconductor region is formed on the surface of the JFET region 14 by heat treatment (annealing) in a nitrogen (N ₂ ) atmosphere having a temperature of, for example, about 500 ° C. or lower. Other than this, it can be manufactured in the same manner as the manufacturing method of the silicon carbide semiconductor device according to the first embodiment.

As described above, according to the fifth embodiment, the same effect as that of the first embodiment can be obtained. Further, in the fifth embodiment, the interlayer insulating film is opened on the JFET region, the Schottky metal is arranged in the opening, and the SBD is built in. As a result, a current flows through the SBD at the time of commutation, and the current flows through the parasitic pn diode is reduced. Therefore, it is possible to prevent the on-resistance of the vertical MOSFET from increasing. Further, since the SBD has a unipolar operation, the Qrr is reduced as compared with the parasitic pn diode in the bipolar operation, and the switching loss can be reduced.

(Embodiment 6)
20 and 21 are cross-sectional views showing the structure of the silicon carbide semiconductor device according to the sixth embodiment. FIG. 20 is a cross-sectional view of a portion corresponding to FIG. 2 of the first embodiment, and FIG. 21 is a cross-sectional view of a portion corresponding to FIG. 3 of the first embodiment.

The silicon carbide semiconductor device according to the sixth embodiment is different from the silicon carbide semiconductor device according to the fifth embodiment in that the interlayer insulating film 9 is opened on the JFET region 14 and a Schottky trench (the first) is formed on the JFET region 14. 2 trenches) 16 are provided, and Schottky metal 15 is arranged on the bottom and side walls of the Schottky trench 16 to incorporate an SBD.

A Schottky connection between the source electrode 10 and the JFET region 14 is formed by embedding a metal such as Ti (titanium) or Mo (molybdenum) that connects to SiC in the bottom and side walls of the Schottky trench 16. To. In the sixth embodiment, since the Schottky connection is formed at the bottom and the side wall of the Schottky trench 16, the area of the Schottky connection can be increased as compared with the fifth embodiment.

Here, the Schottky trench 16 preferably has a tapered shape in which the width of the opening is wider than the width of the bottom. This is because in the reverse taper shape in which the angle θ formed by the side wall and the bottom of the Schottky trench 16 is 90 ° or more, the electric field is concentrated on the corner between the side wall and the bottom of the Schottky trench 16.

Further, the larger the angle θ, the larger the area of the side wall, and the area of the Schottky connection can be increased. On the other hand, the larger the angle θ, the more difficult it is to narrow the width of the Schottky trench 16. Therefore, the angle θ formed by the side wall and the bottom of the Schottky trench 16 is preferably 82 ° or more and less than 90 °, and more preferably 85 ° or more and 88 ° or less.

Further, the Schottky trench 16 can be formed at the same time by self-alignment when forming the trench 11. Therefore, the Schottky trench 16 has the same depth as the trench 11. Further, both the trench 11 and the Schottky trench 16 are preferably deep, but when the trench 11 and the Schottky trench 16 are deepened, the electric field is concentrated on the bottoms of the trench 11 and the Schottky trench 16. Trenches 11, p ⁺ -type base layer 4 is provided on the bottom, because the bottom is protected by a p ⁺ -type base layer 4, from the Schottky trench 16, the electric field is unlikely to concentrate on the bottom. Therefore, the trench 11 may be deeper than the Schottky trench 16.

FIG. 22 is a plan view showing the structure of the silicon carbide semiconductor device according to the sixth embodiment. The AA'cross section of FIG. 22 is the cross section of FIG. 20, and the BB' cross section of FIG. 22 is the cross section of FIG. 22 is a plan view taken along the line CC'of FIGS. 20 and 21. As shown in FIG. 22, the trench 11 has a rectangular shape in a plan view (the direction in which the vertical MOSFET 50 is viewed from the source electrode 10 side toward the n ⁺ type silicon carbide substrate 1 side), and the Schottky trench 16 has a rectangular shape. It has a striped shape in a plan view.

In this case, the width w1 of the trench 11 is preferably wider than the width w2 of the Schottky trench 16. The wider the width, the deeper the trench tends to be. Therefore, the Schottky trench 16 is made thinner than the trench 11 and shallower than the trench 11.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment 6)
The silicon carbide semiconductor device according to the sixth embodiment can be manufactured by adding the following processing to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. First, the interlayer insulating film 9 is opened to the surface of the p ^- type electric field relaxation layer 13 in the region where the gate electrode 6 is separated. Next, on the surface of the p ⁺ type base layer 4 and the JFET region 14, a trench forming mask having a predetermined opening is formed by photolithography, for example, with an oxide film. Next, the surface of the p ⁺ -type base layer 4 by dry etching, to a position shallower than the interface between the n ⁺ -type current diffusion layer 12 and the p ⁺ -type base layer 4, n ^- does not reach the -type silicon carbide epitaxial layer 3 trench 11 and a Schottky trench 16 reaching the JFET region 14 are selectively formed from the surface of the p ^- type electric field relaxation layer 13. Next, a metal film is formed of, for example, Ti or Mo along the side wall and bottom of the Schottky trench 16. Next, a Schottky connection between the metal film and the semiconductor region is formed on the side wall and bottom of the Schottky trench 16 by heat treatment (annealing) in a nitrogen (N ₂ ) atmosphere having a temperature of, for example, about 500 ° C. or lower. Other than this, it can be manufactured in the same manner as the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. As described above, the Schottky trench 16 can be formed at the same time as the trench 11, and no additional process is required.

As described above, according to the sixth embodiment, the same effect as that of the fifth embodiment can be obtained. Further, in the sixth embodiment, a Schottky trench is provided, a Schottky metal is arranged on the bottom and side walls of the Schottky trench, and an SBD is built in. Therefore, the sixth embodiment can increase the area of the Schottkey connection as compared with the fifth embodiment.

(Embodiment 7)
23 and 24 are cross-sectional views showing the structure of the silicon carbide semiconductor device according to the seventh embodiment. FIG. 23 is a cross-sectional view of a portion corresponding to FIG. 2 of the first embodiment, and FIG. 24 is a cross-sectional view of a portion corresponding to FIG. 3 of the first embodiment. FIG. 25 is a plan view showing the structure of the silicon carbide semiconductor device according to the seventh embodiment. The AA'cross section of FIG. 25 is the cross section of FIG. 23, and the BB' cross section of FIG. 25 is the cross section of FIG. 24. Further, FIG. 25 is a plan view taken along the line CC'of FIGS. 23 and 24.

The silicon carbide semiconductor device according to the seventh embodiment is different from the silicon carbide semiconductor device according to the sixth embodiment in that the Schottky trench 16 has a rectangular shape. Therefore, in the seventh embodiment, by making the Schottky trench 16 finer, the side wall portion of the Schottky trench 16 can be increased, and the area of the Schottky connection can be increased as compared with the sixth embodiment. Making the Schottky trench 16 finer means shortening the length l of the rectangle (see FIG. 25). By shortening the length, it is possible to increase the portion of the side wall in the direction in which the rectangles are lined up (the direction orthogonal to AA'in FIG. 25).

The shape of the Schottky trench 16 can be rounded at the corners of a rectangle or made into a circular shape. In this case, it is possible to reduce the concentration of the electric field on the corners of the rectangle. Also, a circular shape is easier to create than a rectangular shape.

Further, as shown in FIG. 25, it is preferable that the trench 11 and the Schottky trench 16 are staggered. That is, the trench 11 and the Schottky trench 16 are cross sections in the direction in which the p ⁺ type base layer 4 and the JFET region 14 are aligned (direction parallel to AA'in FIG. 25), and are not provided in the same cross section. .. As a result, the trench 11 and the Schottky trench 16 can be separated from each other, local heat generation can be suppressed, and further miniaturization becomes easy.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment 7)
The silicon carbide semiconductor device according to the seventh embodiment can be manufactured by forming the Schottky trench 16 into a rectangular shape in the method for manufacturing the silicon carbide semiconductor device according to the sixth embodiment.

As described above, according to the seventh embodiment, the same effect as that of the sixth embodiment can be obtained. Further, in the seventh embodiment, the area of the Schottky connection can be increased as compared with the sixth embodiment by making the Schottky trench finer. Further, by staggering the trench and the Schottky trench, the trench and the Schottky trench can be separated from each other, local heat generation can be suppressed, and further miniaturization becomes easy.

As described above, in the fifth to seventh embodiments, the case where the SBD is added to the first embodiment shown in FIGS. 1 to 3 has been described as an example, but the SBD can also be added to the second to fourth embodiments. Is. That is, the Schottky metal 15 can be arranged on the surface of the JFET region 14 also in the second embodiment in which the JFET region 14 includes the lower JFET region 14a and the upper JFET region 14b. Further, in the third embodiment, in which the interface between the lower JFET region 14a and the upper JFET region 14b is deeper than the surface of the n ⁺ type current diffusion layer 12 on the n ⁺ type silicon carbide substrate 1 side, the shot is made on the surface of the JFET region 14. It is possible to arrange the key metal 15. Further, in the fourth embodiment in which the JFET region 14 has the same impurity concentration as the n ⁺ type current diffusion layer 12, the Schottky metal 15 can be arranged on the surface of the JFET region 14.

Further, in the fifth to seventh embodiments, the shape of the n ⁺ type current diffusion layer 12 can be changed to the shape shown in FIG. That, n ⁺ -type current diffusion layer 12, p ^- -type width of the field relaxation layer 13 is wide, the width of the n ⁺ -type silicon carbide substrate 1 side may be narrower shape.

Although the MOSFET has been described as an example of the embodiment, it can also be applied to an IGBT in which a p-type region is provided on the back surface side of the silicon carbide semiconductor substrate. In this case, the resistance of the surface of the silicon carbide semiconductor substrate is lowered by the IE effect (Injection Enhancement Effect), and a high withstand voltage IGBT becomes possible.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set in various ways according to the required specifications and the like. Further, in each of the above-described embodiments, the case where silicon carbide is used as the wide bandgap semiconductor is described as an example, but it can also be applied to a widebandgap semiconductor such as gallium nitride (GaN) other than silicon carbide. Is. It is also applicable to semiconductors other than wide bandgap semiconductors such as silicon (Si) and germanium (Ge). Further, in each embodiment, the first conductive type is n-type and the second conductive type is p-type, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. It holds.

As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are power semiconductors used in power conversion devices such as inverters, power supply devices such as various industrial machines, and igniters of automobiles. Useful for equipment.

1,101 n ⁺ type silicon carbide substrate 3, 103 n ^- type silicon carbide epitaxial layer 4, 104 p ⁺ type base layer 5, 105 gate insulating film 6, 106 gate electrode 7, 107 p ⁺ type contact region 8, 108 n ⁺ Type source region 9, 109 Interlayer insulating film 10, 110 Source electrode 11, 111 Trench 12, 112 n ⁺ type current diffusion layer 13, 113 p ^- type electric field relaxation layer 14, 114 JFET region 14a Lower JFET region 14b Upper JFET region 15 Shotkey metal 16 Shotkey trench 30 Edge termination area 40 Active area 50, 150, 151 Vertical MOSFET

Claims (11)

The first conductive type semiconductor substrate and
A first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate provided on the semiconductor substrate,
A second conductive type second semiconductor layer of the first semiconductor layer provided on the opposite side of the semiconductor substrate,
A first conductive type first semiconductor region that penetrates the second semiconductor layer from the surface of the second semiconductor layer and reaches the first semiconductor layer.
A first conductive type second semiconductor region having a higher impurity concentration than the semiconductor substrate, which is selectively provided on the surface layer of the second semiconductor layer opposite to the first semiconductor layer,
A first conductive type of the second semiconductor layer, which is selectively provided on the surface layer opposite to the first semiconductor layer and is in contact with the first semiconductor region at a distance from the second semiconductor region. Third semiconductor area and
A trench provided from the surface of the second semiconductor layer, sandwiched between the second semiconductor region and the third semiconductor region, and does not reach the first semiconductor layer.
A gate insulating film provided from the first semiconductor region to the second semiconductor region and provided on the inner wall of the trench.
The gate electrode provided on the gate insulating film and
A second conductive type fourth semiconductor region provided between the third semiconductor region and the gate electrode and in contact with the inner wall of the trench,
An interlayer insulating film provided on the gate electrode and
With
A semiconductor device characterized in that the gate electrodes are separated in a region on the first semiconductor region. The semiconductor device according to claim 1, wherein the width of the separated region is wider than the thickness of the interlayer insulating film. The first semiconductor region includes a lower first semiconductor region deeper than the surface of the third semiconductor region on the semiconductor substrate side and an upper first semiconductor region shallower than the surface of the third semiconductor region on the semiconductor substrate side. ,
The semiconductor device according to claim 1 or 2, wherein the upper first semiconductor region has the same impurity concentration as the third semiconductor region, and has a higher impurity concentration than the lower first semiconductor region. The first semiconductor region includes a lower first semiconductor region provided on the first semiconductor layer and an upper first semiconductor region provided on the lower first semiconductor region.
The interface between the lower first semiconductor region and the upper first semiconductor region is deeper than the surface of the third semiconductor region on the semiconductor substrate side.
The semiconductor device according to claim 1 or 2, wherein the upper first semiconductor region has the same impurity concentration as the third semiconductor region, and has a higher impurity concentration than the lower first semiconductor region. The semiconductor device according to claim 1 or 2, wherein the first semiconductor region has the same impurity concentration as the third semiconductor region. A first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate on the first conductive type semiconductor substrate.
A second conductive type second semiconductor layer is formed on the side of the first semiconductor layer opposite to the semiconductor substrate, and the first semiconductor layer is penetrated from the surface of the second semiconductor layer. The second step of forming the first conductive type first semiconductor region reaching the semiconductor layer, and
A third step of selectively forming a first conductive type second semiconductor region having a higher impurity concentration than the semiconductor substrate on the surface layer of the second semiconductor layer opposite to the first semiconductor layer.
A first conductive type third semiconductor that is selectively separated from the second semiconductor region and is in contact with the first semiconductor region on the surface layer of the second semiconductor layer opposite to the first semiconductor layer. The fourth step of forming the region and
The fifth step of forming the second conductive type fourth semiconductor region on the surface layer of the third semiconductor region, and
A sixth step of forming a trench that is sandwiched between the second semiconductor region and the third semiconductor region and does not reach the first semiconductor layer from the surface of the second semiconductor layer.
A seventh step of forming a gate insulating film from the first semiconductor region to the second semiconductor region and forming a gate insulating film on the inner wall of the trench.
The eighth step of forming the gate electrode on the gate insulating film and
The ninth step of forming an interlayer insulating film on the gate electrode and
Including
In the fifth step, the fourth semiconductor region is formed between the third semiconductor region and the gate electrode so as to be in contact with the inner wall of the trench.
The eighth step is a method for manufacturing a semiconductor device, which comprises a step of removing the gate electrode in a region on the first semiconductor region. The second semiconductor layer and the first electrode provided on the surface side of the second semiconductor region are provided.
The interlayer insulating film is opened in the region where the gate electrode is separated, a Schottky metal is arranged in the opening, and the first electrode is Schottky connected to the first semiconductor region. The semiconductor device according to any one of claims 1 to 5. A second trench provided from the surface of the fourth semiconductor region and reaching the first semiconductor region is provided in the region where the gate electrode is separated.
The semiconductor device according to claim 7, wherein Schottky metal is arranged on the side wall and the bottom of the second trench, and the first electrode is Schottky connected to the first semiconductor region. The trench is rectangular in plan view and has a rectangular shape.
The semiconductor device according to claim 8, wherein the second trench has a striped shape in a plan view. The trench is rectangular in plan view and has a rectangular shape.
The semiconductor device according to claim 8, wherein the second trench has a rectangular shape in a plan view. The semiconductor device according to claim 10, wherein the trench and the second trench are cross sections in a direction in which the second semiconductor layer and the first semiconductor region are aligned and are not provided in the same cross section.

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