WO2019077878A1 - Silicon carbide semiconductor device, and manufacturing method of silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device, and manufacturing method of silicon carbide semiconductor device Download PDF

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WO2019077878A1
WO2019077878A1 PCT/JP2018/031239 JP2018031239W WO2019077878A1 WO 2019077878 A1 WO2019077878 A1 WO 2019077878A1 JP 2018031239 W JP2018031239 W JP 2018031239W WO 2019077878 A1 WO2019077878 A1 WO 2019077878A1
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silicon carbide
type
semiconductor
semiconductor device
carbide semiconductor
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PCT/JP2018/031239
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French (fr)
Japanese (ja)
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保幸 星
悠一 橋爪
熊田　恵志郎
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富士電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the present invention relates to a silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device.
  • silicon is used as a constituent material of a power semiconductor device that controls high voltage and large current.
  • power semiconductor devices such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used according to applications. It is done.
  • bipolar transistors and IGBTs have higher current densities and can be made larger than MOSFETs, but can not be switched at high speed.
  • the use of the bipolar transistor is limited at a switching frequency of about several kHz
  • the use of an IGBT is limited at a switching frequency of about several tens of kHz.
  • power MOSFETs have lower current density and are difficult to increase in current as compared to bipolar transistors and IGBTs, but high-speed switching operation up to about several MHz is possible.
  • SiC silicon carbide
  • Silicon carbide is a chemically very stable semiconductor material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures.
  • silicon carbide is expected as a semiconductor material that can sufficiently reduce the on-resistance because the maximum electric field strength is also larger by one digit or more than that of silicon.
  • Such characteristics of silicon carbide also apply to other wide band gap semiconductors having a wider band gap than silicon, such as gallium nitride (GaN). Therefore, by using the wide band gap semiconductor, the breakdown voltage of the semiconductor device can be increased.
  • FIG. 14 is a top view showing the structure of a conventional silicon carbide semiconductor device.
  • FIG. 15 is a cross-sectional view of a portion A-A 'in FIG. 14 showing a structure of a conventional silicon carbide semiconductor device.
  • FIG. 15 is a top view from which a gate insulating film 106, a gate electrode 108, an interlayer insulating film 109, and a source electrode 110 which will be described later are removed.
  • a silicon carbide semiconductor device a silicon carbide MOSFET (hereinafter, SiC-MOSFET) is taken as an example.
  • an n ⁇ -type silicon carbide epitaxial layer 102 is deposited on the front surface of the n + -type silicon carbide substrate 101, and a p-type on the surface of the n ⁇ -type silicon carbide epitaxial layer 102
  • the base layer 103 is selectively provided.
  • an n + -type source region 104 and a p ++ -type contact region 105 are selectively provided on the surface of the p-type base layer 103.
  • a stripe-shaped gate electrode 108 is provided on the surface of the p-type base layer 103 and the n + -type source region 104 with the gate insulating film 106 interposed therebetween.
  • source electrodes 110 are provided on the surfaces of n ⁇ type silicon carbide epitaxial layer 102, p ++ type contact region 105 and n + type source region 104.
  • the interlayer insulating film 109 insulates the source electrode 110 from the gate electrode 108.
  • a drain electrode 114 is provided on the back surface of the n + -type silicon carbide substrate 101.
  • the p-type base layer 103 is provided in a stripe shape, and p-type base layers 103 and n + -type source regions 104 are alternately provided in a direction parallel to the stripe shape.
  • a p-type impurity region is formed on the source region, an n-type impurity region is formed on the p-type impurity region, and the side surfaces of the p-type impurity region and the n-type impurity region are with respect to the main surface of the substrate.
  • a semiconductor device which may have an angle other than 90 degrees, and each side surface may have a curvature (see, for example, Patent Document 1).
  • a semiconductor device is known in which a C surface or a corner is formed on an R surface in a device region of a semiconductor substrate, the corner being cut off using a straight line intersecting the corner of the rectangle at an angle of 45 ° (See, for example, Patent Document 2).
  • Patent No. 5223041 Unexamined-Japanese-Patent No. 9-320979
  • FIG. 16 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon semiconductor device.
  • the n ⁇ -type silicon epitaxial layer 202 is formed on the front surface of the n + -type silicon substrate 201.
  • gate insulating film 106, gate electrode 108 and interlayer insulating film 109 are formed on the surface of n - type silicon epitaxial layer 202, and then p type base layer 103 and n + type source region 104 are formed by ion implantation and ion diffusion. It was
  • p-type impurities are ion-implanted by ion implantation using the interlayer insulating film 109 as a mask.
  • the p-type impurity is thermally diffused to the gate electrode 108 side to form the p-type base layer 103.
  • n-type impurities are ion-implanted by ion implantation to form an n + -type source region 104.
  • FIG. 17 and FIG. 18 are cross-sectional views showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device.
  • a mask 120 having a desired opening is formed of, for example, an oxide film by photolithography.
  • p-type impurities are ion-implanted by the ion implantation method using the oxide film 120 as a mask.
  • p-type base layer 103 is formed on the surface layer of n ⁇ -type silicon carbide epitaxial layer 102.
  • a mask 121 having a desired opening is formed of, for example, an oxide film by photolithography. Then, n-type impurities are ion-implanted by the ion implantation method using the oxide film 121 as a mask. Thereby, n + -type source region 104 is formed in the surface layer of p-type base layer 103.
  • FIG. 19 is a top view showing the structure of the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device.
  • the corner S of the n + -type source region 104 is formed to have a higher impurity concentration than other portions.
  • the corner S has a high impurity concentration, so the resistance is low. Therefore, due to the overvoltage of the gate electrode 108 and the strong electric field applied to the gate electrode 108 when applied to the drain electrode 114, the electric field is concentrated at the corner S and faces the corner S of the n + -type source region 104.
  • a high electric field is applied to the gate insulating film 106, and the gate insulating film 106 may be broken.
  • the gate insulating film 106 facing the corner S of the n + -type source region 104 is broken.
  • the present invention improves the breakdown resistance of the gate insulating film with respect to the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode.
  • An object of the present invention is to provide a method of manufacturing a silicon semiconductor device and a silicon carbide semiconductor device.
  • the silicon carbide semiconductor device has the following features.
  • a first conductivity type first semiconductor layer having an impurity concentration lower than that of the silicon carbide semiconductor substrate is provided on the front surface of the first conductivity type silicon carbide semiconductor substrate.
  • a second semiconductor layer of the second conductivity type is selectively provided on the surface layer of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side.
  • a first semiconductor region of a first conductivity type is selectively provided in the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side.
  • a stripe-shaped gate electrode is provided on at least a portion of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer via a gate insulating film.
  • a first electrode is provided on the surface of the first semiconductor region and the second semiconductor layer.
  • a second electrode is provided on the back surface of the silicon carbide semiconductor substrate.
  • the impurity concentration of the surface corner of the first semiconductor region is the same as or lower than the impurity concentration of the portion other than the corner of the surface of the first semiconductor region.
  • the surface corner portion of the first semiconductor region is chamfered.
  • the second semiconductor of the second conductivity type is selectively provided on the surface layer opposite to the silicon carbide semiconductor substrate side of the second semiconductor layer.
  • the semiconductor device may further include a region, and a surface corner of the second semiconductor region is chamfered.
  • the first semiconductor region has a rectangular surface, and the corners of the rectangle are rounded or the corners of the rectangle are cut off. It is characterized by
  • the first semiconductor region has a length of 5% to 30% of the width of the first semiconductor region, and the rectangular corner is rounded. Or the corners of the rectangle are cut off.
  • the method for manufacturing a silicon carbide semiconductor device has the following features. First, a first step of forming a first semiconductor layer of the first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is performed on the front surface of the silicon carbide semiconductor substrate of the first conductivity type. Next, a second step of selectively forming a second semiconductor layer of the second conductivity type on the surface layer opposite to the silicon carbide semiconductor substrate side of the first semiconductor layer is performed. Next, a third step of selectively forming a first semiconductor region of the first conductivity type is performed in the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side.
  • a fourth step of forming a stripe-shaped gate electrode via a gate insulating film on at least a part of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer is described. Do. Next, a fifth step of forming a first electrode on the surfaces of the first semiconductor region and the second semiconductor layer is performed. Next, a sixth step of forming a second electrode on the back surface of the silicon carbide semiconductor substrate is performed. The third step is characterized in that the first semiconductor region is formed such that the impurity concentration of the surface corner is equal to or lower than the impurity concentration of the portion other than the surface corner.
  • the first semiconductor region in which a corner is chamfered is formed.
  • the second conductive layer is selectively formed on the surface layer opposite to the silicon carbide semiconductor substrate side of the second semiconductor layer.
  • the method further includes the step of forming a semiconductor region, wherein a surface corner of the second semiconductor region is chamfered.
  • the n + -type source region (the first semiconductor region of the first conductivity type) has a rectangular shape, and all four corners are chamfered.
  • the concentration of the electric field at the corners is reduced by the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode. Therefore, in the silicon carbide semiconductor device of the present configuration, the breakdown resistance of the gate insulating film is improved.
  • the breakdown resistance of the gate insulating film against the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode is improved.
  • FIG. 1A is a top view showing a structure of a silicon carbide semiconductor device according to a first embodiment.
  • FIG. 1B is a top view showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 1C is a top view showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view of the A-A ′ portion of FIG. 1B showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 3 is an enlarged view of a portion B of FIG. 1A showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 4 is an enlarged view of a portion B of FIG. 1A showing another structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 1A is a top view showing a structure of a silicon carbide semiconductor device according to a first embodiment.
  • FIG. 1B is a top view showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 5 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (part 1).
  • FIG. 6 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (part 2).
  • FIG. 7 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 3).
  • FIG. 8 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (part 4).
  • FIG. 9 is a top view showing a state in the middle of manufacture of the n + -type source region of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 10 is a top view showing the structure of the silicon carbide semiconductor device according to the second embodiment.
  • 11 is an enlarged view of a portion B of FIG. 10 showing the structure of the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 12 is an enlarged view of a portion B of FIG. 10 showing another structure of the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 13 is a cross-sectional view showing a structure of a trench type silicon carbide MOSFET according to the first and second embodiments.
  • FIG. 14 is a top view showing the structure of a conventional silicon carbide semiconductor device.
  • FIG. 15 is a cross-sectional view of a portion A-A 'in FIG. 14 showing a structure of a conventional silicon carbide semiconductor device.
  • FIG. 16 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon semiconductor device.
  • FIG. 17 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device (part 1).
  • FIG. 18 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device (part 2).
  • FIG. 19 is a top view showing the structure of the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device.
  • n and p in the layer or region having n or p, it is meant that electrons or holes are majority carriers, respectively.
  • + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively.
  • the notation of n and p including + and-is the same it indicates that the concentration is close, and the concentration is not necessarily the same.
  • Embodiment 1 The semiconductor device according to the present invention is configured using a wide band gap semiconductor.
  • a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a MOSFET as an example.
  • 1A, 1B, and 1C are top views showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view of the AA ′ portion of FIG. 1B showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • the silicon carbide semiconductor device includes a semiconductor substrate made of silicon carbide (hereinafter, referred to as a silicon carbide semiconductor substrate (semiconductor substrate (semiconductor chip)) 40.
  • a MOS insulated gate made of metal-oxide film-semiconductor
  • an n ⁇ -type silicon carbide epitaxial layer (first conductive) made of silicon carbide is formed on the front surface of an n + -type silicon carbide substrate (silicon carbide semiconductor substrate of the first conductivity type) made of silicon carbide (first conductive)
  • the first semiconductor layer 2 of the mold is laminated.
  • a p-type base layer (a second semiconductor layer of the second conductivity type) is provided on the surface layer of the n - type silicon carbide epitaxial layer 2 on the opposite side (base front side) to the n-type silicon carbide substrate 1 side. 3) is provided selectively.
  • n + -type source region (first semiconductor region of the first conductivity type) 4 and a p ++ -type contact region 5 are provided on the surface of the p-type base layer 3. Also, the n + -type source region 4 and the p ++ -type contact region 5 are in contact with each other. The n + -type source region 4 is disposed at the outer periphery of the p ++ -type contact region 5.
  • gate electrode 8 is provided on the surface of a portion of p-type base layer 3 sandwiched by n + -type source region 4 and n ⁇ -type silicon carbide epitaxial layer 2 through gate insulating film 6. . Gate electrode 8 may be provided on the surface of n -- type silicon carbide epitaxial layer 2 via gate insulating film 6.
  • Interlayer insulating film 9 is provided on the entire top surface of silicon carbide semiconductor substrate 40 so as to cover gate electrode 8.
  • Source electrode (first electrode) 10 is in contact with n + -type source region 4 and p ++ -type contact region 5 via a contact hole opened in interlayer insulating film 9.
  • Source electrode 10 is electrically insulated from gate electrode 8 by interlayer insulating film 9.
  • An electrode pad (not shown) is provided on the source electrode 10.
  • the p-type base layer 3 is provided in a stripe shape. Tapered p-type base layer 3 by miniaturization, since the n + -type source region 4 and the like can not be patterned, striped n + -type source region 4 in the p-type base layer 3 is formed, n + -type A plurality of p ++ -type contact regions 5 are provided in source region 4. Thus, p ++ -type contact regions 5 and n + -type source regions 4 are alternately provided in the direction parallel to the stripe shape. In the first embodiment, the n + -type source region 4 has a rectangular shape, and all four corners are chamfered.
  • the corner portion is a corner portion of the n + -type source region 4 surrounded by the p-type base layer 3, and the chamfering is to cut the corner to form a surface.
  • the p ++ -type contact region 5 is also rectangular in shape, and all four corners are chamfered.
  • the corners of n + -type source region 4 and p ++ -type contact region 5 are chamfered, so the corners of n + -type source region 4 and p ++ -type contact region 5 There is no part where the impurity concentration is high. Therefore, the concentration of the electric field at the corners is alleviated by the overvoltage of the gate electrode 8 and the strong electric field applied to the gate electrode 8 when applied to the drain electrode 14, and the breakdown resistance of the gate insulating film 6 is improved. Ru.
  • FIG. 3 is an enlarged view of a portion B of FIG. 1A showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • the corners can be chamfered by rounding the corners of the rectangle. If the amount of rounding the corners of the rectangle is too small, concentration of the electric field at the corners can not be alleviated, and if too large, the area of the n + -type source region 4 decreases and the ineffective region increases. Therefore, it is preferable that the amount of rounding the corner of the rectangle is 5% or more and 30% or less of the width W of the n + -type source region 4. The amount by which the corner of the rectangle is rounded is the distance R1 between the corner of the rectangle before chamfering and the surface after chamfering. Similarly, the amount of rounding the corners of a rectangle of p ++ type contact region 5 is also preferably 30% or less than 5% of the width of the p ++ type contact region 5.
  • FIG. 4 is an enlarged view of a portion B of FIG. 1A showing another structure of the silicon carbide semiconductor device according to the first embodiment.
  • the corners can be chamfered by cutting the corners.
  • the amount by which the corner of the rectangle is cut out is preferably 5% or more and 30% or less of the width W of the n + -type source region 4 for the same reason as the amount by which the corner of the rectangle in FIG. 3 is rounded.
  • the amount by which the corner of the rectangle is cut is the distance R2 between the corner before the cut and the surface after being cut.
  • the amount by which the rectangular corner of the p ++ -type contact region 5 is cut out is preferably 5% or more and 30% or less of the width of the p ++ -type contact region 5.
  • the corners of both the n + -type source region 4 and the p ++ -type contact region 5 are chamfered, but the chamfering of the corners is the n + -type source region Only 4 may be used. This configuration can reduce the concentration of the electric field at the corners.
  • one n + -type source region 4 is provided in one stripe-like p-type base layer 3 in FIG. 1A, a plurality of n + -type source regions 4 may be provided.
  • the p ++ -type contact region 5 may be provided in the n + -type source region 4 as shown in FIG. 1B or may be alternately arranged with the n + -type source region 4 as shown in FIG. 1C.
  • FIG. 5 to 8 are cross sectional views schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • an n + -type silicon carbide substrate 1 doped with nitrogen (N 2 ) at an impurity concentration of, for example, about 2 ⁇ 10 19 / cm 3 is prepared.
  • the n + -type silicon carbide substrate 1 may have, for example, a (000-1) plane whose main surface has an off angle of about 4 degrees in the ⁇ 11-20> direction.
  • an n ⁇ -type silicon carbide epitaxial layer with a thickness of about 10 ⁇ m doped with nitrogen at an impurity concentration of 1.0 ⁇ 10 16 / cm 3 on the (000-1) plane of n + -type silicon carbide substrate 1 Grow two.
  • the structure shown in FIG. 5 is obtained.
  • the dopant may be aluminum (Al), and the dose may be set so that the impurity concentration of the p-type base layer 3 is 1 ⁇ 10 16 to 1 ⁇ 10 18 / cm 3 .
  • the structure shown in FIG. 6 is obtained.
  • the n + -type source region 4 is selectively formed in the surface layer of the p-type base layer 3 by photolithography and ion implantation.
  • the p ++ -type contact region 5 is selectively formed in the surface layer of the p-type base layer 3 by photolithography and ion implantation.
  • the dose may be set such that the dopant is aluminum and the impurity concentration of the p ++ -type contact region 5 is 1 ⁇ 10 17 to 1 ⁇ 10 19 / cm 3 .
  • the structure shown in FIG. 7 is obtained.
  • FIG. 9 is a top view showing a state in the middle of manufacture of the n + -type source region of the silicon carbide semiconductor device according to the first embodiment.
  • the mask 12 having openings at the corners of the n + -type source region 4 is used. be able to.
  • the p ++ -type contact region 5 is formed in a rectangular shape in which all four corners are chamfered.
  • all the four corners can also be formed by reducing the concentration of the impurity implanted by ion implantation toward the corner of the region where the n + -type source region 4 and the p ++ -type contact region 5 are formed. Can be formed to be chamfered.
  • n + -type source region 4 and the p ++ -type contact region 5 can be changed variously.
  • heat treatment is performed to activate the p-type base layer 3, the n + -type source region 4 and the p ++ -type contact region 5.
  • the heat treatment temperature and the heat treatment time at this time may be 1620 ° C. and 2 minutes, respectively.
  • each ion implantation region may be activated collectively by one heat treatment, or may be activated by heat treatment every time ion implantation is performed.
  • the front surface side of silicon carbide semiconductor substrate 40 is thermally oxidized to form an oxide film to be gate insulating film 6.
  • This thermal oxidation may be performed by heat treatment at a temperature of about 1000 ° C. in a mixed atmosphere of oxygen (O 2 ) and hydrogen (H 2 ).
  • O 2 oxygen
  • H 2 hydrogen
  • a polycrystalline silicon layer (polysilicon (poly-Si) layer) doped with, for example, phosphorus (P) is formed as the gate electrode 8 on the gate insulating film 6.
  • the polycrystalline silicon layer is patterned and selectively removed, and polycrystalline silicon is formed on the portion of p-type base layer 3 sandwiched between n + -type source region 4 and n ⁇ -type silicon carbide epitaxial layer 2 Leave a layer. At this time, a polycrystalline silicon layer may be left on the n ⁇ -type silicon carbide epitaxial layer 2.
  • phosphorus glass PSG: Phospho Silicate Glass
  • the thickness of the interlayer insulating film 9 may be 1.0 ⁇ m.
  • interlayer insulating film 9 and gate insulating film 6 are patterned and selectively removed to form a contact hole, thereby exposing n + -type source region 4 and p ++ -type contact region 5.
  • heat treatment is performed to planarize the interlayer insulating film 9.
  • FIG. 8 the structure shown in FIG. 8 is obtained.
  • the source electrode 10 is formed on the surface of the interlayer insulating film 9 on the gate electrode 8. At this time, the source electrode 10 is buried also in the contact hole, and the n + -type source region 4 and the p ++ -type contact region 5 are brought into contact with the source electrode 10. Next, the source electrode 10 other than the contact hole is selectively removed.
  • a nickel film for example, is formed as the drain electrode 14 on the surface of the n + -type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate 40). Then, heat treatment is performed, for example, at a temperature of 970 ° C. to form an ohmic junction between the n + -type silicon carbide substrate 1 and the drain electrode 14.
  • an electrode pad serving as a gate electrode pad (not shown) and a source electrode pad is covered by, for example, sputtering to cover source electrode 10 and interlayer insulating film 9 on the entire front surface of silicon carbide semiconductor substrate 40. accumulate.
  • the thickness of the portion on the interlayer insulating film 9 of the electrode pad may be, for example, 5 ⁇ m.
  • the electrode pad may be made of, for example, aluminum (Al—Si) containing silicon at a ratio of 1%.
  • the electrode pad is selectively removed.
  • titanium (Ti), nickel (Ni) and gold (Au), for example, are formed in this order as drain electrode pads on the surface of the drain electrode 14.
  • a protective film may be formed on the surface. Thereby, the silicon carbide semiconductor device shown in FIG. 1 and FIG. 2 is completed.
  • the n + -type source region has a rectangular shape, and all four corner portions are chamfered.
  • the concentration of the electric field at the corners is reduced by the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode. Therefore, in the silicon carbide semiconductor device of the present configuration, the breakdown resistance of the gate insulating film is improved.
  • FIG. 10 is a top view showing the structure of the silicon carbide semiconductor device according to the second embodiment.
  • the cross-sectional view taken along the line AA 'of FIG. 10 showing the structure of the silicon carbide semiconductor device according to the second embodiment is the same as the cross-sectional view of the first embodiment (FIG. 2).
  • the impurity concentration of the corner of the n + -type source region 4 is n + -type It is lower than the impurity concentration of the portion other than the corner of the source region 4 and that the p ++ -type contact region 5 is not chamfered.
  • the n + -type source region 4 according to the second embodiment includes the corner S and a portion T other than the corner, and the impurity concentration of the corner S is the same as the portion T other than the corner or Lower than part T.
  • the corner S here corresponds to the portion removed when rounding the rectangular corner of the n + -type source region 4 in the first embodiment.
  • the distance R3 from the rectangular corner P of the n + -type source region 4 to the portion T other than the corner be 5% or more and 30% or less of the width W of the n + -type source region 4.
  • FIG. 12 is an enlarged view of a portion B of FIG. 10 showing another structure of the silicon carbide semiconductor device according to the second embodiment.
  • the corner S in FIG. 12 corresponds to the portion removed when the rectangle of the n + -type source region 4 is cut out in the first embodiment.
  • the distance R4 from the corner P of the rectangle of the n + -type source region 4 to the portion T other than the corner is 5% or more and 30% or less of the width W of the n + -type source region 4 Is preferred.
  • the n + -type source region 4 is formed in a portion where the impurity concentration in the corner is other than the corner. It may be formed to be the same as or lower than the impurity concentration.
  • n-type impurities are ion-implanted into the p-type base layer 3 using the mask 12 of FIG. 9 of the first embodiment. Thereafter, using a mask having an opening in a region where the n + type source region 4 of p-type base layer 3 is formed, the n-type impurity is formed by performing ion implantation into the p-type base layer 3.
  • two-stage ion implantation is used here, three or more stages of ion implantation may be used.
  • the impurity concentration of the corner is It can be lower than the impurity concentration of the part.
  • the impurity concentration of the corners of the n + -type source region is lower than the impurity concentration of the portion other than the corner portion of the n + -type source region .
  • FIG. 13 is a cross-sectional view showing a structure of a trench type silicon carbide MOSFET according to the first and second embodiments.
  • reference numerals 21 to 32 and 38 denote an n + -type silicon carbide substrate, an n ⁇ -type drift layer, a first p + -type region, a second p + -type region, an n-type region, a p-type base layer, and an n + -type, respectively.
  • the gate electrode 30 is provided in a stripe shape.
  • planarized carbonization is performed by chamfering the corner of the n + -type source region 27 or setting the impurity concentration of the corner lower than the impurity concentration of the portion other than the corner. Similar to the silicon MOSFET, the breakdown tolerance of the gate insulating film 29 can be improved.
  • the first p + -type region 23 in contact with the gate insulating film 29 is provided at the bottom of the trench 38. Therefore, by chamfering the corner of the first p + -type region 23 or setting the impurity concentration of the corner lower than the impurity concentration of the portion other than the corner, the gate is the same as in the case of the n + -type source region 27. The breakdown resistance of the insulating film 29 can be improved.
  • the main surface of the silicon carbide substrate made of silicon carbide is described as the (0001) plane and the MOS is formed on the (0001) plane.
  • the present invention is not limited thereto.
  • the semiconductor, the plane orientation of the main surface of the substrate, and the like can be variously changed.
  • planar and trench MOSFETs have been described as an example, but the present invention is not limited to this, and semiconductor devices of various configurations such as MOS semiconductor devices such as IGBTs having stripe-shaped gate electrodes are described. It is applicable.
  • MOS semiconductor devices such as IGBTs having stripe-shaped gate electrodes
  • GaN gallium nitride
  • the first conductivity type is n-type
  • the second conductivity type is p-type.
  • the present invention similarly applies the first conductivity type to p-type and the second conductivity type to n-type. It holds.
  • the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for a high breakdown voltage semiconductor device used for a power conversion device or a power supply device such as various industrial machines.

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Abstract

This silicon carbide semiconductor device is provided with a first conductivity-type first semiconductor layer (2) provided on the front surface of a first conductivity-type silicon carbide semiconductor substrate (1), a second conductivity-type second conductor layer (3), a first conductivity-type first semiconductor region (4), and stripe-shaped gate electrodes (8) provided with a gate insulating film (6) interposed therebetween. The second semiconductor layer (3) and the first semiconductor region (4) are provided alternately in a direction parallel to the aforementioned stripe shape, and the corners of the first semiconductor region (4) are chamfered.

Description

炭化珪素半導体装置および炭化珪素半導体装置の製造方法Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
　この発明は、炭化珪素半導体装置および炭化珪素半導体装置の製造方法に関する。 The present invention relates to a silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device.
　従来、高電圧や大電流を制御するパワー半導体装置の構成材料として、シリコン（Ｓｉ）が用いられている。パワー半導体装置は、バイポーラトランジスタやＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ：絶縁ゲート型バイポーラトランジスタ）、ＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ：絶縁ゲート型電界効果トランジスタ）など複数種類あり、これらは用途に合わせて使い分けられている。 Conventionally, silicon (Si) is used as a constituent material of a power semiconductor device that controls high voltage and large current. There are multiple types of power semiconductor devices such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used according to applications. It is done.
　例えば、バイポーラトランジスタやＩＧＢＴは、ＭＯＳＦＥＴに比べて電流密度は高く大電流化が可能であるが、高速にスイッチングさせることができない。具体的には、バイポーラトランジスタは数ｋＨｚ程度のスイッチング周波数での使用が限界であり、ＩＧＢＴは数十ｋＨｚ程度のスイッチング周波数での使用が限界である。一方、パワーＭＯＳＦＥＴは、バイポーラトランジスタやＩＧＢＴに比べて電流密度が低く大電流化が難しいが、数ＭＨｚ程度までの高速スイッチング動作が可能である。 For example, bipolar transistors and IGBTs have higher current densities and can be made larger than MOSFETs, but can not be switched at high speed. Specifically, the use of the bipolar transistor is limited at a switching frequency of about several kHz, and the use of an IGBT is limited at a switching frequency of about several tens of kHz. On the other hand, power MOSFETs have lower current density and are difficult to increase in current as compared to bipolar transistors and IGBTs, but high-speed switching operation up to about several MHz is possible.
　しかしながら、市場では大電流と高速性とを兼ね備えたパワー半導体装置への要求が強く、ＩＧＢＴやパワーＭＯＳＦＥＴはその改良に力が注がれ、現在ではほぼ材料限界に近いところまで開発が進んでいる。パワー半導体装置の観点からシリコンに代わる半導体材料が検討されており、低オン電圧、高速特性、高温特性に優れた次世代のパワー半導体装置を作製（製造）可能な半導体材料として炭化珪素（ＳｉＣ）が注目を集めている。 However, in the market, there is a strong demand for power semiconductor devices having both high current and high speed, and efforts are being made to improve IGBTs and power MOSFETs, and development is currently progressing to near the material limit. . From the viewpoint of power semiconductor devices, semiconductor materials to replace silicon have been studied, and silicon carbide (SiC) as a semiconductor material capable of producing (manufacturing) next-generation power semiconductor devices excellent in low on voltage, high speed characteristics, and high temperature characteristics. Is attracting attention.
　炭化珪素は、化学的に非常に安定した半導体材料であり、バンドギャップが３ｅＶと広く、高温でも半導体として極めて安定的に使用することができる。また、炭化珪素は、最大電界強度もシリコンより１桁以上大きいため、オン抵抗を十分に小さくすることができる半導体材料として期待される。このような炭化珪素の特長は、他の、シリコンよりバンドギャップが広いワイドバンドギャップ半導体である、例えば窒化ガリウム（ＧａＮ）にもあてはまる。このため、ワイドバンドギャップ半導体を用いることにより、半導体装置の高耐圧化を図ることができる。 Silicon carbide is a chemically very stable semiconductor material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. In addition, silicon carbide is expected as a semiconductor material that can sufficiently reduce the on-resistance because the maximum electric field strength is also larger by one digit or more than that of silicon. Such characteristics of silicon carbide also apply to other wide band gap semiconductors having a wider band gap than silicon, such as gallium nitride (GaN). Therefore, by using the wide band gap semiconductor, the breakdown voltage of the semiconductor device can be increased.
　図１４は、従来の炭化珪素半導体装置の構造を示す上面図である。図１５は、従来の炭化珪素半導体装置の構造を示す図１４のＡ－Ａ’部分の断面図である。ここで、図１５は、後述するゲート絶縁膜１０６、ゲート電極１０８、層間絶縁膜１０９およびソース電極１１０を除去した上面図である。炭化珪素半導体装置として、炭化珪素ＭＯＳＦＥＴ（以下、ＳｉＣ－ＭＯＳＦＥＴ）を例にしている。 FIG. 14 is a top view showing the structure of a conventional silicon carbide semiconductor device. FIG. 15 is a cross-sectional view of a portion A-A 'in FIG. 14 showing a structure of a conventional silicon carbide semiconductor device. Here, FIG. 15 is a top view from which a gate insulating film 106, a gate electrode 108, an interlayer insulating film 109, and a source electrode 110 which will be described later are removed. As a silicon carbide semiconductor device, a silicon carbide MOSFET (hereinafter, SiC-MOSFET) is taken as an example.
　図１５に示すように、ＳｉＣ－ＭＯＳＦＥＴは、ｎ+型炭化珪素基板１０１のおもて面にｎ-型炭化珪素エピタキシャル層１０２が堆積され、ｎ-型炭化珪素エピタキシャル層１０２の表面にｐ型ベース層１０３が選択的に設けられる。また、ｐ型ベース層１０３の表面にｎ+型ソース領域１０４、ｐ++型コンタクト領域１０５が選択的に設けられる。 As shown in FIG. 15, in the SiC-MOSFET, an n − -type silicon carbide epitaxial layer 102 is deposited on the front surface of the n + -type silicon carbide substrate 101, and a p-type on the surface of the n − -type silicon carbide epitaxial layer 102 The base layer 103 is selectively provided. Further, an n + -type source region 104 and a p ++ -type contact region 105 are selectively provided on the surface of the p-type base layer 103.
　ｐ型ベース層１０３およびｎ+型ソース領域１０４との表面に、ゲート絶縁膜１０６を介してストライプ形状のゲート電極１０８が設けられている。また、ｎ-型炭化珪素エピタキシャル層１０２、ｐ++型コンタクト領域１０５およびｎ+型ソース領域１０４の表面に、ソース電極１１０が設けられている。層間絶縁膜１０９によって、ソース電極１１０とゲート電極１０８とが絶縁されている。また、ｎ+型炭化珪素基板１０１の裏面には、ドレイン電極１１４が設けられている。 A stripe-shaped gate electrode 108 is provided on the surface of the p-type base layer 103 and the n + -type source region 104 with the gate insulating film 106 interposed therebetween. In addition, source electrodes 110 are provided on the surfaces of n − type silicon carbide epitaxial layer 102, p ++ type contact region 105 and n + type source region 104. The interlayer insulating film 109 insulates the source electrode 110 from the gate electrode 108. In addition, a drain electrode 114 is provided on the back surface of the n + -type silicon carbide substrate 101.
　また、図１４に示すように、ｐ型ベース層１０３はストライプ形状に設けられ、ストライプ形状と平行な方向にｐ型ベース層１０３とｎ+型ソース領域１０４が交互に設けられている。 Further, as shown in FIG. 14, the p-type base layer 103 is provided in a stripe shape, and p-type base layers 103 and n + -type source regions 104 are alternately provided in a direction parallel to the stripe shape.
　また、ソース領域の上にｐ型不純物領域が形成され、ｐ型不純物領域の上にｎ型不純物領域が形成され、ｐ型不純物領域及びｎ型不純物領域の各側面が、基板の主面に対して９０度以外の角度を有していてもよいし、該各側面が曲率を持っていてもよい半導体装置が公知である（例えば、特許文献１参照）。また、半導体基板の素子領域において、隅部を矩形の角部にそれと４５゜の角度で交わる直線を用いて切り取った形状からなるＣ面または隅部をＲ面に形成する半導体装置が公知である（例えば、特許文献２参照）。 Further, a p-type impurity region is formed on the source region, an n-type impurity region is formed on the p-type impurity region, and the side surfaces of the p-type impurity region and the n-type impurity region are with respect to the main surface of the substrate. There is known a semiconductor device which may have an angle other than 90 degrees, and each side surface may have a curvature (see, for example, Patent Document 1). In addition, a semiconductor device is known in which a C surface or a corner is formed on an R surface in a device region of a semiconductor substrate, the corner being cut off using a straight line intersecting the corner of the rectangle at an angle of 45 ° (See, for example, Patent Document 2).
特許第５２２３０４１号公報Patent No. 5223041 特開平９－３２０９７９号公報Unexamined-Japanese-Patent No. 9-320979
　ここで、図１６は、従来のシリコン半導体装置のｐ型ベース層、ｎ+型ソース領域の製造途中の状態を示す断面図である。シリコン半導体装置の場合は、まず、ｎ+型珪素基板２０１のおもて面にｎ-型珪素エピタキシャル層２０２を形成する。その後、ｎ-型珪素エピタキシャル層２０２の表面にゲート絶縁膜１０６、ゲート電極１０８および層間絶縁膜１０９を形成後、イオン注入とイオン拡散によりｐ型ベース層１０３、ｎ+型ソース領域１０４を形成していた。 Here, FIG. 16 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon semiconductor device. In the case of a silicon semiconductor device, first, the n − -type silicon epitaxial layer 202 is formed on the front surface of the n + -type silicon substrate 201. Thereafter, gate insulating film 106, gate electrode 108 and interlayer insulating film 109 are formed on the surface of n - type silicon epitaxial layer 202, and then p type base layer 103 and n + type source region 104 are formed by ion implantation and ion diffusion. It was
　具体的には、層間絶縁膜１０９を形成後、層間絶縁膜１０９をマスクとして、イオン注入法によって、ｐ型の不純物をイオン注入する。この後の熱処理（アニール）により、ｐ型の不純物をゲート電極１０８側に熱拡散させてｐ型ベース層１０３を形成した。その後、層間絶縁膜１０９をマスクとして、イオン注入法によって、ｎ型の不純物をイオン注入し、ｎ+型ソース領域１０４を形成した。 Specifically, after the interlayer insulating film 109 is formed, p-type impurities are ion-implanted by ion implantation using the interlayer insulating film 109 as a mask. By the subsequent heat treatment (annealing), the p-type impurity is thermally diffused to the gate electrode 108 side to form the p-type base layer 103. Thereafter, using the interlayer insulating film 109 as a mask, n-type impurities are ion-implanted by ion implantation to form an n + -type source region 104.
　これに対して、炭化珪素は、不純物が熱拡散しにくい材料であり、長時間の熱処理では炭化珪素の表面の結晶構造が損傷するため、炭化珪素半導体装置は、シリコン半導体装置と同様に製造することができなかった。図１７、図１８は、従来の炭化珪素半導体装置のｐ型ベース層、ｎ+型ソース領域の製造途中の状態を示す断面図である。まず、図１７に示すように、フォトリソグラフィ技術によって所望の開口部を有するマスク１２０を、例えば酸化膜で形成する。そして、この酸化膜１２０をマスクとしてイオン注入法によってｐ型の不純物をイオン注入する。それによって、ｎ-型炭化珪素エピタキシャル層１０２の表面層に、ｐ型ベース層１０３が形成される。 On the other hand, silicon carbide is a material in which the impurities are not easily diffused thermally, and the long-term heat treatment damages the crystal structure of the surface of silicon carbide, so the silicon carbide semiconductor device is manufactured in the same manner as the silicon semiconductor device. I could not. FIG. 17 and FIG. 18 are cross-sectional views showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device. First, as shown in FIG. 17, a mask 120 having a desired opening is formed of, for example, an oxide film by photolithography. Then, p-type impurities are ion-implanted by the ion implantation method using the oxide film 120 as a mask. Thereby, p-type base layer 103 is formed on the surface layer of n − -type silicon carbide epitaxial layer 102.
　次に、図１８に示すように、フォトリソグラフィ技術によって所望の開口部を有するマスク１２１を、例えば酸化膜で形成する。そして、この酸化膜１２１をマスクとしてイオン注入法によってｎ型の不純物をイオン注入する。それによって、ｐ型ベース層１０３の表面層に、ｎ+型ソース領域１０４が形成される。 Next, as shown in FIG. 18, a mask 121 having a desired opening is formed of, for example, an oxide film by photolithography. Then, n-type impurities are ion-implanted by the ion implantation method using the oxide film 121 as a mask. Thereby, n + -type source region 104 is formed in the surface layer of p-type base layer 103.
　図１９は、従来の炭化珪素半導体装置のｐ型ベース層、ｎ+型ソース領域の構造を示す上面図である。上述のように、ｎ+型ソース領域１０４はイオン注入により形成されるため、ｎ+型ソース領域１０４の隅部Ｓは、他の部分に比べて不純物濃度が高く形成されてしまう。隅部Ｓは、不純物濃度が高いため、抵抗が低くなる。このため、ゲート電極１０８の過電圧、ドレイン電極１１４に印加された際に加わるゲート電極１０８への強い電界により、隅部Ｓに電界が集中し、ｎ+型ソース領域１０４の隅部Ｓと対向するゲート絶縁膜１０６に高い電界が印加され、ゲート絶縁膜１０６が破壊されるおそれがある。例えば、ゲート絶縁膜１０６に対する破壊試験を行うとｎ+型ソース領域１０４の隅部Ｓと対向するゲート絶縁膜１０６が破壊される。 FIG. 19 is a top view showing the structure of the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device. As described above, since the n + -type source region 104 is formed by ion implantation, the corner S of the n + -type source region 104 is formed to have a higher impurity concentration than other portions. The corner S has a high impurity concentration, so the resistance is low. Therefore, due to the overvoltage of the gate electrode 108 and the strong electric field applied to the gate electrode 108 when applied to the drain electrode 114, the electric field is concentrated at the corner S and faces the corner S of the n + -type source region 104. A high electric field is applied to the gate insulating film 106, and the gate insulating film 106 may be broken. For example, when a destructive test is performed on the gate insulating film 106, the gate insulating film 106 facing the corner S of the n + -type source region 104 is broken.
　この発明は、上述した従来技術による問題点を解消するため、ゲート電極の過電圧、ドレイン電極に印加された際に加わるゲート電極への強い電界に対して、ゲート絶縁膜の破壊耐量を改善する炭化珪素半導体装置および炭化珪素半導体装置の製造方法を提供することを目的とする。 In order to solve the above-mentioned problems of the prior art, the present invention improves the breakdown resistance of the gate insulating film with respect to the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode. An object of the present invention is to provide a method of manufacturing a silicon semiconductor device and a silicon carbide semiconductor device.
　上述した課題を解決し、本発明の目的を達成するため、この発明にかかる炭化珪素半導体装置は、次の特徴を有する。第１導電型の炭化珪素半導体基板のおもて面に、前記炭化珪素半導体基板より低不純物濃度の第１導電型の第１半導体層が設けられる。前記第１半導体層の、前記炭化珪素半導体基板側に対して反対側の表面層に選択的に第２導電型の第２半導体層が設けられる。前記第２半導体層の、前記炭化珪素半導体基板側に対して反対側の表面層に選択的に第１導電型の第１半導体領域が設けられる。前記第１半導体領域と前記第１半導体層とに挟まれた前記第２半導体層の表面上の少なくとも一部にゲート絶縁膜を介してストライプ形状のゲート電極が設けられる。前記第１半導体領域と前記第２半導体層の表面に第１電極が設けられる。前記炭化珪素半導体基板の裏面に第２電極が設けられる。前記第１半導体領域の表面隅部の不純物濃度が、前記第１半導体領域の表面の隅部以外の部分の不純物濃度と同じもしくはより低い。 In order to solve the problems described above and to achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. A first conductivity type first semiconductor layer having an impurity concentration lower than that of the silicon carbide semiconductor substrate is provided on the front surface of the first conductivity type silicon carbide semiconductor substrate. A second semiconductor layer of the second conductivity type is selectively provided on the surface layer of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side. A first semiconductor region of a first conductivity type is selectively provided in the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side. A stripe-shaped gate electrode is provided on at least a portion of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer via a gate insulating film. A first electrode is provided on the surface of the first semiconductor region and the second semiconductor layer. A second electrode is provided on the back surface of the silicon carbide semiconductor substrate. The impurity concentration of the surface corner of the first semiconductor region is the same as or lower than the impurity concentration of the portion other than the corner of the surface of the first semiconductor region.
　また、この発明にかかる炭化珪素半導体装置は、上述した発明において、前記第１半導体領域の表面隅部が面取りされていることを特徴とする。 In the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the surface corner portion of the first semiconductor region is chamfered.
　また、この発明にかかる炭化珪素半導体装置は、上述した発明において、前記第２半導体層の、前記炭化珪素半導体基板側に対して反対側の表面層に選択的に第２導電型の第２半導体領域をさらに有し、前記第２半導体領域の表面隅部は面取りされていることを特徴とする。 Further, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the second semiconductor of the second conductivity type is selectively provided on the surface layer opposite to the silicon carbide semiconductor substrate side of the second semiconductor layer. The semiconductor device may further include a region, and a surface corner of the second semiconductor region is chamfered.
　また、この発明にかかる炭化珪素半導体装置は、上述した発明において、前記第１半導体領域は表面が矩形の形状であり、前記矩形の角が丸められている、または、前記矩形の角が切り取られていることを特徴とする。 In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first semiconductor region has a rectangular surface, and the corners of the rectangle are rounded or the corners of the rectangle are cut off. It is characterized by
　また、この発明にかかる炭化珪素半導体装置は、上述した発明において、前記第１半導体領域は、前記第１半導体領域の幅の５％以上３０％以下の長さ、前記矩形の角が丸められている、または、前記矩形の角が切り取られていることを特徴とする。 In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first semiconductor region has a length of 5% to 30% of the width of the first semiconductor region, and the rectangular corner is rounded. Or the corners of the rectangle are cut off.
　上述した課題を解決し、本発明の目的を達成するため、この発明にかかる炭化珪素半導体装置の製造方法は、次の特徴を有する。まず、第１導電型の炭化珪素半導体基板のおもて面に、前記炭化珪素半導体基板より低不純物濃度の第１導電型の第１半導体層を形成する第１工程を行う。次に、前記第１半導体層の、前記炭化珪素半導体基板側に対して反対側の表面層に選択的に第２導電型の第２半導体層を形成する第２工程を行う。次に、前記第２半導体層の、前記炭化珪素半導体基板側に対して反対側の表面層に選択的に第１導電型の第１半導体領域を形成する第３工程を行う。次に、前記第１半導体領域と前記第１半導体層とに挟まれた前記第２半導体層の表面上の少なくとも一部にゲート絶縁膜を介してストライプ形状のゲート電極を形成する第４工程を行う。次に、前記第１半導体領域と前記第２半導体層の表面に第１電極を形成する第５工程を行う。次に、前記炭化珪素半導体基板の裏面に第２電極を形成する第６工程を行う。前記第３工程では、表面隅部の不純物濃度が表面の隅部以外の部分の不純物濃度と同じもしくはより低い前記第１半導体領域を形成することを特徴とする。 In order to solve the problems described above and to achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step of forming a first semiconductor layer of the first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is performed on the front surface of the silicon carbide semiconductor substrate of the first conductivity type. Next, a second step of selectively forming a second semiconductor layer of the second conductivity type on the surface layer opposite to the silicon carbide semiconductor substrate side of the first semiconductor layer is performed. Next, a third step of selectively forming a first semiconductor region of the first conductivity type is performed in the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side. Next, a fourth step of forming a stripe-shaped gate electrode via a gate insulating film on at least a part of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer is described. Do. Next, a fifth step of forming a first electrode on the surfaces of the first semiconductor region and the second semiconductor layer is performed. Next, a sixth step of forming a second electrode on the back surface of the silicon carbide semiconductor substrate is performed. The third step is characterized in that the first semiconductor region is formed such that the impurity concentration of the surface corner is equal to or lower than the impurity concentration of the portion other than the surface corner.
　また、この発明にかかる炭化珪素半導体装置の製造方法は、上述した発明において、前記第３工程では、隅部が面取りされた前記第１半導体領域を形成することを特徴とする。 Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, in the third step, the first semiconductor region in which a corner is chamfered is formed.
　また、この発明にかかる炭化珪素半導体装置の製造方法は、上述した発明において、前記第２半導体層の前記炭化珪素半導体基板側に対して反対側の表面層に選択的に第２導電型の第２半導体領域を形成する工程さらに有し、前記第２半導体領域の表面隅部は面取りされていることを特徴とする。 Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the second conductive layer is selectively formed on the surface layer opposite to the silicon carbide semiconductor substrate side of the second semiconductor layer. The method further includes the step of forming a semiconductor region, wherein a surface corner of the second semiconductor region is chamfered.
　上述した発明によれば、ｎ+型ソース領域（第１導電型の第１半導体領域）は矩形の形状であり、４つの隅部すべてが面取りされている。これにより、ゲート電極の過電圧、ドレイン電極に印加された際に加わるゲート電極への強い電界により、隅部に電界が集中することが軽減される。このため、本構成の炭化珪素半導体装置は、ゲート絶縁膜の破壊耐量が改善される。 According to the invention described above, the n + -type source region (the first semiconductor region of the first conductivity type) has a rectangular shape, and all four corners are chamfered. As a result, the concentration of the electric field at the corners is reduced by the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode. Therefore, in the silicon carbide semiconductor device of the present configuration, the breakdown resistance of the gate insulating film is improved.
　本発明にかかる炭化珪素半導体装置および炭化珪素半導体装置の製造方法によれば、ゲート電極の過電圧、ドレイン電極に印加された際に加わるゲート電極への強い電界に対して、ゲート絶縁膜の破壊耐量を改善するという効果を奏する。 According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention, the breakdown resistance of the gate insulating film against the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode. The effect of improving the
図１Ａは、実施の形態１にかかる炭化珪素半導体装置の構造を示す上面図である。FIG. 1A is a top view showing a structure of a silicon carbide semiconductor device according to a first embodiment. 図１Ｂは、実施の形態１にかかる炭化珪素半導体装置の構造を示す上面図である。FIG. 1B is a top view showing the structure of the silicon carbide semiconductor device according to the first embodiment. 図１Ｃは、実施の形態１にかかる炭化珪素半導体装置の構造を示す上面図である。FIG. 1C is a top view showing the structure of the silicon carbide semiconductor device according to the first embodiment. 図２は、実施の形態１にかかる炭化珪素半導体装置の構造を示す図１ＢのＡ－Ａ’部分の断面図である。FIG. 2 is a cross-sectional view of the A-A ′ portion of FIG. 1B showing the structure of the silicon carbide semiconductor device according to the first embodiment. 図３は、実施の形態１にかかる炭化珪素半導体装置の構造を示す図１ＡのＢ部分の拡大図である。FIG. 3 is an enlarged view of a portion B of FIG. 1A showing the structure of the silicon carbide semiconductor device according to the first embodiment. 図４は、実施の形態１にかかる炭化珪素半導体装置の他の構造を示す図１ＡのＢ部分の拡大図である。FIG. 4 is an enlarged view of a portion B of FIG. 1A showing another structure of the silicon carbide semiconductor device according to the first embodiment. 図５は、実施の形態１にかかる炭化珪素半導体装置の製造途中の状態を示す断面図である（その１）。FIG. 5 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (part 1). 図６は、実施の形態１にかかる炭化珪素半導体装置の製造途中の状態を示す断面図である（その２）。FIG. 6 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (part 2). 図７は、実施の形態１にかかる炭化珪素半導体装置の製造途中の状態を示す断面図である（その３）。FIG. 7 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 3). 図８は、実施の形態１にかかる炭化珪素半導体装置の製造途中の状態を示す断面図である（その４）。FIG. 8 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (part 4). 図９は、実施の形態１にかかる炭化珪素半導体装置のｎ+型ソース領域の製造途中の状態を示す上面図である。FIG. 9 is a top view showing a state in the middle of manufacture of the n + -type source region of the silicon carbide semiconductor device according to the first embodiment. 図１０は、実施の形態２にかかる炭化珪素半導体装置の構造を示す上面図である。FIG. 10 is a top view showing the structure of the silicon carbide semiconductor device according to the second embodiment. 図１１は、実施の形態２にかかる炭化珪素半導体装置の構造を示す図１０のＢ部分の拡大図である。11 is an enlarged view of a portion B of FIG. 10 showing the structure of the silicon carbide semiconductor device according to the second embodiment. 図１２は、実施の形態２にかかる炭化珪素半導体装置の他の構造を示す図１０のＢ部分の拡大図である。FIG. 12 is an enlarged view of a portion B of FIG. 10 showing another structure of the silicon carbide semiconductor device according to the second embodiment. 図１３は、実施の形態１、２にかかるトレンチ型の炭化珪素ＭＯＳＦＥＴの構造を示す断面図である。FIG. 13 is a cross-sectional view showing a structure of a trench type silicon carbide MOSFET according to the first and second embodiments. 図１４は、従来の炭化珪素半導体装置の構造を示す上面図である。FIG. 14 is a top view showing the structure of a conventional silicon carbide semiconductor device. 図１５は、従来の炭化珪素半導体装置の構造を示す図１４のＡ－Ａ’部分の断面図である。FIG. 15 is a cross-sectional view of a portion A-A 'in FIG. 14 showing a structure of a conventional silicon carbide semiconductor device. 図１６は、従来のシリコン半導体装置のｐ型ベース層、ｎ+型ソース領域の製造途中の状態を示す断面図である。FIG. 16 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon semiconductor device. 図１７は、従来の炭化珪素半導体装置のｐ型ベース層、ｎ+型ソース領域の製造途中の状態を示す断面図である（その１）。FIG. 17 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device (part 1). 図１８は、従来の炭化珪素半導体装置のｐ型ベース層、ｎ+型ソース領域の製造途中の状態を示す断面図である（その２）。FIG. 18 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device (part 2). 図１９は、従来の炭化珪素半導体装置のｐ型ベース層、ｎ+型ソース領域の構造を示す上面図である。FIG. 19 is a top view showing the structure of the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device.
　以下に添付図面を参照して、この発明にかかる炭化珪素半導体装置および炭化珪素半導体装置の製造方法の好適な実施の形態を詳細に説明する。本明細書および添付図面においては、ｎまたはｐを冠記した層や領域では、それぞれ電子または正孔が多数キャリアであることを意味する。また、ｎやｐに付す＋および－は、それぞれそれが付されていない層や領域よりも高不純物濃度および低不純物濃度であることを意味する。＋および－を含めたｎやｐの表記が同じ場合は近い濃度であることを示し濃度が同等とは限らない。なお、以下の実施の形態の説明および添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。また、本明細書では、ミラー指数の表記において、“－”はその直後の指数につくバーを意味しており、指数の前に“－”を付けることで負の指数をあらわしている。 Hereinafter, preferred embodiments of a silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail with reference to the attached drawings. In the present specification and the accompanying drawings, in the layer or region having n or p, it is meant that electrons or holes are majority carriers, respectively. In addition, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. When the notation of n and p including + and-is the same, it indicates that the concentration is close, and the concentration is not necessarily the same. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals and redundant description will be omitted. Further, in the present specification, in the notation of Miller index, "-" means a bar attached to the index immediately after that, and a negative index is represented by putting "-" in front of the index.
（実施の形態１）
　本発明にかかる半導体装置は、ワイドバンドギャップ半導体を用いて構成される。実施の形態においては、ワイドバンドギャップ半導体として例えば炭化珪素（ＳｉＣ）を用いて作製された炭化珪素半導体装置について、ＭＯＳＦＥＴを例に説明する。図１Ａ、図１Ｂ、図１Ｃは、実施の形態１にかかる炭化珪素半導体装置の構造を示す上面図である。これ以降、図１Ａ、図１Ｂ、図１Ｃのすべてに対応する場合、図１と記載する。図２は、実施の形態１にかかる炭化珪素半導体装置の構造を示す図１ＢのＡ－Ａ’部分の断面図である。 Embodiment 1
The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a MOSFET as an example. 1A, 1B, and 1C are top views showing the structure of the silicon carbide semiconductor device according to the first embodiment. Hereinafter, when corresponding to all of FIG. 1A, FIG. 1B, and FIG. 1C, it describes as FIG. FIG. 2 is a cross-sectional view of the AA ′ portion of FIG. 1B showing the structure of the silicon carbide semiconductor device according to the first embodiment.
　図１および図２に示すように、実施の形態にかかる炭化珪素半導体装置は、炭化珪素からなる半導体基体（以下、炭化珪素半導体基体（半導体基板（半導体チップ））とする）４０のおもて面側には、ＭＯＳ（金属－酸化膜－半導体からなる絶縁ゲート）構造（素子構造）が形成されている。具体的には、炭化珪素からなるｎ+型炭化珪素基板（第１導電型の炭化珪素半導体基板）１のおもて面上に、炭化珪素からなるｎ-型炭化珪素エピタキシャル層（第１導電型の第１半導体層）２を積層してなる。ｎ-型炭化珪素エピタキシャル層２の、ｎ型炭化珪素基板１側に対して反対側（基体おもて面側）の表面層には、ｐ型ベース層（第２導電型の第２半導体層）３が選択的に設けられている。 As shown in FIGS. 1 and 2, the silicon carbide semiconductor device according to the embodiment includes a semiconductor substrate made of silicon carbide (hereinafter, referred to as a silicon carbide semiconductor substrate (semiconductor substrate (semiconductor chip)) 40. On the surface side, a MOS (insulated gate made of metal-oxide film-semiconductor) structure (element structure) is formed. Specifically, an n − -type silicon carbide epitaxial layer (first conductive) made of silicon carbide is formed on the front surface of an n + -type silicon carbide substrate (silicon carbide semiconductor substrate of the first conductivity type) made of silicon carbide (first conductive) The first semiconductor layer 2 of the mold is laminated. A p-type base layer (a second semiconductor layer of the second conductivity type) is provided on the surface layer of the n - type silicon carbide epitaxial layer 2 on the opposite side (base front side) to the n-type silicon carbide substrate 1 side. 3) is provided selectively.
　ｐ型ベース層３の表面には、ｎ+型ソース領域（第１導電型の第１半導体領域）４およびｐ++型コンタクト領域５が設けられている。また、ｎ+型ソース領域４およびｐ++型コンタクト領域５は互いに接する。ｎ+型ソース領域４は、ｐ++型コンタクト領域５の外周に配置されている。 An n + -type source region (first semiconductor region of the first conductivity type) 4 and a p ++ -type contact region 5 are provided on the surface of the p-type base layer 3. Also, the n + -type source region 4 and the p ++ -type contact region 5 are in contact with each other. The n + -type source region 4 is disposed at the outer periphery of the p ++ -type contact region 5.
　また、ｐ型ベース層３の、ｎ+型ソース領域４とｎ-型炭化珪素エピタキシャル層２とに挟まれた部分の表面には、ゲート絶縁膜６を介してゲート電極８が設けられている。ゲート電極８は、ゲート絶縁膜６を介して、ｎ-型炭化珪素エピタキシャル層２の表面に設けられていてもよい。 Further, gate electrode 8 is provided on the surface of a portion of p-type base layer 3 sandwiched by n + -type source region 4 and n − -type silicon carbide epitaxial layer 2 through gate insulating film 6. . Gate electrode 8 may be provided on the surface of n -- type silicon carbide epitaxial layer 2 via gate insulating film 6.
　層間絶縁膜９は、炭化珪素半導体基体４０のおもて面側の全面に、ゲート電極８を覆うように設けられている。ソース電極（第１電極）１０は、層間絶縁膜９に開口されたコンタクトホールを介して、ｎ+型ソース領域４およびｐ++型コンタクト領域５に接する。ソース電極１０は、層間絶縁膜９によって、ゲート電極８と電気的に絶縁されている。ソース電極１０上には、電極パッド（不図示）が設けられている。 Interlayer insulating film 9 is provided on the entire top surface of silicon carbide semiconductor substrate 40 so as to cover gate electrode 8. Source electrode (first electrode) 10 is in contact with n + -type source region 4 and p ++ -type contact region 5 via a contact hole opened in interlayer insulating film 9. Source electrode 10 is electrically insulated from gate electrode 8 by interlayer insulating film 9. An electrode pad (not shown) is provided on the source electrode 10.
　図１に示すように、ｐ型ベース層３はストライプ形状に設けられている。微細化によりｐ型ベース層３が細くなって、ｎ+型ソース領域４等がパターニングできなくなるため、ｐ型ベース層３の中にストライプ状のｎ+型ソース領域４が設けられ、ｎ+型ソース領域４の中に複数のｐ++型コンタクト領域５が設けられている。このようにして、ストライプ形状と平行な方向にｐ++型コンタクト領域５とｎ+型ソース領域４とが交互に設けられている。また、実施の形態１では、ｎ+型ソース領域４は矩形の形状であり、４つの隅部すべてが面取りされている。ここで、隅部とは、ｐ型ベース層３で囲まれたｎ+型ソース領域４の角の部分であり、面取りとは、角を削り取って面を作ることである。また、ｐ++型コンタクト領域５も矩形の形状であり、４つの隅部すべてが面取りされている。 As shown in FIG. 1, the p-type base layer 3 is provided in a stripe shape. Tapered p-type base layer 3 by miniaturization, since the n + -type source region 4 and the like can not be patterned, striped n + -type source region 4 in the p-type base layer 3 is formed, n + -type A plurality of p ++ -type contact regions 5 are provided in source region 4. Thus, p ++ -type contact regions 5 and n + -type source regions 4 are alternately provided in the direction parallel to the stripe shape. In the first embodiment, the n + -type source region 4 has a rectangular shape, and all four corners are chamfered. Here, the corner portion is a corner portion of the n + -type source region 4 surrounded by the p-type base layer 3, and the chamfering is to cut the corner to form a surface. The p ++ -type contact region 5 is also rectangular in shape, and all four corners are chamfered.
　このように、実施の形態１ではｎ+型ソース領域４とｐ++型コンタクト領域５の隅部が面取りされているため、ｎ+型ソース領域４とｐ++型コンタクト領域５の隅部に不純物濃度が高い部分がない。このため、ゲート電極８の過電圧、ドレイン電極１４に印加された際に加わるゲート電極８への強い電界により、隅部に電界が集中することが軽減され、ゲート絶縁膜６の破壊耐量が改善される。 Thus, in the first embodiment, the corners of n + -type source region 4 and p ++ -type contact region 5 are chamfered, so the corners of n + -type source region 4 and p ++ -type contact region 5 There is no part where the impurity concentration is high. Therefore, the concentration of the electric field at the corners is alleviated by the overvoltage of the gate electrode 8 and the strong electric field applied to the gate electrode 8 when applied to the drain electrode 14, and the breakdown resistance of the gate insulating film 6 is improved. Ru.
　また、図３は、実施の形態１にかかる炭化珪素半導体装置の構造を示す図１ＡのＢ部分の拡大図である。図３に示すように、矩形の角を丸めることで、隅部を面取りすることができる。矩形の角を丸める量は、少なすぎると隅部に電界が集中することを軽減できず、多すぎるとｎ+型ソース領域４の面積が減り無効領域が増える。このため、矩形の角を丸める量は、ｎ+型ソース領域４の幅Ｗの５％以上３０％以下であることが好ましい。矩形の角を丸める量とは、面取りする前の矩形の角と面取りした後の面との距離Ｒ１である。同様に、ｐ++型コンタクト領域５の矩形の角を丸める量も、ｐ++型コンタクト領域５の幅の５％以上３０％以下であることが好ましい。 3 is an enlarged view of a portion B of FIG. 1A showing the structure of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 3, the corners can be chamfered by rounding the corners of the rectangle. If the amount of rounding the corners of the rectangle is too small, concentration of the electric field at the corners can not be alleviated, and if too large, the area of the n + -type source region 4 decreases and the ineffective region increases. Therefore, it is preferable that the amount of rounding the corner of the rectangle is 5% or more and 30% or less of the width W of the n + -type source region 4. The amount by which the corner of the rectangle is rounded is the distance R1 between the corner of the rectangle before chamfering and the surface after chamfering. Similarly, the amount of rounding the corners of a rectangle of p ++ type contact region 5 is also preferably 30% or less than 5% of the width of the p ++ type contact region 5.
　また、図４は、実施の形態１にかかる炭化珪素半導体装置の他の構造を示す図１ＡのＢ部分の拡大図である。図４に示すように、角を切り取ることで、隅部を面取りすることができる。矩形の角を切り取る量は、図３の矩形の角を丸める量と同様の理由により、ｎ+型ソース領域４の幅Ｗの５％以上３０％以下であることが好ましい。矩形の角を切り取る量とは、切り取る前の矩形の角と切り取った後の面との距離Ｒ２である。ｐ++型コンタクト領域５の矩形の角を切り取る量も同様に、ｐ++型コンタクト領域５の幅の５％以上３０％以下であることが好ましい。 4 is an enlarged view of a portion B of FIG. 1A showing another structure of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 4, the corners can be chamfered by cutting the corners. The amount by which the corner of the rectangle is cut out is preferably 5% or more and 30% or less of the width W of the n + -type source region 4 for the same reason as the amount by which the corner of the rectangle in FIG. 3 is rounded. The amount by which the corner of the rectangle is cut is the distance R2 between the corner before the cut and the surface after being cut. Similarly, the amount by which the rectangular corner of the p ++ -type contact region 5 is cut out is preferably 5% or more and 30% or less of the width of the p ++ -type contact region 5.
　なお、図１、図３、図４では、ｎ+型ソース領域４とｐ++型コンタクト領域５の双方の隅部が面取りされているが、隅部を面取りするのはｎ+型ソース領域４のみとしてもよい。この構成でも隅部に電界が集中することを軽減できる。また、図１Ａでは１つのストライプ状のｐ型ベース層３の中に１つのｎ+型ソース領域４を設けているが、複数のｎ+型ソース領域４を設けても構わない。この場合、ｐ++型コンタクト領域５は、図１Ｂのようにｎ+型ソース領域４の中に設けてもよいし、図１Ｃのようにｎ+型ソース領域４と交互に並べてもよい。 In FIG. 1, FIG. 3 and FIG. 4, the corners of both the n + -type source region 4 and the p ++ -type contact region 5 are chamfered, but the chamfering of the corners is the n + -type source region Only 4 may be used. This configuration can reduce the concentration of the electric field at the corners. Although one n + -type source region 4 is provided in one stripe-like p-type base layer 3 in FIG. 1A, a plurality of n + -type source regions 4 may be provided. In this case, the p ++ -type contact region 5 may be provided in the n + -type source region 4 as shown in FIG. 1B or may be alternately arranged with the n + -type source region 4 as shown in FIG. 1C.
（実施の形態１にかかる炭化珪素半導体装置の製造方法）
　次に、実施の形態１にかかる炭化珪素半導体装置の製造方法について説明する。図５～図８は、実施の形態１にかかる炭化珪素半導体装置の製造途中の状態を模式的に示す断面図である。 (Method of Manufacturing Silicon Carbide Semiconductor Device According to First Embodiment)
Next, a method of manufacturing the silicon carbide semiconductor device according to the first embodiment will be described. 5 to 8 are cross sectional views schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment.
　まず、例えば２×１０19／ｃｍ3程度の不純物濃度で窒素（Ｎ2）がドーピングされたｎ+型炭化珪素基板１を用意する。ｎ+型炭化珪素基板１は、主面が例えば、＜１１－２０＞方向に４度程度のオフ角を有する（０００－１）面であってもよい。次に、ｎ+型炭化珪素基板１の（０００－１）面上に、１．０×１０16／ｃｍ3の不純物濃度で窒素がドーピングされた厚さ１０μｍ程度のｎ-型炭化珪素エピタキシャル層２を成長させる。ここで、図５に示される構造となる。 First, an n + -type silicon carbide substrate 1 doped with nitrogen (N 2 ) at an impurity concentration of, for example, about 2 × 10 19 / cm 3 is prepared. The n + -type silicon carbide substrate 1 may have, for example, a (000-1) plane whose main surface has an off angle of about 4 degrees in the <11-20> direction. Next, an n − -type silicon carbide epitaxial layer with a thickness of about 10 μm doped with nitrogen at an impurity concentration of 1.0 × 10 16 / cm 3 on the (000-1) plane of n + -type silicon carbide substrate 1 Grow two. Here, the structure shown in FIG. 5 is obtained.
　次に、フォトリソグラフィおよびエッチングによりイオン注入用の酸化膜マスクを形成し、イオン注入によってｎ-型炭化珪素エピタキシャル層２の表面層に、ｐ型ベース層３を選択的に形成する。このイオン注入では、例えば、ドーパントをアルミニウム（Ａｌ）とし、ｐ型ベース層３の不純物濃度が１×１０16～１×１０18／ｃｍ3となるようにドーズ量を設定してもよい。ここで、図６に示される構造となる。 Next, by photolithography and etching to form an oxide film mask for ion implantation, n by ion implantation - the mold surface layer of the silicon carbide epitaxial layer 2 is selectively formed p-type base layer 3. In this ion implantation, for example, the dopant may be aluminum (Al), and the dose may be set so that the impurity concentration of the p-type base layer 3 is 1 × 10 16 to 1 × 10 18 / cm 3 . Here, the structure shown in FIG. 6 is obtained.
　次に、フォトリソグラフィおよびイオン注入によって、ｐ型ベース層３の表面層に、ｎ+型ソース領域４を選択的に形成する。次に、フォトリソグラフィおよびイオン注入によって、ｐ型ベース層３の表面層に、ｐ++型コンタクト領域５を選択的に形成する。例えば、ドーパントをアルミニウムとし、ｐ++型コンタクト領域５の不純物濃度が１×１０17～１×１０19／ｃｍ3となるようにドーズ量を設定してもよい。ここで、図７に示される構造となる。 Next, the n + -type source region 4 is selectively formed in the surface layer of the p-type base layer 3 by photolithography and ion implantation. Next, the p ++ -type contact region 5 is selectively formed in the surface layer of the p-type base layer 3 by photolithography and ion implantation. For example, the dose may be set such that the dopant is aluminum and the impurity concentration of the p ++ -type contact region 5 is 1 × 10 17 to 1 × 10 19 / cm 3 . Here, the structure shown in FIG. 7 is obtained.
　ここで、ｎ+型ソース領域４を矩形の形状に、４つの隅部すべてが面取りされるように形成する。図９は、実施の形態１にかかる炭化珪素半導体装置のｎ+型ソース領域の製造途中の状態を示す上面図である。例えば、図９に示すように、ｐ型ベース層３のｎ+型ソース領域４が形成される領域に、ｎ+型ソース領域４の隅部に開口部を有するマスク１２を用いることで形成することができる。ｐ++型コンタクト領域５も同様にして、４つの隅部すべてが面取りされた矩形の形状に形成する。 Here, the n + -type source region 4 is formed in a rectangular shape so that all four corners are chamfered. FIG. 9 is a top view showing a state in the middle of manufacture of the n + -type source region of the silicon carbide semiconductor device according to the first embodiment. For example, as shown in FIG. 9, in the region of the p-type base layer 3 where the n + -type source region 4 is formed, the mask 12 having openings at the corners of the n + -type source region 4 is used. be able to. Similarly, the p ++ -type contact region 5 is formed in a rectangular shape in which all four corners are chamfered.
　また、例えば、ｎ+型ソース領域４やｐ++型コンタクト領域５が形成される領域の隅に近づくにつれ、イオン注入で注入される不純物の濃度を薄くすることによっても、４つの隅部すべてが面取りされるように形成することができる。 Further, for example, all the four corners can also be formed by reducing the concentration of the impurity implanted by ion implantation toward the corner of the region where the n + -type source region 4 and the p ++ -type contact region 5 are formed. Can be formed to be chamfered.
　また、ｎ+型ソース領域４、ｐ++型コンタクト領域５を形成する順序は種々変更可能である。 In addition, the order of forming the n + -type source region 4 and the p ++ -type contact region 5 can be changed variously.
　次に、ｐ型ベース層３、ｎ+型ソース領域４およびｐ++型コンタクト領域５を活性化させるための熱処理（アニール）を行う。このときの熱処理温度および熱処理時間は、それぞれ１６２０℃および２分間であってもよい。なお、上述したように１回の熱処理によって各イオン注入領域をまとめて活性化してもよいし、イオン注入を行うたびに熱処理を行って活性化してもよい。 Next, heat treatment (annealing) is performed to activate the p-type base layer 3, the n + -type source region 4 and the p ++ -type contact region 5. The heat treatment temperature and the heat treatment time at this time may be 1620 ° C. and 2 minutes, respectively. As described above, each ion implantation region may be activated collectively by one heat treatment, or may be activated by heat treatment every time ion implantation is performed.
　次に、炭化珪素半導体基体４０のおもて面側を熱酸化し、ゲート絶縁膜６となる酸化膜を形成する。この熱酸化は、酸素（Ｏ2）と水素（Ｈ2）の混合雰囲気中において１０００℃程度の温度の熱処理によって行ってもよい。これにより、ｐ型ベース層３およびｎ-型炭化珪素エピタキシャル層２の表面に形成された各領域がゲート絶縁膜６で覆われる。 Next, the front surface side of silicon carbide semiconductor substrate 40 is thermally oxidized to form an oxide film to be gate insulating film 6. This thermal oxidation may be performed by heat treatment at a temperature of about 1000 ° C. in a mixed atmosphere of oxygen (O 2 ) and hydrogen (H 2 ). Thereby, each region formed on the surface of p type base layer 3 and n − type silicon carbide epitaxial layer 2 is covered with gate insulating film 6.
　次に、ゲート絶縁膜６上に、ゲート電極８として、例えばリン（Ｐ）がドープされた多結晶シリコン層（ポリシリコン（ｐｏｌｙ－Ｓｉ）層）を形成する。次に、多結晶シリコン層をパターニングして選択的に除去し、ｐ型ベース層３の、ｎ+型ソース領域４とｎ-型炭化珪素エピタキシャル層２とに挟まれた部分上に多結晶シリコン層を残す。このとき、ｎ-型炭化珪素エピタキシャル層２上に多結晶シリコン層を残してもよい。 Next, a polycrystalline silicon layer (polysilicon (poly-Si) layer) doped with, for example, phosphorus (P) is formed as the gate electrode 8 on the gate insulating film 6. Next, the polycrystalline silicon layer is patterned and selectively removed, and polycrystalline silicon is formed on the portion of p-type base layer 3 sandwiched between n + -type source region 4 and n − -type silicon carbide epitaxial layer 2 Leave a layer. At this time, a polycrystalline silicon layer may be left on the n − -type silicon carbide epitaxial layer 2.
　次に、ゲート絶縁膜６を覆うように、層間絶縁膜９として例えばリンガラス（ＰＳＧ：Ｐｈｏｓｐｈｏ　Ｓｉｌｉｃａｔｅ　Ｇｌａｓｓ）を成膜する。層間絶縁膜９の厚さは１．０μｍであってもよい。次に、層間絶縁膜９およびゲート絶縁膜６をパターニングして選択的に除去してコンタクトホールを形成し、ｎ+型ソース領域４およびｐ++型コンタクト領域５を露出させる。次に、層間絶縁膜９を平坦化するための熱処理（リフロー）を行う。ここで、図８に示される構造となる。 Next, phosphorus glass (PSG: Phospho Silicate Glass), for example, is formed as the interlayer insulating film 9 so as to cover the gate insulating film 6. The thickness of the interlayer insulating film 9 may be 1.0 μm. Next, interlayer insulating film 9 and gate insulating film 6 are patterned and selectively removed to form a contact hole, thereby exposing n + -type source region 4 and p ++ -type contact region 5. Next, heat treatment (reflow) is performed to planarize the interlayer insulating film 9. Here, the structure shown in FIG. 8 is obtained.
　次に、ゲート電極８上の層間絶縁膜９の表面に、ソース電極１０を成膜する。このとき、コンタクトホール内にもソース電極１０を埋め込み、ｎ+型ソース領域４およびｐ++型コンタクト領域５とソース電極１０とを接触させる。次に、コンタクトホール以外のソース電極１０を選択的に除去する。 Next, the source electrode 10 is formed on the surface of the interlayer insulating film 9 on the gate electrode 8. At this time, the source electrode 10 is buried also in the contact hole, and the n + -type source region 4 and the p ++ -type contact region 5 are brought into contact with the source electrode 10. Next, the source electrode 10 other than the contact hole is selectively removed.
　次に、ｎ+型炭化珪素基板１の表面（炭化珪素半導体基体４０の裏面）に、ドレイン電極１４として例えばニッケル膜を成膜する。そして、例えば９７０℃の温度で熱処理し、ｎ+型炭化珪素基板１とドレイン電極１４とのオーミック接合を形成する。次に、例えばスパッタ法によって、炭化珪素半導体基体４０のおもて面の全面にソース電極１０および層間絶縁膜９を覆うように、ゲート電極パッド（不図示）およびソース電極パッドとなる電極パッドを堆積する。電極パッドの層間絶縁膜９上の部分の厚さは、例えば５μｍであってもよい。電極パッドは、例えば、１％の割合でシリコンを含んだアルミニウム（Ａｌ－Ｓｉ）で形成してもよい。次に、電極パッドを選択的に除去する。 Next, a nickel film, for example, is formed as the drain electrode 14 on the surface of the n + -type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate 40). Then, heat treatment is performed, for example, at a temperature of 970 ° C. to form an ohmic junction between the n + -type silicon carbide substrate 1 and the drain electrode 14. Next, an electrode pad serving as a gate electrode pad (not shown) and a source electrode pad is covered by, for example, sputtering to cover source electrode 10 and interlayer insulating film 9 on the entire front surface of silicon carbide semiconductor substrate 40. accumulate. The thickness of the portion on the interlayer insulating film 9 of the electrode pad may be, for example, 5 μm. The electrode pad may be made of, for example, aluminum (Al—Si) containing silicon at a ratio of 1%. Next, the electrode pad is selectively removed.
　次に、ドレイン電極１４の表面に、ドレイン電極パッドとして例えばチタン（Ｔｉ）、ニッケル（Ｎｉ）および金（Ａｕ）をこの順に成膜する。次に、保護膜を表面に形成してもよい。これにより、図１、図２に示す炭化珪素半導体装置が完成する。 Next, titanium (Ti), nickel (Ni) and gold (Au), for example, are formed in this order as drain electrode pads on the surface of the drain electrode 14. Next, a protective film may be formed on the surface. Thereby, the silicon carbide semiconductor device shown in FIG. 1 and FIG. 2 is completed.
　以上、説明したように、実施の形態１にかかる炭化珪素半導体装置によれば、ｎ+型ソース領域は矩形の形状であり、４つの隅部すべてが面取りされている。これにより、ゲート電極の過電圧、ドレイン電極に印加された際に加わるゲート電極への強い電界により、隅部に電界が集中することが軽減される。このため、本構成の炭化珪素半導体装置は、ゲート絶縁膜の破壊耐量が改善される。 As described above, according to the silicon carbide semiconductor device according to the first embodiment, the n + -type source region has a rectangular shape, and all four corner portions are chamfered. As a result, the concentration of the electric field at the corners is reduced by the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode. Therefore, in the silicon carbide semiconductor device of the present configuration, the breakdown resistance of the gate insulating film is improved.
（実施の形態２）
　次に、実施の形態２にかかる炭化珪素半導体装置の構造について説明する。図１０は、実施の形態２にかかる炭化珪素半導体装置の構造を示す上面図である。実施の形態２にかかる炭化珪素半導体装置の構造を示す図１０のＡ－Ａ’部分の断面図は、実施の形態１の断面図と同様であるために記載を省略する（図２参照）。実施の形態２にかかる炭化珪素半導体装置が実施の形態１にかかる炭化珪素半導体装置の変形例（図１Ｂ）と異なる点は、ｎ+型ソース領域４の隅部の不純物濃度が、ｎ+型ソース領域４の隅部以外の部分の不純物濃度より低いこと、およびｐ++型コンタクト領域５を面取りしていない点である。 Second Embodiment
Next, the structure of the silicon carbide semiconductor device according to the second embodiment will be described. FIG. 10 is a top view showing the structure of the silicon carbide semiconductor device according to the second embodiment. The cross-sectional view taken along the line AA 'of FIG. 10 showing the structure of the silicon carbide semiconductor device according to the second embodiment is the same as the cross-sectional view of the first embodiment (FIG. 2). The difference between the silicon carbide semiconductor device according to the second embodiment and the modification (FIG. 1B) of the silicon carbide semiconductor device according to the first embodiment is that the impurity concentration of the corner of the n + -type source region 4 is n + -type It is lower than the impurity concentration of the portion other than the corner of the source region 4 and that the p ++ -type contact region 5 is not chamfered.
　図１１は、実施の形態２にかかる炭化珪素半導体装置の構造を示す図１０のＢ部分の拡大図である。図１１に示すように、実施の形態２のｎ+型ソース領域４は、隅部Ｓと隅部以外の部分Ｔからなり、隅部Ｓの不純物濃度は、隅部以外の部分Ｔと同じもしくは部分Ｔより低い。また、ここでの隅部Ｓは、実施の形態１においてｎ+型ソース領域４の矩形の角を丸める際に取り除いた部分に該当する。実施の形態１と同様に、隅部Ｓの面積が少なすぎると隅部に電界が集中することを軽減できず、多すぎると不純物濃度の高い部分が減り無効領域が増える。このため、ｎ+型ソース領域４の矩形の角Ｐから隅部以外の部分Ｔまでの距離Ｒ３が、ｎ+型ソース領域４の幅Ｗの５％以上３０％以下であることが好ましい。 11 is an enlarged view of a portion B of FIG. 10 showing the structure of the silicon carbide semiconductor device according to the second embodiment. As shown in FIG. 11, the n + -type source region 4 according to the second embodiment includes the corner S and a portion T other than the corner, and the impurity concentration of the corner S is the same as the portion T other than the corner or Lower than part T. Also, the corner S here corresponds to the portion removed when rounding the rectangular corner of the n + -type source region 4 in the first embodiment. As in the first embodiment, when the area of the corner S is too small, the concentration of the electric field at the corner can not be reduced. When it is too large, the portion with high impurity concentration decreases and the ineffective region increases. Therefore, it is preferable that the distance R3 from the rectangular corner P of the n + -type source region 4 to the portion T other than the corner be 5% or more and 30% or less of the width W of the n + -type source region 4.
　また、図１２は、実施の形態２にかかる炭化珪素半導体装置の他の構造を示す図１０のＢ部分の拡大図である。図１２での隅部Ｓは、実施の形態１においてｎ+型ソース領域４の矩形を切り取った際に取り除いた部分に該当する。図１１と同様の理由により、ｎ+型ソース領域４の矩形の角Ｐから隅部以外の部分Ｔまでの距離Ｒ４が、ｎ+型ソース領域４の幅Ｗの５％以上３０％以下であることが好ましい。 12 is an enlarged view of a portion B of FIG. 10 showing another structure of the silicon carbide semiconductor device according to the second embodiment. The corner S in FIG. 12 corresponds to the portion removed when the rectangle of the n + -type source region 4 is cut out in the first embodiment. For the same reason as FIG. 11, the distance R4 from the corner P of the rectangle of the n + -type source region 4 to the portion T other than the corner is 5% or more and 30% or less of the width W of the n + -type source region 4 Is preferred.
（実施の形態２にかかる炭化珪素半導体装置の製造方法）
　実施の形態２にかかる炭化珪素半導体装置の製造方法は、実施の形態１にかかる炭化珪素半導体装置の製造方法において、ｎ+型ソース領域４を、隅部の不純物濃度が隅部以外の部分の不純物濃度と同じもしくはより低くなるように形成すればよい。 (Method of Manufacturing Silicon Carbide Semiconductor Device According to Second Embodiment)
In the method of manufacturing a silicon carbide semiconductor device according to the second embodiment, in the method of manufacturing the silicon carbide semiconductor device according to the first embodiment, the n + -type source region 4 is formed in a portion where the impurity concentration in the corner is other than the corner. It may be formed to be the same as or lower than the impurity concentration.
　例えば、実施の形態１の図９のマスク１２を用いて、ｎ型の不純物をｐ型ベース層３にイオン注入を行う。この後、ｐ型ベース層３のｎ+型ソース領域４が形成される領域に開口部を持つマスクを用いて、ｎ型の不純物をｐ型ベース層３にイオン注入を行うことで形成する。ここでは２段のイオン注入であったが、３段以上のイオン注入にしてもよい。 For example, n-type impurities are ion-implanted into the p-type base layer 3 using the mask 12 of FIG. 9 of the first embodiment. Thereafter, using a mask having an opening in a region where the n + type source region 4 of p-type base layer 3 is formed, the n-type impurity is formed by performing ion implantation into the p-type base layer 3. Although two-stage ion implantation is used here, three or more stages of ion implantation may be used.
　また、例えば、ｎ+型ソース領域４が形成される領域の隅に近づくにつれ、イオン注入で注入されるｎ型の不純物の濃度を薄くすることによっても、隅部の不純物濃度を隅部以外の部分の不純物濃度より低くすることができる。 Also, for example, as the concentration of the n-type impurity implanted by ion implantation is reduced toward the corner of the region in which the n + -type source region 4 is formed, the impurity concentration of the corner is It can be lower than the impurity concentration of the part.
　以上、説明したように、実施の形態２にかかる炭化珪素半導体装置によれば、ｎ+型ソース領域の隅部の不純物濃度が、ｎ+型ソース領域の隅部以外の部分の不純物濃度より低い。これにより、実施の形態１と同様の効果を得ることができる。 As described above, according to the silicon carbide semiconductor device according to the second embodiment, the impurity concentration of the corners of the n + -type source region is lower than the impurity concentration of the portion other than the corner portion of the n + -type source region . Thereby, the same effect as that of the first embodiment can be obtained.
　上記実施の形態では、プレーナ型の炭化珪素ＭＯＳＦＥＴを例に説明してきたが、本発明は、トレンチ型の炭化珪素ＭＯＳＦＥＴにも適用可能である。図１３は、実施の形態１、２にかかるトレンチ型の炭化珪素ＭＯＳＦＥＴの構造を示す断面図である。 Although the planar silicon carbide MOSFET has been described as an example in the above embodiment, the present invention is also applicable to a trench silicon carbide MOSFET. FIG. 13 is a cross-sectional view showing a structure of a trench type silicon carbide MOSFET according to the first and second embodiments.
　図１３において、符号２１～３２、３８は、それぞれｎ+型炭化珪素基板、ｎ-型ドリフト層、第１ｐ+型領域、第２ｐ+型領域、ｎ型領域、ｐ型ベース層、ｎ+型ソース領域、ｐ+型コンタクト領域、ゲート絶縁膜、ゲート電極、層間絶縁膜、ソース電極、トレンチである。このようなトレンチゲート構造のような縦型ＭＯＳＦＥＴは、ゲート電極３０がストライプ形状に設けられる。 In FIG. 13, reference numerals 21 to 32 and 38 denote an n + -type silicon carbide substrate, an n − -type drift layer, a first p + -type region, a second p + -type region, an n-type region, a p-type base layer, and an n + -type, respectively. A source region, ap + -type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a trench. In a vertical MOSFET such as such a trench gate structure, the gate electrode 30 is provided in a stripe shape.
　また、トレンチ型の炭化珪素ＭＯＳＦＥＴの上面図は、プレーナ型の炭化珪素ＭＯＳＦＥＴのｎ-型炭化珪素エピタキシャル層２をゲート絶縁膜２９、ゲート電極３０に変更する以外同様であるために記載は省略する。このようなトレンチ型の炭化珪素ＭＯＳＦＥＴでも、ｎ+型ソース領域２７の隅部を面取りする、または、隅部の不純物濃度を隅部以外の部分の不純物濃度より低くすることで、プレーナ型の炭化珪素ＭＯＳＦＥＴと同様にゲート絶縁膜２９の破壊耐量を改善することができる。 Further, the top view of a silicon carbide MOSFET trench type, n of the planar-type silicon carbide MOSFET - according to the same except for changing the type silicon carbide epitaxial layer 2 gate insulating film 29, the gate electrode 30 is omitted . Even in such a trench type silicon carbide MOSFET, planarized carbonization is performed by chamfering the corner of the n + -type source region 27 or setting the impurity concentration of the corner lower than the impurity concentration of the portion other than the corner. Similar to the silicon MOSFET, the breakdown tolerance of the gate insulating film 29 can be improved.
　また、トレンチ型の炭化珪素ＭＯＳＦＥＴでは、トレンチ３８の底にゲート絶縁膜２９と接する第１ｐ+型領域２３が設けられている。このため、第１ｐ+型領域２３の隅部を面取りする、または、隅部の不純物濃度を隅部以外の部分の不純物濃度より低くすることで、ｎ+型ソース領域２７の場合と同様にゲート絶縁膜２９の破壊耐量を改善することができる。 Further, in the trench type silicon carbide MOSFET, the first p + -type region 23 in contact with the gate insulating film 29 is provided at the bottom of the trench 38. Therefore, by chamfering the corner of the first p + -type region 23 or setting the impurity concentration of the corner lower than the impurity concentration of the portion other than the corner, the gate is the same as in the case of the n + -type source region 27. The breakdown resistance of the insulating film 29 can be improved.
　以上において本発明では、炭化珪素でできた炭化珪素基板の主面を（０００１）面とし当該（０００１）面上にＭＯＳを構成した場合を例に説明したが、これに限らず、ワイドバンドギャップ半導体、基板主面の面方位などを種々変更可能である。 In the present invention, the main surface of the silicon carbide substrate made of silicon carbide is described as the (0001) plane and the MOS is formed on the (0001) plane. However, the present invention is not limited thereto. The semiconductor, the plane orientation of the main surface of the substrate, and the like can be variously changed.
　また、本発明の実施の形態では、プレーナ型およびトレンチ型ＭＯＳＦＥＴを例に説明したが、これに限らず、ストライプ形状のゲート電極を有するＩＧＢＴなどのＭＯＳ型半導体装置など様々な構成の半導体装置に適用可能である。また、上述した各実施の形態では、ワイドバンドギャップ半導体として炭化珪素を用いた場合を例に説明したが、窒化ガリウム（ＧａＮ）など炭化珪素以外のワイドバンドギャップ半導体を用いた場合においても同様の効果が得られる。また、各実施の形態では第１導電型をｎ型とし、第２導電型をｐ型としたが、本発明は第１導電型をｐ型とし、第２導電型をｎ型としても同様に成り立つ。 In the embodiments of the present invention, planar and trench MOSFETs have been described as an example, but the present invention is not limited to this, and semiconductor devices of various configurations such as MOS semiconductor devices such as IGBTs having stripe-shaped gate electrodes are described. It is applicable. In each of the above-described embodiments, although the case of using silicon carbide as the wide band gap semiconductor has been described as an example, the same applies to the case of using a wide band gap semiconductor other than silicon carbide such as gallium nitride (GaN). An effect is obtained. In each embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. However, the present invention similarly applies the first conductivity type to p-type and the second conductivity type to n-type. It holds.
　以上のように、本発明にかかる炭化珪素半導体装置および炭化珪素半導体装置の製造方法は、電力変換装置や種々の産業用機械などの電源装置などに使用される高耐圧半導体装置に有用である。 As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for a high breakdown voltage semiconductor device used for a power conversion device or a power supply device such as various industrial machines.
　１、１０１　ｎ+型炭化珪素基板
　２、１０２　ｎ-型炭化珪素エピタキシャル層
　３、１０３　ｐ型ベース層
　４、１０４　ｎ+型ソース領域
　５、１０５　ｐ++型コンタクト領域
　６、１０６　ゲート絶縁膜
　８、１０８　ゲート電極
　９、１０９　層間絶縁膜
１０、１１０　ソース電極
１２、１２０、１２１　マスク
１４、１１４　ドレイン電極
２１　ｎ+型炭化珪素基板
２２　ｎ-型ドリフト層
２３　第１ｐ+型領域
２４　第２ｐ+型領域
２５　ｎ型領域
２６　ｐ型ベース層
２７　ｎ+型ソース領域
２８　ｐ+型コンタクト領域
２９　ゲート絶縁膜
３０　ゲート電極
３１　層間絶縁膜
３２　ソース電極
３８　トレンチ
４０、１４０　炭化珪素半導体基体
２０１　ｎ+型珪素基板
２０２　ｎ-型珪素エピタキシャル層 1, 101 n + type silicon carbide substrate 2, 102 n − type silicon carbide epitaxial layer 3, 103 p type base layer 4, 104 n + type source region 5, 105 p ++ type contact region 6, 106 gate insulating film 8 , 108 gate electrode 9, 109 interlayer insulating film 10, 110 source electrode 12, 120, 121 mask 14, 114 drain electrode 21 n + type silicon carbide substrate 22 n − type drift layer 23 first p + type region 24 second p + type Region 25 n-type region 26 p-type base layer 27 n + -type source region 28 p + -type contact region 29 gate insulating film 30 gate electrode 31 interlayer insulating film 32 source electrode 38 trench 40, 140 silicon carbide semiconductor substrate 201 n + -type silicon Substrate 202 n - type silicon epitaxial layer

Claims (8)

  1. 　第１導電型の炭化珪素半導体基板と、
    　前記炭化珪素半導体基板のおもて面に設けられた、前記炭化珪素半導体基板より低不純物濃度の第１導電型の第１半導体層と、
    　前記第１半導体層の、前記炭化珪素半導体基板側に対して反対側の表面層に選択的に設けられた第２導電型の第２半導体層と、
    　前記第２半導体層の、前記炭化珪素半導体基板側に対して反対側の表面層に選択的に設けられた第１導電型の第１半導体領域と、
    　前記第１半導体領域と前記第１半導体層とに挟まれた前記第２半導体層の表面上の少なくとも一部にゲート絶縁膜を介して設けられたストライプ形状のゲート電極と、
    　前記第１半導体領域と前記第２半導体層の表面に設けられた第１電極と、
    　前記炭化珪素半導体基板の裏面に設けられた第２電極と、
    　を備え、
    　前記第１半導体領域の表面隅部の不純物濃度が、前記第１半導体領域の表面の隅部以外の部分の不純物濃度と同じもしくはより低いことを特徴とする炭化珪素半導体装置。     A first conductivity type silicon carbide semiconductor substrate,
    A first semiconductor layer of a first conductivity type provided on the front surface of the silicon carbide semiconductor substrate and having a lower impurity concentration than the silicon carbide semiconductor substrate;
    A second semiconductor layer of a second conductivity type selectively provided on a surface layer opposite to the silicon carbide semiconductor substrate side of the first semiconductor layer;
    A first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side;
    A stripe-shaped gate electrode provided via a gate insulating film on at least a portion of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer;
    A first electrode provided on the surface of the first semiconductor region and the second semiconductor layer;
    A second electrode provided on the back surface of the silicon carbide semiconductor substrate;
    Equipped with
    The silicon carbide semiconductor device characterized in that the impurity concentration of the surface corner of the first semiconductor region is the same as or lower than the impurity concentration of the portion other than the corner of the surface of the first semiconductor region.
  2. 　前記第１半導体領域の表面隅部が面取りされていることを特徴とする請求項１に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1, wherein a surface corner of the first semiconductor region is chamfered.
  3. 　前記第２半導体層の、前記炭化珪素半導体基板側に対して反対側の表面層に選択的に第２導電型の第２半導体領域をさらに有し、
    　前記第２半導体領域の表面隅部は面取りされていることを特徴とする請求項２に記載の炭化珪素半導体装置。     The semiconductor device further comprises a second semiconductor region of the second conductivity type selectively on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side,
    The silicon carbide semiconductor device according to claim 2, wherein a surface corner of the second semiconductor region is chamfered.
  4. 　前記第１半導体領域は表面が矩形の形状であり、前記矩形の角が丸められている、または、前記矩形の角が切り取られていることを特徴とする請求項２に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 2, wherein the first semiconductor region has a rectangular surface, and the corners of the rectangle are rounded or the corners of the rectangle are cut off. .
  5. 　前記第１半導体領域は、前記第１半導体領域の幅の５％以上３０％以下の長さ、前記矩形の角が丸められている、または、前記矩形の角が切り取られていることを特徴とする請求項４に記載の炭化珪素半導体装置。 The first semiconductor region has a length of 5% to 30% of the width of the first semiconductor region, and the corner of the rectangle is rounded, or the corner of the rectangle is cut off. The silicon carbide semiconductor device according to claim 4.
  6. 　第１導電型の炭化珪素半導体基板のおもて面に、前記炭化珪素半導体基板より低不純物濃度の第１導電型の第１半導体層を形成する第１工程と、
    　前記第１半導体層の、前記炭化珪素半導体基板側に対して反対側の表面層に選択的に第２導電型の第２半導体層を形成する第２工程と、
    　前記第２半導体層の、前記炭化珪素半導体基板側に対して反対側の表面層に選択的に第１導電型の第１半導体領域を形成する第３工程と、
    　前記第１半導体領域と前記第１半導体層とに挟まれた前記第２半導体層の表面上の少なくとも一部にゲート絶縁膜を介してストライプ形状のゲート電極を形成する第４工程と、
    　前記第１半導体領域と前記第２半導体層の表面に第１電極を形成する第５工程と、
    　前記炭化珪素半導体基板の裏面に第２電極を形成する第６工程と、
    　を含み、
    　前記第３工程では、表面隅部の不純物濃度が表面の隅部以外の部分の不純物濃度と同じもしくはより低い前記第１半導体領域を形成することを特徴とする炭化珪素半導体装置の製造方法。     A first step of forming a first conductive first semiconductor layer having a lower impurity concentration than the silicon carbide semiconductor substrate on a front surface of the first conductive silicon carbide semiconductor substrate;
    A second step of selectively forming a second semiconductor layer of a second conductivity type on a surface layer of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side;
    A third step of selectively forming a first semiconductor region of a first conductivity type in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side;
    Forming a stripe-shaped gate electrode via a gate insulating film on at least a portion of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer;
    Forming a first electrode on surfaces of the first semiconductor region and the second semiconductor layer;
    A sixth step of forming a second electrode on the back surface of the silicon carbide semiconductor substrate;
    Including
    In the third step, the first semiconductor region is formed, wherein the impurity concentration of the surface corner is the same as or lower than the impurity concentration of the portion other than the corner of the surface.
  7. 　前記第３工程では、隅部が面取りされた前記第１半導体領域を形成することを特徴とする請求項６に記載の炭化珪素半導体装置の製造方法。 The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein in the third step, the first semiconductor region whose corner is chamfered is formed.
  8. 　前記第２半導体層の前記炭化珪素半導体基板側に対して反対側の表面層に選択的に第２導電型の第２半導体領域を形成する工程さらに有し、
    　前記第２半導体領域の表面隅部は面取りされていることを特徴とする請求項７に記載の炭化珪素半導体装置の製造方法。     The method further includes the step of selectively forming a second semiconductor region of the second conductivity type in a surface layer opposite to the silicon carbide semiconductor substrate side of the second semiconductor layer.
    8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein a surface corner of the second semiconductor region is chamfered.
PCT/JP2018/031239 2017-10-17 2018-08-23 Silicon carbide semiconductor device, and manufacturing method of silicon carbide semiconductor device WO2019077878A1 (en)

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