WO2019077878A1 - Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication associé - Google Patents

Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication associé Download PDF

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WO2019077878A1
WO2019077878A1 PCT/JP2018/031239 JP2018031239W WO2019077878A1 WO 2019077878 A1 WO2019077878 A1 WO 2019077878A1 JP 2018031239 W JP2018031239 W JP 2018031239W WO 2019077878 A1 WO2019077878 A1 WO 2019077878A1
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silicon carbide
type
semiconductor
semiconductor device
carbide semiconductor
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PCT/JP2018/031239
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Japanese (ja)
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保幸 星
悠一 橋爪
熊田　恵志郎
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富士電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the present invention relates to a silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device.
  • silicon is used as a constituent material of a power semiconductor device that controls high voltage and large current.
  • power semiconductor devices such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used according to applications. It is done.
  • bipolar transistors and IGBTs have higher current densities and can be made larger than MOSFETs, but can not be switched at high speed.
  • the use of the bipolar transistor is limited at a switching frequency of about several kHz
  • the use of an IGBT is limited at a switching frequency of about several tens of kHz.
  • power MOSFETs have lower current density and are difficult to increase in current as compared to bipolar transistors and IGBTs, but high-speed switching operation up to about several MHz is possible.
  • SiC silicon carbide
  • Silicon carbide is a chemically very stable semiconductor material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures.
  • silicon carbide is expected as a semiconductor material that can sufficiently reduce the on-resistance because the maximum electric field strength is also larger by one digit or more than that of silicon.
  • Such characteristics of silicon carbide also apply to other wide band gap semiconductors having a wider band gap than silicon, such as gallium nitride (GaN). Therefore, by using the wide band gap semiconductor, the breakdown voltage of the semiconductor device can be increased.
  • FIG. 14 is a top view showing the structure of a conventional silicon carbide semiconductor device.
  • FIG. 15 is a cross-sectional view of a portion A-A 'in FIG. 14 showing a structure of a conventional silicon carbide semiconductor device.
  • FIG. 15 is a top view from which a gate insulating film 106, a gate electrode 108, an interlayer insulating film 109, and a source electrode 110 which will be described later are removed.
  • a silicon carbide semiconductor device a silicon carbide MOSFET (hereinafter, SiC-MOSFET) is taken as an example.
  • an n ⁇ -type silicon carbide epitaxial layer 102 is deposited on the front surface of the n + -type silicon carbide substrate 101, and a p-type on the surface of the n ⁇ -type silicon carbide epitaxial layer 102
  • the base layer 103 is selectively provided.
  • an n + -type source region 104 and a p ++ -type contact region 105 are selectively provided on the surface of the p-type base layer 103.
  • a stripe-shaped gate electrode 108 is provided on the surface of the p-type base layer 103 and the n + -type source region 104 with the gate insulating film 106 interposed therebetween.
  • source electrodes 110 are provided on the surfaces of n ⁇ type silicon carbide epitaxial layer 102, p ++ type contact region 105 and n + type source region 104.
  • the interlayer insulating film 109 insulates the source electrode 110 from the gate electrode 108.
  • a drain electrode 114 is provided on the back surface of the n + -type silicon carbide substrate 101.
  • the p-type base layer 103 is provided in a stripe shape, and p-type base layers 103 and n + -type source regions 104 are alternately provided in a direction parallel to the stripe shape.
  • a p-type impurity region is formed on the source region, an n-type impurity region is formed on the p-type impurity region, and the side surfaces of the p-type impurity region and the n-type impurity region are with respect to the main surface of the substrate.
  • a semiconductor device which may have an angle other than 90 degrees, and each side surface may have a curvature (see, for example, Patent Document 1).
  • a semiconductor device is known in which a C surface or a corner is formed on an R surface in a device region of a semiconductor substrate, the corner being cut off using a straight line intersecting the corner of the rectangle at an angle of 45 ° (See, for example, Patent Document 2).
  • Patent No. 5223041 Unexamined-Japanese-Patent No. 9-320979
  • FIG. 16 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon semiconductor device.
  • the n ⁇ -type silicon epitaxial layer 202 is formed on the front surface of the n + -type silicon substrate 201.
  • gate insulating film 106, gate electrode 108 and interlayer insulating film 109 are formed on the surface of n - type silicon epitaxial layer 202, and then p type base layer 103 and n + type source region 104 are formed by ion implantation and ion diffusion. It was
  • p-type impurities are ion-implanted by ion implantation using the interlayer insulating film 109 as a mask.
  • the p-type impurity is thermally diffused to the gate electrode 108 side to form the p-type base layer 103.
  • n-type impurities are ion-implanted by ion implantation to form an n + -type source region 104.
  • FIG. 17 and FIG. 18 are cross-sectional views showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device.
  • a mask 120 having a desired opening is formed of, for example, an oxide film by photolithography.
  • p-type impurities are ion-implanted by the ion implantation method using the oxide film 120 as a mask.
  • p-type base layer 103 is formed on the surface layer of n ⁇ -type silicon carbide epitaxial layer 102.
  • a mask 121 having a desired opening is formed of, for example, an oxide film by photolithography. Then, n-type impurities are ion-implanted by the ion implantation method using the oxide film 121 as a mask. Thereby, n + -type source region 104 is formed in the surface layer of p-type base layer 103.
  • FIG. 19 is a top view showing the structure of the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device.
  • the corner S of the n + -type source region 104 is formed to have a higher impurity concentration than other portions.
  • the corner S has a high impurity concentration, so the resistance is low. Therefore, due to the overvoltage of the gate electrode 108 and the strong electric field applied to the gate electrode 108 when applied to the drain electrode 114, the electric field is concentrated at the corner S and faces the corner S of the n + -type source region 104.
  • a high electric field is applied to the gate insulating film 106, and the gate insulating film 106 may be broken.
  • the gate insulating film 106 facing the corner S of the n + -type source region 104 is broken.
  • the present invention improves the breakdown resistance of the gate insulating film with respect to the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode.
  • An object of the present invention is to provide a method of manufacturing a silicon semiconductor device and a silicon carbide semiconductor device.
  • the silicon carbide semiconductor device has the following features.
  • a first conductivity type first semiconductor layer having an impurity concentration lower than that of the silicon carbide semiconductor substrate is provided on the front surface of the first conductivity type silicon carbide semiconductor substrate.
  • a second semiconductor layer of the second conductivity type is selectively provided on the surface layer of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side.
  • a first semiconductor region of a first conductivity type is selectively provided in the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side.
  • a stripe-shaped gate electrode is provided on at least a portion of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer via a gate insulating film.
  • a first electrode is provided on the surface of the first semiconductor region and the second semiconductor layer.
  • a second electrode is provided on the back surface of the silicon carbide semiconductor substrate.
  • the impurity concentration of the surface corner of the first semiconductor region is the same as or lower than the impurity concentration of the portion other than the corner of the surface of the first semiconductor region.
  • the surface corner portion of the first semiconductor region is chamfered.
  • the second semiconductor of the second conductivity type is selectively provided on the surface layer opposite to the silicon carbide semiconductor substrate side of the second semiconductor layer.
  • the semiconductor device may further include a region, and a surface corner of the second semiconductor region is chamfered.
  • the first semiconductor region has a rectangular surface, and the corners of the rectangle are rounded or the corners of the rectangle are cut off. It is characterized by
  • the first semiconductor region has a length of 5% to 30% of the width of the first semiconductor region, and the rectangular corner is rounded. Or the corners of the rectangle are cut off.
  • the method for manufacturing a silicon carbide semiconductor device has the following features. First, a first step of forming a first semiconductor layer of the first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is performed on the front surface of the silicon carbide semiconductor substrate of the first conductivity type. Next, a second step of selectively forming a second semiconductor layer of the second conductivity type on the surface layer opposite to the silicon carbide semiconductor substrate side of the first semiconductor layer is performed. Next, a third step of selectively forming a first semiconductor region of the first conductivity type is performed in the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side.
  • a fourth step of forming a stripe-shaped gate electrode via a gate insulating film on at least a part of the surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer is described. Do. Next, a fifth step of forming a first electrode on the surfaces of the first semiconductor region and the second semiconductor layer is performed. Next, a sixth step of forming a second electrode on the back surface of the silicon carbide semiconductor substrate is performed. The third step is characterized in that the first semiconductor region is formed such that the impurity concentration of the surface corner is equal to or lower than the impurity concentration of the portion other than the surface corner.
  • the first semiconductor region in which a corner is chamfered is formed.
  • the second conductive layer is selectively formed on the surface layer opposite to the silicon carbide semiconductor substrate side of the second semiconductor layer.
  • the method further includes the step of forming a semiconductor region, wherein a surface corner of the second semiconductor region is chamfered.
  • the n + -type source region (the first semiconductor region of the first conductivity type) has a rectangular shape, and all four corners are chamfered.
  • the concentration of the electric field at the corners is reduced by the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode. Therefore, in the silicon carbide semiconductor device of the present configuration, the breakdown resistance of the gate insulating film is improved.
  • the breakdown resistance of the gate insulating film against the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode is improved.
  • FIG. 1A is a top view showing a structure of a silicon carbide semiconductor device according to a first embodiment.
  • FIG. 1B is a top view showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 1C is a top view showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view of the A-A ′ portion of FIG. 1B showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 3 is an enlarged view of a portion B of FIG. 1A showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 4 is an enlarged view of a portion B of FIG. 1A showing another structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 1A is a top view showing a structure of a silicon carbide semiconductor device according to a first embodiment.
  • FIG. 1B is a top view showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 5 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (part 1).
  • FIG. 6 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (part 2).
  • FIG. 7 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (No. 3).
  • FIG. 8 is a cross-sectional view showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment (part 4).
  • FIG. 9 is a top view showing a state in the middle of manufacture of the n + -type source region of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 10 is a top view showing the structure of the silicon carbide semiconductor device according to the second embodiment.
  • 11 is an enlarged view of a portion B of FIG. 10 showing the structure of the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 12 is an enlarged view of a portion B of FIG. 10 showing another structure of the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 13 is a cross-sectional view showing a structure of a trench type silicon carbide MOSFET according to the first and second embodiments.
  • FIG. 14 is a top view showing the structure of a conventional silicon carbide semiconductor device.
  • FIG. 15 is a cross-sectional view of a portion A-A 'in FIG. 14 showing a structure of a conventional silicon carbide semiconductor device.
  • FIG. 16 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon semiconductor device.
  • FIG. 17 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device (part 1).
  • FIG. 18 is a cross-sectional view showing a state in the middle of manufacturing the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device (part 2).
  • FIG. 19 is a top view showing the structure of the p-type base layer and the n + -type source region of the conventional silicon carbide semiconductor device.
  • n and p in the layer or region having n or p, it is meant that electrons or holes are majority carriers, respectively.
  • + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively.
  • the notation of n and p including + and-is the same it indicates that the concentration is close, and the concentration is not necessarily the same.
  • Embodiment 1 The semiconductor device according to the present invention is configured using a wide band gap semiconductor.
  • a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a MOSFET as an example.
  • 1A, 1B, and 1C are top views showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view of the AA ′ portion of FIG. 1B showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • the silicon carbide semiconductor device includes a semiconductor substrate made of silicon carbide (hereinafter, referred to as a silicon carbide semiconductor substrate (semiconductor substrate (semiconductor chip)) 40.
  • a MOS insulated gate made of metal-oxide film-semiconductor
  • an n ⁇ -type silicon carbide epitaxial layer (first conductive) made of silicon carbide is formed on the front surface of an n + -type silicon carbide substrate (silicon carbide semiconductor substrate of the first conductivity type) made of silicon carbide (first conductive)
  • the first semiconductor layer 2 of the mold is laminated.
  • a p-type base layer (a second semiconductor layer of the second conductivity type) is provided on the surface layer of the n - type silicon carbide epitaxial layer 2 on the opposite side (base front side) to the n-type silicon carbide substrate 1 side. 3) is provided selectively.
  • n + -type source region (first semiconductor region of the first conductivity type) 4 and a p ++ -type contact region 5 are provided on the surface of the p-type base layer 3. Also, the n + -type source region 4 and the p ++ -type contact region 5 are in contact with each other. The n + -type source region 4 is disposed at the outer periphery of the p ++ -type contact region 5.
  • gate electrode 8 is provided on the surface of a portion of p-type base layer 3 sandwiched by n + -type source region 4 and n ⁇ -type silicon carbide epitaxial layer 2 through gate insulating film 6. . Gate electrode 8 may be provided on the surface of n -- type silicon carbide epitaxial layer 2 via gate insulating film 6.
  • Interlayer insulating film 9 is provided on the entire top surface of silicon carbide semiconductor substrate 40 so as to cover gate electrode 8.
  • Source electrode (first electrode) 10 is in contact with n + -type source region 4 and p ++ -type contact region 5 via a contact hole opened in interlayer insulating film 9.
  • Source electrode 10 is electrically insulated from gate electrode 8 by interlayer insulating film 9.
  • An electrode pad (not shown) is provided on the source electrode 10.
  • the p-type base layer 3 is provided in a stripe shape. Tapered p-type base layer 3 by miniaturization, since the n + -type source region 4 and the like can not be patterned, striped n + -type source region 4 in the p-type base layer 3 is formed, n + -type A plurality of p ++ -type contact regions 5 are provided in source region 4. Thus, p ++ -type contact regions 5 and n + -type source regions 4 are alternately provided in the direction parallel to the stripe shape. In the first embodiment, the n + -type source region 4 has a rectangular shape, and all four corners are chamfered.
  • the corner portion is a corner portion of the n + -type source region 4 surrounded by the p-type base layer 3, and the chamfering is to cut the corner to form a surface.
  • the p ++ -type contact region 5 is also rectangular in shape, and all four corners are chamfered.
  • the corners of n + -type source region 4 and p ++ -type contact region 5 are chamfered, so the corners of n + -type source region 4 and p ++ -type contact region 5 There is no part where the impurity concentration is high. Therefore, the concentration of the electric field at the corners is alleviated by the overvoltage of the gate electrode 8 and the strong electric field applied to the gate electrode 8 when applied to the drain electrode 14, and the breakdown resistance of the gate insulating film 6 is improved. Ru.
  • FIG. 3 is an enlarged view of a portion B of FIG. 1A showing the structure of the silicon carbide semiconductor device according to the first embodiment.
  • the corners can be chamfered by rounding the corners of the rectangle. If the amount of rounding the corners of the rectangle is too small, concentration of the electric field at the corners can not be alleviated, and if too large, the area of the n + -type source region 4 decreases and the ineffective region increases. Therefore, it is preferable that the amount of rounding the corner of the rectangle is 5% or more and 30% or less of the width W of the n + -type source region 4. The amount by which the corner of the rectangle is rounded is the distance R1 between the corner of the rectangle before chamfering and the surface after chamfering. Similarly, the amount of rounding the corners of a rectangle of p ++ type contact region 5 is also preferably 30% or less than 5% of the width of the p ++ type contact region 5.
  • FIG. 4 is an enlarged view of a portion B of FIG. 1A showing another structure of the silicon carbide semiconductor device according to the first embodiment.
  • the corners can be chamfered by cutting the corners.
  • the amount by which the corner of the rectangle is cut out is preferably 5% or more and 30% or less of the width W of the n + -type source region 4 for the same reason as the amount by which the corner of the rectangle in FIG. 3 is rounded.
  • the amount by which the corner of the rectangle is cut is the distance R2 between the corner before the cut and the surface after being cut.
  • the amount by which the rectangular corner of the p ++ -type contact region 5 is cut out is preferably 5% or more and 30% or less of the width of the p ++ -type contact region 5.
  • the corners of both the n + -type source region 4 and the p ++ -type contact region 5 are chamfered, but the chamfering of the corners is the n + -type source region Only 4 may be used. This configuration can reduce the concentration of the electric field at the corners.
  • one n + -type source region 4 is provided in one stripe-like p-type base layer 3 in FIG. 1A, a plurality of n + -type source regions 4 may be provided.
  • the p ++ -type contact region 5 may be provided in the n + -type source region 4 as shown in FIG. 1B or may be alternately arranged with the n + -type source region 4 as shown in FIG. 1C.
  • FIG. 5 to 8 are cross sectional views schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • an n + -type silicon carbide substrate 1 doped with nitrogen (N 2 ) at an impurity concentration of, for example, about 2 ⁇ 10 19 / cm 3 is prepared.
  • the n + -type silicon carbide substrate 1 may have, for example, a (000-1) plane whose main surface has an off angle of about 4 degrees in the ⁇ 11-20> direction.
  • an n ⁇ -type silicon carbide epitaxial layer with a thickness of about 10 ⁇ m doped with nitrogen at an impurity concentration of 1.0 ⁇ 10 16 / cm 3 on the (000-1) plane of n + -type silicon carbide substrate 1 Grow two.
  • the structure shown in FIG. 5 is obtained.
  • the dopant may be aluminum (Al), and the dose may be set so that the impurity concentration of the p-type base layer 3 is 1 ⁇ 10 16 to 1 ⁇ 10 18 / cm 3 .
  • the structure shown in FIG. 6 is obtained.
  • the n + -type source region 4 is selectively formed in the surface layer of the p-type base layer 3 by photolithography and ion implantation.
  • the p ++ -type contact region 5 is selectively formed in the surface layer of the p-type base layer 3 by photolithography and ion implantation.
  • the dose may be set such that the dopant is aluminum and the impurity concentration of the p ++ -type contact region 5 is 1 ⁇ 10 17 to 1 ⁇ 10 19 / cm 3 .
  • the structure shown in FIG. 7 is obtained.
  • FIG. 9 is a top view showing a state in the middle of manufacture of the n + -type source region of the silicon carbide semiconductor device according to the first embodiment.
  • the mask 12 having openings at the corners of the n + -type source region 4 is used. be able to.
  • the p ++ -type contact region 5 is formed in a rectangular shape in which all four corners are chamfered.
  • all the four corners can also be formed by reducing the concentration of the impurity implanted by ion implantation toward the corner of the region where the n + -type source region 4 and the p ++ -type contact region 5 are formed. Can be formed to be chamfered.
  • n + -type source region 4 and the p ++ -type contact region 5 can be changed variously.
  • heat treatment is performed to activate the p-type base layer 3, the n + -type source region 4 and the p ++ -type contact region 5.
  • the heat treatment temperature and the heat treatment time at this time may be 1620 ° C. and 2 minutes, respectively.
  • each ion implantation region may be activated collectively by one heat treatment, or may be activated by heat treatment every time ion implantation is performed.
  • the front surface side of silicon carbide semiconductor substrate 40 is thermally oxidized to form an oxide film to be gate insulating film 6.
  • This thermal oxidation may be performed by heat treatment at a temperature of about 1000 ° C. in a mixed atmosphere of oxygen (O 2 ) and hydrogen (H 2 ).
  • O 2 oxygen
  • H 2 hydrogen
  • a polycrystalline silicon layer (polysilicon (poly-Si) layer) doped with, for example, phosphorus (P) is formed as the gate electrode 8 on the gate insulating film 6.
  • the polycrystalline silicon layer is patterned and selectively removed, and polycrystalline silicon is formed on the portion of p-type base layer 3 sandwiched between n + -type source region 4 and n ⁇ -type silicon carbide epitaxial layer 2 Leave a layer. At this time, a polycrystalline silicon layer may be left on the n ⁇ -type silicon carbide epitaxial layer 2.
  • phosphorus glass PSG: Phospho Silicate Glass
  • the thickness of the interlayer insulating film 9 may be 1.0 ⁇ m.
  • interlayer insulating film 9 and gate insulating film 6 are patterned and selectively removed to form a contact hole, thereby exposing n + -type source region 4 and p ++ -type contact region 5.
  • heat treatment is performed to planarize the interlayer insulating film 9.
  • FIG. 8 the structure shown in FIG. 8 is obtained.
  • the source electrode 10 is formed on the surface of the interlayer insulating film 9 on the gate electrode 8. At this time, the source electrode 10 is buried also in the contact hole, and the n + -type source region 4 and the p ++ -type contact region 5 are brought into contact with the source electrode 10. Next, the source electrode 10 other than the contact hole is selectively removed.
  • a nickel film for example, is formed as the drain electrode 14 on the surface of the n + -type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate 40). Then, heat treatment is performed, for example, at a temperature of 970 ° C. to form an ohmic junction between the n + -type silicon carbide substrate 1 and the drain electrode 14.
  • an electrode pad serving as a gate electrode pad (not shown) and a source electrode pad is covered by, for example, sputtering to cover source electrode 10 and interlayer insulating film 9 on the entire front surface of silicon carbide semiconductor substrate 40. accumulate.
  • the thickness of the portion on the interlayer insulating film 9 of the electrode pad may be, for example, 5 ⁇ m.
  • the electrode pad may be made of, for example, aluminum (Al—Si) containing silicon at a ratio of 1%.
  • the electrode pad is selectively removed.
  • titanium (Ti), nickel (Ni) and gold (Au), for example, are formed in this order as drain electrode pads on the surface of the drain electrode 14.
  • a protective film may be formed on the surface. Thereby, the silicon carbide semiconductor device shown in FIG. 1 and FIG. 2 is completed.
  • the n + -type source region has a rectangular shape, and all four corner portions are chamfered.
  • the concentration of the electric field at the corners is reduced by the overvoltage of the gate electrode and the strong electric field applied to the gate electrode when applied to the drain electrode. Therefore, in the silicon carbide semiconductor device of the present configuration, the breakdown resistance of the gate insulating film is improved.
  • FIG. 10 is a top view showing the structure of the silicon carbide semiconductor device according to the second embodiment.
  • the cross-sectional view taken along the line AA 'of FIG. 10 showing the structure of the silicon carbide semiconductor device according to the second embodiment is the same as the cross-sectional view of the first embodiment (FIG. 2).
  • the impurity concentration of the corner of the n + -type source region 4 is n + -type It is lower than the impurity concentration of the portion other than the corner of the source region 4 and that the p ++ -type contact region 5 is not chamfered.
  • the n + -type source region 4 according to the second embodiment includes the corner S and a portion T other than the corner, and the impurity concentration of the corner S is the same as the portion T other than the corner or Lower than part T.
  • the corner S here corresponds to the portion removed when rounding the rectangular corner of the n + -type source region 4 in the first embodiment.
  • the distance R3 from the rectangular corner P of the n + -type source region 4 to the portion T other than the corner be 5% or more and 30% or less of the width W of the n + -type source region 4.
  • FIG. 12 is an enlarged view of a portion B of FIG. 10 showing another structure of the silicon carbide semiconductor device according to the second embodiment.
  • the corner S in FIG. 12 corresponds to the portion removed when the rectangle of the n + -type source region 4 is cut out in the first embodiment.
  • the distance R4 from the corner P of the rectangle of the n + -type source region 4 to the portion T other than the corner is 5% or more and 30% or less of the width W of the n + -type source region 4 Is preferred.
  • the n + -type source region 4 is formed in a portion where the impurity concentration in the corner is other than the corner. It may be formed to be the same as or lower than the impurity concentration.
  • n-type impurities are ion-implanted into the p-type base layer 3 using the mask 12 of FIG. 9 of the first embodiment. Thereafter, using a mask having an opening in a region where the n + type source region 4 of p-type base layer 3 is formed, the n-type impurity is formed by performing ion implantation into the p-type base layer 3.
  • two-stage ion implantation is used here, three or more stages of ion implantation may be used.
  • the impurity concentration of the corner is It can be lower than the impurity concentration of the part.
  • the impurity concentration of the corners of the n + -type source region is lower than the impurity concentration of the portion other than the corner portion of the n + -type source region .
  • FIG. 13 is a cross-sectional view showing a structure of a trench type silicon carbide MOSFET according to the first and second embodiments.
  • reference numerals 21 to 32 and 38 denote an n + -type silicon carbide substrate, an n ⁇ -type drift layer, a first p + -type region, a second p + -type region, an n-type region, a p-type base layer, and an n + -type, respectively.
  • the gate electrode 30 is provided in a stripe shape.
  • planarized carbonization is performed by chamfering the corner of the n + -type source region 27 or setting the impurity concentration of the corner lower than the impurity concentration of the portion other than the corner. Similar to the silicon MOSFET, the breakdown tolerance of the gate insulating film 29 can be improved.
  • the first p + -type region 23 in contact with the gate insulating film 29 is provided at the bottom of the trench 38. Therefore, by chamfering the corner of the first p + -type region 23 or setting the impurity concentration of the corner lower than the impurity concentration of the portion other than the corner, the gate is the same as in the case of the n + -type source region 27. The breakdown resistance of the insulating film 29 can be improved.
  • the main surface of the silicon carbide substrate made of silicon carbide is described as the (0001) plane and the MOS is formed on the (0001) plane.
  • the present invention is not limited thereto.
  • the semiconductor, the plane orientation of the main surface of the substrate, and the like can be variously changed.
  • planar and trench MOSFETs have been described as an example, but the present invention is not limited to this, and semiconductor devices of various configurations such as MOS semiconductor devices such as IGBTs having stripe-shaped gate electrodes are described. It is applicable.
  • MOS semiconductor devices such as IGBTs having stripe-shaped gate electrodes
  • GaN gallium nitride
  • the first conductivity type is n-type
  • the second conductivity type is p-type.
  • the present invention similarly applies the first conductivity type to p-type and the second conductivity type to n-type. It holds.
  • the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for a high breakdown voltage semiconductor device used for a power conversion device or a power supply device such as various industrial machines.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur au carbure de silicium comprenant : une première couche semi-conductrice de premier type de conductivité (2) disposée sur la surface avant d'un substrat semi-conducteur au carbure de silicium de premier type de conductivité (1) ; une seconde couche conductrice de second type de conductivité (3) ; une première région semi-conductrice de premier type de conductivité (4) ; et des électrodes de grille en bandes (8) disposées avec un film d'isolation de grille (6) disposé entre celles-ci. La seconde couche semi-conductrice (3) et la première région semi-conductrice (4) sont disposées en alternance dans une direction parallèle à la forme de bande susmentionnée, et les coins de la première région semi-conductrice (4) sont chanfreinés.
PCT/JP2018/031239 2017-10-17 2018-08-23 Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication associé WO2019077878A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7451981B2 (ja) 2019-12-10 2024-03-19 富士電機株式会社 半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02154469A (ja) * 1988-12-06 1990-06-13 Fuji Electric Co Ltd 縦形電界効果トランジスタ
WO2009139140A1 (fr) * 2008-05-13 2009-11-19 パナソニック株式会社 Elément semi-conducteur
JP2012033809A (ja) * 2010-08-02 2012-02-16 Fuji Electric Co Ltd Ｍｏｓ型半導体装置
JP2012178536A (ja) * 2011-02-02 2012-09-13 Rohm Co Ltd 半導体装置およびその製造方法
JP2012235001A (ja) * 2011-05-06 2012-11-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2015076437A (ja) * 2013-10-07 2015-04-20 三菱電機株式会社 半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02154469A (ja) * 1988-12-06 1990-06-13 Fuji Electric Co Ltd 縦形電界効果トランジスタ
WO2009139140A1 (fr) * 2008-05-13 2009-11-19 パナソニック株式会社 Elément semi-conducteur
JP2012033809A (ja) * 2010-08-02 2012-02-16 Fuji Electric Co Ltd Ｍｏｓ型半導体装置
JP2012178536A (ja) * 2011-02-02 2012-09-13 Rohm Co Ltd 半導体装置およびその製造方法
JP2012235001A (ja) * 2011-05-06 2012-11-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2015076437A (ja) * 2013-10-07 2015-04-20 三菱電機株式会社 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7451981B2 (ja) 2019-12-10 2024-03-19 富士電機株式会社 半導体装置

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