JP6848316B2 - 半導体装置および半導体装置の製造方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims description 23
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 117
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
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Description
本発明にかかる半導体装置は、半導体材料としてシリコン(Si)よりもバンドギャップの広い半導体(以下、ワイドバンドギャップ半導体とする)を用いて構成される。ここでは、ワイドバンドギャップ半導体として炭化珪素(SiC)を用いて作製(製造)されたエンハンスメント(ノーマリオフ)型の縦型MOSFET(以下、SiC−縦型MOSFETとする)を例に、実施の形態1にかかる半導体装置の構造について説明する。図1は、実施の形態1にかかる半導体装置の構造を示す断面図である。
次に、実施の形態2にかかる半導体装置の構造について説明する。図7は、実施の形態2にかかる半導体装置の構造を示す断面図である。実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、p+型高濃度ベース領域3の、ゲートトレンチ7の側壁に沿った部分を、ゲートトレンチ7の側壁に沿ってドレイン側に延在させた点である。
次に、実施の形態3にかかる半導体装置の構造について説明する。図14は、実施の形態3にかかる半導体装置の構造を示す断面図である。実施の形態3にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、n-型ドリフト領域2の内部に、ゲートトレンチ7の底部の少なくとも一部を覆うp+型領域(第2半導体領域)31が設けられている点である。すなわち、ゲートトレンチ7は、基板おもて面からn-型ドリフト領域2に達し、かつn-型ドリフト領域2の内部においてp+型領域31に達する。
2 n-型ドリフト領域
3 p+型高濃度ベース領域
3a p+型高濃度ベース領域のドレイン側に延在する部分
4 p型ベース領域
4a p型ベース領域のドレイン側に延在する部分
5 n+型ソース領域
6 p++型コンタクト領域
7 ゲートトレンチ
8 ゲート絶縁膜
9 ゲート電極
10 炭化珪素基板
11 層間絶縁膜
12 ソース電極
13 ソースパッド
14 ドレイン電極
15 ドレインパッド
20 単位セル
21〜23 炭化珪素層(エピタキシャル成長層)
24,25 トレンチ
24a,25a トレンチの底部
24b,25b トレンチの側壁
31 ゲートトレンチの少なくとも一部を覆うp+型領域
w1 ゲートトレンチの幅
w2,w4 トレンチの幅
w3 ゲートトレンチの側壁からp+型高濃度ベース領域までの幅
w5 トレンチの側壁から当該トレンチの内部に形成されたトレンチの側壁までの幅
w6 ゲートトレンチの少なくとも一部を覆うp+型領域の幅
Claims (9)
- シリコンよりもバンドギャップの広い半導体からなる半導体基板と、
前記半導体基板のおもて面に設けられた、シリコンよりもバンドギャップの広い半導体からなる第1導電型の第1半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面に設けられた、シリコンよりもバンドギャップの広い半導体からなる第2導電型の第2半導体層と、
前記第2半導体層の両表面間を厚さ方向に貫通して前記第1半導体層に達する第1溝と、
前記第2半導体層の、前記第1半導体層側に対して反対側の表面に設けられ、かつ前記第1溝の内部に埋め込まれた、前記第2半導体層よりも不純物濃度が低く、シリコンよりもバンドギャップの広い半導体からなる第2導電型の第3半導体層と、
前記第3半導体層の内部に選択的に設けられた第1導電型の第1半導体領域と、
前記第1半導体領域および前記第1溝の内部の前記第3半導体層を前記厚さ方向に貫通して前記第1半導体層に達する、前記第1溝よりも幅の狭いトレンチと、
前記トレンチの内壁に沿って設けられたゲート絶縁膜と、
前記トレンチの内部において、前記ゲート絶縁膜上に設けられたゲート電極と、
前記第1半導体領域および前記第3半導体層に電気的に接続された第1電極と、
前記半導体基板の裏面に電気的に接続された第2電極と、
を備え、
前記第1半導体領域は、前記トレンチの側壁の前記ゲート絶縁膜に接しており、
前記第2半導体層は、前記第3半導体層を挟んで、前記トレンチの側壁の前記ゲート絶縁膜に対向しており、
前記第3半導体層は、
エピタキシャル成長層であり、
前記トレンチの底面よりも前記第1電極側に浅い位置に配置され、
前記第2半導体層の、前記第1半導体層側に対して反対側の表面に設けられた部分から、前記第2半導体層と前記トレンチの側壁の前記ゲート絶縁膜との間に設けられた部分にわたって不純物濃度が一様であることを特徴とする半導体装置。 - 前記第1半導体層の、前記半導体基板側に対して反対側の表面から前記厚さ方向に所定の深さで設けられた、前記第1溝よりも幅の広い第2溝をさらに備え、
前記第2半導体層は、前記第2溝に埋め込まれ、
前記第1溝は、前記第2半導体層の、前記第3半導体層側の表面から前記厚さ方向に、前記第2溝の内部の前記第2半導体層を貫通して前記第1半導体層に達することを特徴とする請求項1に記載の半導体装置。 - 前記第1半導体層の内部に、前記第2半導体層および前記第3半導体層と離して設けられ、前記トレンチの底部の少なくとも一部を覆う、前記第3半導体層よりも不純物濃度の高い第2導電型の第2半導体領域をさらに備えることを特徴とする請求項1または2に記載の半導体装置。
- 前記第2半導体層は、エピタキシャル成長層であることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。
- シリコンよりもバンドギャップの広い半導体は炭化珪素であることを特徴とする請求項1〜4のいずれか一つに記載の半導体装置。
- シリコンよりもバンドギャップの広い半導体からなる半導体基板のおもて面に、第1導電型の第1エピタキシャル成長層を堆積する第1工程と、
前記第1エピタキシャル成長層上に、第2導電型の第2エピタキシャル成長層を堆積する第2工程と、
前記第2エピタキシャル成長層の両表面間を厚さ方向に貫通して前記第1エピタキシャル成長層に達する第1溝を形成する第3工程と、
前記第2エピタキシャル成長層上に、前記第2エピタキシャル成長層よりも不純物濃度の低い第2導電型の第3エピタキシャル成長層を堆積し、かつ前記第3エピタキシャル成長層で前記第1溝の内部を埋め込む第4工程と、
前記第3エピタキシャル成長層の内部に、第1導電型の第1半導体領域を選択的に形成する第5工程と、
前記第1半導体領域および前記第1溝の内部の前記第3エピタキシャル成長層を前記厚さ方向に貫通して前記第1エピタキシャル成長層に達する、前記第1溝よりも幅の狭いトレンチを形成する第6工程と、
前記トレンチの内壁に沿ってゲート絶縁膜を形成する第7工程と、
前記トレンチの内部において、前記ゲート絶縁膜上にゲート電極を形成する第8工程と、
前記第1半導体領域および前記第3エピタキシャル成長層に電気的に接続された第1電極を形成する第9工程と、
前記半導体基板の裏面に電気的に接続された第2電極を形成する第10工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第1工程の後、前記第2工程の前に、前記第1エピタキシャル成長層に、前記厚さ方向に所定の深さで、前記第1溝よりも幅の広い第2溝を形成する第11工程をさらに含み、
前記第2工程では、前記第2溝に前記第2エピタキシャル成長層を埋め込み、
前記第3工程では、前記第2エピタキシャル成長層の表面から前記厚さ方向に、前記第2溝の内部の前記第2エピタキシャル成長層を貫通して前記第1エピタキシャル成長層に達する前記第1溝を形成することを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記第1工程の後、前記第2工程の前に、前記第1エピタキシャル成長層の内部に、前記第3エピタキシャル成長層よりも不純物濃度の高い第2導電型の第2半導体領域を形成する第12工程をさらに含み、
前記第6工程では、底部の少なくとも一部が前記第2半導体領域に達する前記トレンチを形成することを特徴とする請求項6または7に記載の半導体装置の製造方法。 - シリコンよりもバンドギャップの広い半導体は炭化珪素であることを特徴とする請求項6〜8のいずれか一つに記載の半導体装置の製造方法。
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