JP6874797B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6874797B2 JP6874797B2 JP2019148138A JP2019148138A JP6874797B2 JP 6874797 B2 JP6874797 B2 JP 6874797B2 JP 2019148138 A JP2019148138 A JP 2019148138A JP 2019148138 A JP2019148138 A JP 2019148138A JP 6874797 B2 JP6874797 B2 JP 6874797B2
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- wide bandgap
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- H01L29/45—Ohmic electrodes
Description
本発明にかかる半導体装置は、ワイドバンドギャップ半導体を用いて構成される。実施の形態においては、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いて作製された炭化珪素半導体装置について、MOSFETを例に説明する。図1Aは、実施の形態1にかかる炭化珪素半導体装置の構成を示す断面図である。
次に、実施の形態にかかる炭化珪素半導体装置の製造方法について説明する。図3〜図8は、実施の形態にかかる炭化珪素半導体装置の製造途中の状態を模式的に示す断面図である。
図9は、実施の形態1にかかる炭化珪素半導体装置の実施例においてトレンチと第2p+型ベース領域との横方向位置にズレが生じた状態の一例を示す断面図である。横方向とは、第1,2p型ベース領域3,4が並ぶ方向である。ここで、合わせズレ量101は、第2p+型ベース領域4の中心とトレンチ16の中心との横方向の距離(単位:μm)であり、p型ベース領域幅102は、第2p+型ベース領域4の幅(単位:μm)であり、トレンチ幅103は、トレンチ16の幅(単位:μm)である。
図12は、本発明の実施の形態2にかかる炭化珪素半導体装置の構成を示す断面図である。図12に示すように、実施の形態2にかかる炭化珪素半導体装置は、n型炭化珪素エピタキシャル層2の内部に、第1p+型ベース領域3の下端部(ドレイン側端部)に接するように第3p型領域3cを設けた構造である。第3p型領域3cは、p型ベース層6および第1p+型ベース領域3とともにベース領域として機能する。
図13は、実施の形態2にかかる炭化珪素半導体装置の製造途中の状態を模式的に示す断面図である。図13に示すように、第1p型領域3a、第2p+型ベース領域4、第1n型領域5aを形成した後、イオン注入時に用いたマスクを除去する。その後、第1n型炭化珪素エピタキシャル層2aの表面上に、フォトリソグラフィ技術によって所望の開口部を有する図示しないマスクを、例えばレジストで形成する。そして、このレジストをマスクとしてイオン注入法によってp型の不純物、例えばアルミニウム原子をイオン注入する。それによって、図13に示すように、第1p型領域3aの下部(ドレイン側端部)に、第1p型領域3aに接するように、例えば厚さ0.25μm程度の第3p型領域3cが、例えば幅1μm程度となるように、形成される。第3p型領域3cを形成する際のイオンのエネルギーを、例えば700keV、ドーズ量を、例えば1×1014/cm2程度となるように設定してもよい。
図14は、実施の形態2にかかる炭化珪素半導体装置の実施例と比較例におけるアバランシェ降伏時の電流分布図である。図14では、実施例として第3p型領域3cを形成した構造(図14(b))と、比較例として第3p型領域3cを形成しない構造(図14(a))によるアバランシェ降伏が起こったときの電流値の面内分布(断面図)の変化を評価した。図14(a)に示すように、比較例ではゲート電極10直下の第2p+型ベース領域4でアバランシェ降伏が起こり、ゲート電極10直下で電流が多く流れることが分かる。一方、図14(b)に示すように、実施例ではアバランシェ降伏が第3p型領域3cで発生し、電流経路がn+ソース領域7から第3p型領域3cを通過しドレイン側へ流れることが確認できる。同様の結果は、第3p型領域3cの厚さが0.1μm以上、幅が第1p+型ベース領域3よりも0.1μm以上狭ければ起こる。
2 n型炭化珪素エピタキシャル層
2a 第1n型炭化珪素エピタキシャル層
2b 第2n型炭化珪素エピタキシャル層
3 第1p+型ベース領域
3a 第1p型領域
3b 第2p型領域
3c 第3p型領域
4 第2p+型ベース領域
5 n型高濃度領域
5a 第1n型領域
5b 第2n型領域
6 p型ベース層
7 n+ソース領域
8 p++コンタクト領域
9 ゲート絶縁膜
10 ゲート電極
11 層間絶縁膜
12 ソース電極
13 ドレイン電極
14 ソース電極パッド
15 ドレイン電極パッド
16 トレンチ
Claims (14)
- シリコンよりもバンドギャップが広い半導体からなる第1導電型のワイドバンドギャップ半導体基板と、
前記ワイドバンドギャップ半導体基板のおもて面に形成された、シリコンよりもバンドギャップが広い半導体からなる、前記ワイドバンドギャップ半導体基板より低不純物濃度の第1導電型ワイドバンドギャップ半導体層と、
前記第1導電型ワイドバンドギャップ半導体層の前記ワイドバンドギャップ半導体基板に対して反対側の表面層に選択的に形成された第2導電型の第1ベース領域と、
前記第1導電型ワイドバンドギャップ半導体層の内部に選択的に形成された第2導電型の第2ベース領域と、
前記第1導電型ワイドバンドギャップ半導体層の前記ワイドバンドギャップ半導体基板に対して反対側の表面層に選択的に形成された、前記第1導電型ワイドバンドギャップ半導体層より高不純物濃度の第1導電型の領域と、
前記第1導電型ワイドバンドギャップ半導体層の前記ワイドバンドギャップ半導体基板に対して反対側の表面に形成された、シリコンよりもバンドギャップが広い半導体からなる第2導電型ワイドバンドギャップ半導体層と、
前記第2導電型ワイドバンドギャップ半導体層の表面層に選択的に形成された第1導電型のソース領域と、
前記第2導電型ワイドバンドギャップ半導体層および前記ソース領域を貫通して前記第1導電型の領域に達するトレンチと、
前記トレンチ内部にゲート絶縁膜を介して形成されたゲート電極と、
前記第2導電型ワイドバンドギャップ半導体層および前記ソース領域に接触するソース電極と、
前記ワイドバンドギャップ半導体基板の裏面に設けられたドレイン電極と、
を備え、
前記第2ベース領域は、前記トレンチと深さ方向に対向する位置のすべてに配置され、
前記第1ベース領域の一部は、前記トレンチ側に延在し、前記第2ベース領域に接続され、
前記第1導電型の領域の下端部は、前記トレンチの底部よりも深くかつ前記第1ベース領域の下端部よりも浅い位置にあり、
前記第1ベース領域の前記ドレイン電極側の角部の曲率半径は、前記第2ベース領域の前記ドレイン電極側の角部の曲率半径より小さく、
前記第2ベース領域の幅は、前記トレンチの幅よりも広いことを特徴とする半導体装置。 - シリコンよりもバンドギャップが広い半導体からなる第1導電型のワイドバンドギャップ半導体基板と、
前記ワイドバンドギャップ半導体基板のおもて面に形成された、シリコンよりもバンドギャップが広い半導体からなる、前記ワイドバンドギャップ半導体基板より低不純物濃度の第1導電型ワイドバンドギャップ半導体層と、
前記第1導電型ワイドバンドギャップ半導体層の前記ワイドバンドギャップ半導体基板に対して反対側の表面層に選択的に形成された第2導電型の第1ベース領域と、
前記第1導電型ワイドバンドギャップ半導体層の内部に選択的に形成された第2導電型の第2ベース領域と、
前記第1導電型ワイドバンドギャップ半導体層の前記ワイドバンドギャップ半導体基板に対して反対側の表面層に選択的に形成された、前記第1導電型ワイドバンドギャップ半導体層より高不純物濃度の第1導電型の領域と、
前記第1導電型ワイドバンドギャップ半導体層の前記ワイドバンドギャップ半導体基板に対して反対側の表面に形成された、シリコンよりもバンドギャップが広い半導体からなる第2導電型ワイドバンドギャップ半導体層と、
前記第2導電型ワイドバンドギャップ半導体層の表面層に選択的に形成された第1導電型のソース領域と、
前記第2導電型ワイドバンドギャップ半導体層および前記ソース領域を貫通して前記第1導電型の領域に達するトレンチと、
前記トレンチ内部にゲート絶縁膜を介して形成されたゲート電極と、
前記第2導電型ワイドバンドギャップ半導体層および前記ソース領域に接触するソース電極と、
前記ワイドバンドギャップ半導体基板の裏面に設けられたドレイン電極と、
を備え、
前記第2ベース領域は、前記トレンチと深さ方向に対向する位置のすべてに配置され、
前記第1ベース領域の一部は、前記トレンチ側に延在し、前記第2ベース領域に接続され、
前記第1導電型の領域の下端部は、前記トレンチの底部よりも深くかつ前記第1ベース領域の下端部よりも浅い位置にあり、
前記第1ベース領域の前記ドレイン電極側の角部の曲率半径は、前記第2ベース領域の前記ドレイン電極側の角部の曲率半径より小さく、
前記第2ベース領域の下端部の深さは、前記第1ベース領域の下端部の深さと同じであることを特徴とする半導体装置。 - 前記第2ベース領域の不純物濃度は、前記第1ベース領域の不純物濃度と同じであることを特徴とする請求項1または2に記載の半導体装置。
- 前記第2ベース領域の下端部の深さは、前記第1ベース領域の下端部の深さと同じであることを特徴とする請求項1に記載の半導体装置。
- 前記第2ベース領域の幅は、前記トレンチの幅よりも広いことを特徴とする請求項2に記載の半導体装置。
- 前記トレンチは、前記第1導電型の領域を貫通して前記第2ベース領域に達することを特徴とする請求項1または2に記載の半導体装置。
- 前記第1ベース領域の一部と前記第2ベース領域との接続部分と、前記第2導電型ワイドバンドギャップ半導体層との間に、前記第1導電型の領域が延在していることを特徴とする請求項1または2に記載の半導体装置。
- 前記第1導電型の領域を挟んで、前記第1ベース領域の一部と前記第2ベース領域との接続部分を、前記第1ベース領域と前記第2ベース領域とが並ぶ方向と直交する方向に周期的に配置した平面レイアウトを有することを特徴とする請求項1または2に記載の半導体装置。
- 前記第1ベース領域の前記ドレイン電極側の端部の少なくとも一部は、前記第2ベース領域の前記ドレイン電極側の端部よりも前記ドレイン電極側に位置することを特徴とする請求項1に記載の半導体装置。
- 前記第1ベース領域の前記ドレイン電極側の端部の、前記第2ベース領域の前記ドレイン電極側の端部よりも深い部分を、前記第1ベース領域と前記第2ベース領域とが並ぶ方向と直交する方向に周期的に配置した平面レイアウトを有することを特徴とする請求項1に記載の半導体装置。
- シリコンよりもバンドギャップが広い半導体は、炭化珪素であることを特徴とする請求項1〜10のいずれか一つに記載の半導体装置。
- 前記第1ベース領域と前記第2ベース領域とが、平面視で格子状のレイアウトをしていることを特徴とする請求項1または2に記載の半導体装置。
- 前記第1ベース領域と前記第2ベース領域の接続部分以外の、前記第1ベース領域と前記第2ベース領域との間に前記第1導電型の領域が設けられていることを特徴とする請求項1または2に記載の半導体装置。
- 前記第2導電型ワイドバンドギャップ半導体層の表面層に選択的に形成された第2導電型のコンタクト領域をさらに備え、
前記第1ベース領域と前記第2ベース領域とが並ぶ方向において、前記コンタクト領域の幅は、前記第1ベース領域の幅よりも狭いことを特徴とする請求項1または2に記載の半導体装置。
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