JP2018133377A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP2018133377A JP2018133377A JP2017024491A JP2017024491A JP2018133377A JP 2018133377 A JP2018133377 A JP 2018133377A JP 2017024491 A JP2017024491 A JP 2017024491A JP 2017024491 A JP2017024491 A JP 2017024491A JP 2018133377 A JP2018133377 A JP 2018133377A
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Abstract
【解決手段】半導体装置は、半導体基板1と、第1導電型の第1半導体層2と、第2導電型の第2半導体層3と、第1導電型の第1半導体領域4と、第2導電型の第2半導体領域5と、ゲート絶縁膜6と、ゲート電極7と、を備える。前記第1半導体層または/および前記第2半導体層の前記第2半導体領域と深さ方向に対向する領域を除いた領域に、ライフタイムキラーを注入したライフタイムキラー領域10を備える。
【選択図】図1
Description
本発明にかかる半導体装置は、シリコンよりバンドギャップが広いワイドバンドギャップ半導体を用いて構成される。実施の形態においては、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いて作製された炭化珪素半導体装置について、縦型プレーナーゲート構造のMOSFETを例に説明する。図1は、実施の形態にかかる炭化珪素半導体装置の構成を示す断面図である。
次に、実施の形態にかかる炭化珪素半導体装置の製造方法について、例えば1200Vの耐圧クラスのMOSFETを作成する場合を例に説明する。図4〜7は、実施の形態にかかる炭化珪素半導体装置の製造途中の状態を示す断面図である。まず、例えば2×1019/cm3程度の不純物濃度で窒素がドーピングされたn+型炭化珪素基板1を用意する。n+型炭化珪素基板1は、主面が例えば、<11−20>方向に4度程度のオフ角を有する(000−1)面であってもよい。次に、n+型炭化珪素基板1の(000−1)面上に、1.0×1016/cm3の不純物濃度で窒素がドーピングされた厚さ10μm程度のn型炭化珪素エピタキシャル層2を成長させる。ここで、図4に示される構造となる。
2 n型炭化珪素エピタキシャル層
3 p型ベース層
3a 第1p+型ベース層
3b 第2p+型ベース層
4 n+型ソース領域
5 p+型コンタクト領域
6 ゲート絶縁膜
7 ゲート電極
8 ソース電極
9 ドレイン電極
10 ライフタイムキラー領域
11 JFET領域
18 トレンチ
Claims (10)
- 第1導電型の半導体基板と、
前記半導体基板のおもて面に設けられた、前記半導体基板より低不純物濃度の第1導電型の第1半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた第2導電型の第2半導体層と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた第1導電型の第1半導体領域と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に設けられた、前記第2半導体層より高不純物濃度の第2導電型の第2半導体領域と、
前記第2半導体層の、前記第1半導体層と前記第1半導体領域とに挟まれた領域の表面上にゲート絶縁膜を介して設けられたゲート電極と、
前記第2半導体層と前記第1半導体領域の表面に設けられた第1電極と、
前記半導体基板の裏面に設けられた第2電極と、
前記第1半導体層または/および前記第2半導体層の、前記第2半導体領域と深さ方向に対向する領域を除いた領域に選択的に設けられた、ライフタイムキラーを注入したライフタイムキラー領域と、
を備えることを特徴とする半導体装置。 - 前記第2半導体層を貫通して、前記第1半導体層に達するトレンチをさらに備え、
前記ゲート電極は、前記トレンチの内部に前記ゲート絶縁膜を介して設けられていることを特徴とする請求項1に記載の半導体装置。 - 前記ライフタイムキラー領域は、前記第1半導体層または/および前記第2半導体層の前記ゲート絶縁膜と対向する領域に設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記ライフタイムキラー領域の底面は、前記第1半導体層と前記第2半導体層との界面より前記半導体基板側にあることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。
- 前記ライフタイムキラー領域の底面は、前記半導体基板と接することを特徴とする請求項4に記載の半導体装置。
- 前記ライフタイムキラー領域の表面は、前記第1半導体層と前記第2半導体層との界面に接する、もしくはこれより前記ゲート絶縁膜側にあることを特徴とする請求項3に記載の半導体装置。
- 前記ライフタイムキラー領域の表面は、前記第1半導体層と前記ゲート絶縁膜との界面にあることを特徴とする請求項6に記載の半導体装置。
- 前記ライフタイムキラーは、ヘリウムまたはプロトンであることを特徴とする請求項1〜7のいずれか一つに記載の半導体装置。
- 第1導電型の半導体基板のおもて面に、前記半導体基板より低不純物濃度の第1導電型の第1半導体層を形成する第1工程と、
前記第1半導体層の、前記半導体基板側に対して反対側の表面層に選択的に第2導電型の第2半導体層を形成する第2工程と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に第1導電型の第1半導体領域を形成する第3工程と、
前記第2半導体層の、前記半導体基板側に対して反対側の表面層に選択的に、前記第2半導体層より高不純物濃度の第2導電型の第2半導体領域を形成する第4工程と、
前記第2半導体層の、前記第1半導体層と前記第1半導体領域とに挟まれた領域の表面上にゲート絶縁膜を介してゲート電極を形成する第5工程と、
前記第2半導体層と前記第1半導体領域の表面に第1電極を形成する第6工程と、
前記第1半導体層または/および前記第2半導体層の、前記第2半導体領域と深さ方向に対向する領域を除いた領域にライフタイムキラーを選択的に注入して、ライフタイムキラー領域を形成する第7工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第4工程より後、前記第5工程より前に、
前記第2半導体層を貫通して、前記第1半導体層に達するトレンチを形成する工程をさらに含み、
前記第5工程では、前記ゲート電極を、前記トレンチの内部に前記ゲート絶縁膜を介して形成することを特徴とする請求項9に記載の半導体装置の製造方法。
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