JP2018107168A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
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- 239000010703 silicon Substances 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
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Abstract
Description
本発明にかかる半導体装置は、ワイドバンドギャップ半導体を用いて構成される。実施の形態においては、ワイドバンドギャップ半導体として例えばSiCを用いて作製された炭化珪素半導体装置について、MOSFETを例に説明する。図1は、実施の形態1にかかる炭化珪素半導体装置の構成を示す断面図である。
次に、実施の形態1にかかる炭化珪素半導体装置の製造方法について説明する。図7〜図9は、実施の形態1にかかる炭化珪素半導体装置の製造途中の状態を模式的に示す断面図である。
図10は、実施の形態2にかかる炭化珪素半導体装置の構成を示す断面図である。図10に示すように、実施の形態2にかかる炭化珪素半導体装置は、ショットキー電極24とn型高濃度領域15との間に、トレンチ28の側壁と接するn型層(第1導電型の第2半導体層)25を設けた構造である。
次に、実施の形態2にかかる炭化珪素半導体装置の製造方法について説明する。図12〜図14は、実施の形態2にかかる炭化珪素半導体装置の製造途中の状態を模式的に示す断面図である。まず、実施の形態1と同様に、n+型炭化珪素基板2を用意し、n-型炭化珪素エピタキシャル層1をエピタキシャル成長させる工程からp+型領域3の上の部分を形成する工程を順に行う(図7、図8参照)。
図15は、実施の形態3にかかる炭化珪素半導体装置の構成を示す断面図である。図15に示すように、実施の形態3にかかる炭化珪素半導体装置は、ショットキー電極24とn型高濃度領域15との間にn型層25を設け、n型層25とトレンチ28の側壁の間にp型ベース領域16を設けた構造である。また、図16は、実施の形態3にかかる炭化珪素半導体装置の構成を示す他の断面図である。図16に示すように、p型ベース領域16は、奥行方向でp+型領域3に接続される。
次に、実施の形態3にかかる炭化珪素半導体装置の製造方法について説明する。図17は、実施の形態3にかかる炭化珪素半導体装置の製造途中の状態を示す断面図である。まず、実施の形態1と同様に、n+型炭化珪素基板2を用意し、n-型炭化珪素エピタキシャル層1をエピタキシャル成長させる工程からp+型領域3の上の部分を形成する工程を順に行う(図7、図8参照)。この後、実施の形態2と同様に、p型ベース領域16を形成する工程から、p+型コンタクト領域18を形成する工程までの工程を行う。
図18は、実施の形態4にかかる炭化珪素半導体装置の構成を示す断面図である。図18に示すように、実施の形態4にかかる炭化珪素半導体装置は、トレンチ28の底に接したp+型領域3が領域Bの下部に広がっている構造である。
次に、実施の形態4にかかる炭化珪素半導体装置の製造方法について説明する。実施の形態4にかかる炭化珪素半導体装置は、p+型領域3を形成する際のマスクを実施の形態1の製造方法より狭くすることで、実施の形態1の製造方法と同様の方法で形成される。
2 n+型炭化珪素基板
3 p+型領域
15 n型高濃度領域
16 p型ベース層
17 n+型ソース領域
18 p+型コンタクト領域
19 ゲート絶縁膜
20 ゲート電極
21 層間絶縁膜
22 ソース電極バッド
23 ソース電極
24 ショットキー電極
25 n型層
26 n+型層
28 トレンチ
Claims (14)
- 第1導電型の半導体基板と、
前記半導体基板のおもて面に設けられた、前記半導体基板より不純物濃度の低い第1導電型の第1半導体層と、
前記第1半導体層の内部に選択的に設けられた、前記第1半導体層よりも不純物濃度の高い第2導電型の第1半導体領域と、
前記第1半導体層の、前記半導体基板に対して反対側に選択的に設けられた、前記第1半導体領域よりも不純物濃度の低い第1導電型の第2半導体領域と、
前記第1半導体領域の内部に選択的に設けられた、前記第1半導体領域よりも不純物濃度の高い第1導電型の第3半導体領域と、
前記第3半導体領域および前記第2半導体領域を貫通して前記第1半導体層に達するトレンチと、
前記トレンチの内部にゲート絶縁膜を介して設けられたゲート電極と、
前記第1半導体領域および前記第3半導体領域に接する第1電極と、
前記第1半導体層に接するショットキー電極と、
を備え、
前記ショットキー電極が設けられた前記トレンチ間では、前記トレンチの側壁は、前記第1半導体層と接し、
前記第1電極が設けられた前記トレンチ間では、前記トレンチの側壁は、前記第2半導体領域および前記第3半導体領域と接し、
前記ショットキー電極の少なくとも一部の領域は、前記第1半導体領域と深さ方向に対向し、
前記トレンチは、前記第1半導体領域と深さ方向に対向することを特徴とする半導体装置。 - 前記第1半導体層の前記半導体基板に対して反対側に選択的に設けられた、前記第1半導体層より不純物濃度の高い第1導電型の第2半導体層をさらに備え、
前記ショットキー電極が設けられた前記トレンチ間では、前記トレンチの側壁は、前記第2半導体層と接し、
前記ショットキー電極は、前記第2半導体層と接することを特徴とする請求項1に記載の半導体装置。 - 前記第1半導体層と前記第2半導体層との間に、前記第2半導体層より不純物濃度の高い第1導電型の第3半導体層をさらに備え、
前記ショットキー電極が設けられた前記トレンチ間では、前記トレンチの側壁は、前記第2半導体層および前記第3半導体層と接することを特徴とする請求項2に記載の半導体装置。 - 前記ショットキー電極が設けられた前記トレンチ間では、前記トレンチの側壁は、前記第1半導体層および前記第2半導体領域と接することを特徴とする請求項1〜3のいずれか一つに半導体装置。
- 前記ショットキー電極が設けられた前記トレンチ間の第1領域と、前記第2電極が設けられた前記トレンチ間の第2領域が、単位セルとして配置されることを特徴とする請求項1〜4のいずれか一つに記載の半導体装置。
- 前記第1領域の面積は、前記第2領域の面積より大きいことを特徴とする請求項5に記載の半導体装置。
- 前記第1領域と前記第2領域は、ストライプ状に配置されていることを特徴とする請求項5または6に記載の半導体装置。
- 前記第1半導体領域は、少なくとも一部が前記トレンチに接することを特徴とする請求項1〜7のいずれか一つに記載の半導体装置。
- 前記第1半導体領域は、前記トレンチの幅方向に0.8μm〜1.2μmの距離を離して配置されることを特徴とする請求項1〜8のいずれか一つに記載の半導体装置。
- 前記第1半導体領域の前記半導体基板側の端部は、前記トレンチの底より前記半導体基板側に位置し、
前記第1半導体領域の前記第1電極側の端部は、前記第3半導体領域の表面から0.4μm〜1.9μmの距離を離して配置されることを特徴とする請求項1〜9のいずれか一つに記載の半導体装置。 - 前記トレンチは、前記トレンチの幅方向に6μm以下の距離を離して等間隔に配置されることを特徴とする請求項1〜10のいずれか一つに記載の半導体装置。
- 前記ショットキー電極と接する前記第1半導体層の表面から深さ0.1μmまでの領域の不純物濃度は、1.0×1016〜1.0×1018/cm3であることを特徴とする請求項1〜11のいずれか一つに記載の半導体装置。
- 前記ショットキー電極と前記第1電極は、同一の材料から形成されていることを特徴とする請求項1〜12のいずれか一つに記載の半導体装置。
- 第1導電型の半導体基板のおもて面に、前記半導体基板より不純物濃度の低い第1導電型の第1半導体層を形成する第1工程と、
前記第1半導体層の内部に選択的に、前記第1半導体層よりも不純物濃度の高い第2導電型の第1半導体領域を形成する第2工程と、
前記第1半導体層の、前記半導体基板に対して反対側に選択的に、前記第1半導体領域よりも不純物濃度の低い第1導電型の第2半導体領域を形成する第3工程と、
前記第1半導体領域の内部に選択的に、前記第1半導体領域よりも不純物濃度の高い第1導電型の第3半導体領域を形成する第4工程と、
前記第3半導体領域および前記第2半導体領域を貫通して前記第1半導体層に達するトレンチを形成する第5工程と、
前記トレンチの内部にゲート絶縁膜を介してゲート電極を形成する第6工程と、
前記第1半導体領域および前記第3半導体領域に接する第1電極を形成する第7工程と、
前記第1半導体層に接するショットキー電極を形成する第8工程と、
を含み、
前記第5工程において、前記ショットキー電極が形成される前記トレンチ間では、前記トレンチの側壁を、前記第1半導体層に接し、前記第1電極が形成される前記トレンチ間では、前記トレンチの側壁を、前記第2半導体領域および前記第3半導体領域に接し、前記トレンチを、前記第1半導体領域と深さ方向に対向するように形成し、
前記第8工程において、前記ショットキー電極の少なくとも一部の領域を、前記第1半導体領域と深さ方向に対向するように形成することを特徴とする半導体装置の製造方法。
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