WO2012105609A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2012105609A1 WO2012105609A1 PCT/JP2012/052285 JP2012052285W WO2012105609A1 WO 2012105609 A1 WO2012105609 A1 WO 2012105609A1 JP 2012052285 W JP2012052285 W JP 2012052285W WO 2012105609 A1 WO2012105609 A1 WO 2012105609A1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
Definitions
- the present invention relates to a semiconductor device.
- SiC silicon carbide: silicon carbide
- the SiC power device is used as a switching element of various inverter circuits incorporated in, for example, a motor control system, a power conversion system, or the like.
- the SiC power device switching element
- the current flowing through the motor coil is cut off
- the back electromotive force generated in the motor coil is consumed by the diode due to electromagnetic induction of the motor coil.
- the current caused by the back electromotive force is caused to flow as a return current to the motor coil by the rectification action of the parasitic diode (body diode) by the pn junction between the p-type channel region and the n-type drain region inherent in the device.
- high back electromotive force is prevented from being applied to the switching element.
- a trench reaching the n-type drain region from the n-type source region through the p-type channel region is formed at a position different from the gate trench, and the n-type exposed in the trench.
- a countermeasure for Schottky junction of the source electrode to the drain region can be considered. According to this measure, when a back electromotive force is generated, a current can be preferentially passed through the Schottky junction, and the current flowing through the pn channel diode may be reduced or eliminated.
- An object of the present invention is to provide a semiconductor device capable of suppressing an increase in on-resistance and further improving a breakdown voltage.
- a semiconductor device is a semiconductor device having a semiconductor layer made of a wide bandgap semiconductor, and the semiconductor layer is exposed on the surface side of the semiconductor layer.
- a first conductivity type source region formed on the semiconductor layer, a second conductivity type channel region formed on and in contact with the source region on the back side of the semiconductor layer, and the channel region.
- a drain region of a first conductivity type formed on the back side of the semiconductor layer so as to be in contact with the channel region, and penetrating from the surface of the semiconductor layer to the source region and the channel region into the drain region.
- a source trench having a side surface and a bottom surface, a gate insulating film formed to be in contact with the channel region, and a front through the gate insulating film A gate electrode opposed to the channel region; and a second conductivity type first breakdown voltage holding region selectively formed on the side surface or the bottom surface of the source trench, and is joined to the drain region in the source trench.
- a barrier forming layer for forming a junction barrier lower than a diffusion potential of a body diode formed by a pn junction between the channel region and the drain region by the junction with the drain region.
- a semiconductor device employing this wide band gap semiconductor (for example, a band gap Eg of 2 eV or more, preferably 2.5 eV to 7 eV) is used as a switching element, for example.
- the current flowing through the load is turned on / off by turning on / off the gate voltage in a state where a positive voltage on the drain region side is applied between the source region and the drain region.
- the load When the load is inductive, when the current flowing through the load is cut off (that is, when the gate voltage is turned off), a back electromotive force is generated in the load. Due to the counter electromotive force, a voltage that is positive on the source region side may be applied between the source region and the drain region. In such a case, current flows preferentially at the junction between the barrier forming layer and the drain region, and the current flowing through the body diode can be reduced or eliminated. The current flowing through the semiconductor device in this way can be supplied to the load as a return current, for example.
- the off-state current passes through the barrier forming layer, there is almost no carrier movement between the channel region and the drain region. Therefore, recombination of holes and electrons in the drain region can be suppressed or prevented. As a result, expansion of crystal defects in the wide band gap semiconductor can be suppressed, so that an increase in on-resistance of the transistor can be suppressed.
- the first breakdown voltage holding region is selectively formed in the drain region on the side surface or the bottom surface of the source trench.
- the body diode formed by the junction (pn junction) between the first breakdown voltage holding region and the drain region can be formed on the back surface side of the semiconductor layer with respect to the junction between the barrier forming layer and the drain region. . Therefore, a depletion layer generated in the body diode can be generated in the vicinity of the source trench. Due to the presence of the depletion layer, a high potential equipotential surface with respect to the gate electrode can be kept away from the gate insulating film. As a result, the electric field applied to the gate insulating film can be reduced, so that dielectric breakdown can be suppressed.
- the barrier forming layer forms a junction barrier lower than the diffusion potential of the body diode with the drain region by forming a heterojunction or a Schottky junction with the drain region made of a wide band gap semiconductor. It may be.
- the barrier forming layer is preferably made of Poly-Si.
- the barrier forming layer is made of a group consisting of Ni, Ti, Al, and Mo. It is preferable that it consists of 1 type selected from.
- the semiconductor layer includes a lattice-shaped gate trench having a side surface and a bottom surface, penetrating the source region and the channel region from the surface of the semiconductor layer to the drain region, and the lattice-shaped gate trench.
- a plurality of polygonal columnar unit cells having a plurality of corners, each unit cell including the source region, the channel region, and the drain region; and the gate insulating film is formed of the gate trench.
- the gate electrode is embedded in the gate trench so as to face the channel region through the gate insulating film, and the first breakdown voltage holding region is , In a part of the source trench so that the drain region is exposed on the bottom surface of the source trench.
- the side surface and the bottom surface are selectively formed at an edge portion of the source trench, and the barrier forming layer is joined to the drain region exposed at the bottom surface of the source trench. .
- the present inventors diligently studied the mechanism of dielectric breakdown of the gate insulating film at the time of turn-off in the trench gate type MIS transistor. Specifically, when the semiconductor device is off (that is, the gate voltage is 0 V), the drain region is on the (+) side between the source region and the drain region functioning as the drain (between the source and the drain). Is applied, an electric field is applied to the gate insulating film interposed between the gate electrode and the drain region. This electric field is generated due to a potential difference between the gate electrode and the drain region.
- the barrier forming layer is joined to the drain region at the bottom surface of the source trench.
- a body diode can be formed in the vicinity of the edge portion of the source trench by forming the first breakdown voltage holding region at the edge portion of the source trench.
- the depletion layer generated in the body diode can be expanded between the gate trench and the source trench, so that the equipotential surface between the gate trench and the source trench can be prevented from being concentrated.
- the electric field applied to the bottom of the gate trench can be reduced, and the electric field applied to the gate insulating film can be reduced. Therefore, the gate insulating film can be prevented from being broken.
- the semiconductor layer may further include a second conductivity type second breakdown voltage holding region selectively formed at a corner edge portion of the gate trench formed at the corner portion of the unit cell.
- a second conductivity type second breakdown voltage holding region selectively formed at a corner edge portion of the gate trench formed at the corner portion of the unit cell.
- the second breakdown voltage holding region When the second breakdown voltage holding region is formed at the corner edge portion of the gate trench, the second breakdown voltage holding region may be formed so as to reach a portion immediately above the corner edge portion in the channel region.
- a channel is formed along the side surface of the unit cell that forms a part of the side surface of the gate trench by controlling the voltage applied to the gate electrode. That is, a channel is not formed at the corner of the unit cell, or even if it is formed, a small amount of current flows through the channel. Therefore, by forming the second breakdown voltage holding region so as to reach the portion immediately above the corner edge portion in the channel region, the effect of preventing the breakdown of the gate insulating film can be further improved without substantially affecting the performance of the device. it can.
- the second breakdown voltage holding region When the second breakdown voltage holding region is formed at the corner edge portion of the gate trench, the second breakdown voltage holding region may be selectively formed at the intersection of the lattice-shaped gate trench.
- the semiconductor layer may further include a second breakdown voltage holding region of a second conductivity type formed on the bottom surface of the linear portion of the lattice-shaped gate trench and having a width narrower than the width of the linear portion. preferable.
- the electric field generated along the linear portion of the gate trench acts on the gate insulating film, the electric field is relaxed by the depletion layer generated by the junction (pn junction) between the third breakdown voltage holding region and the drain region. can do. As a result, the electric field generated in the gate insulating film can be alleviated evenly.
- the third breakdown voltage holding region is not formed on the side surface of the linear portion of the gate trench (that is, the portion where the channel is formed in the unit cell), it is possible to prevent the device performance from being deteriorated.
- the impurity concentration in the third breakdown voltage holding region is preferably higher than the impurity concentration in the second breakdown voltage holding region. Moreover, it is preferable that the thickness of the third breakdown voltage holding region is smaller than the thickness of the second breakdown voltage holding region. With this configuration, an increase in channel resistance can be suppressed.
- the thicknesses of the second and third breakdown voltage holding regions are, for example, thicknesses along the direction from the front surface to the back surface side of the semiconductor layer.
- the semiconductor device may include a planar gate type MIS transistor. That is, in the semiconductor device according to one aspect of the present invention, the channel region is formed to be exposed on the surface of the semiconductor layer in a polygonal shape in plan view having a plurality of corners, and the channel region is The channel regions are arranged in a matrix, the source regions are formed in a well shape so as to be exposed on the surface of each channel region, and the gate insulating film is exposed on the surface of the semiconductor layer
- the first breakdown voltage holding region is formed above, and the side surface and the bottom surface intersect each other in a partial region of the source trench so that the drain region is exposed to the bottom surface of the source trench.
- the barrier forming layer is selectively formed at an edge portion of the source trench, and the barrier forming layer is formed on the drain region exposed on the bottom surface of the source trench. It may be engaged.
- the semiconductor layer may include a second conductive layer selectively formed at an inter-channel region extending between adjacent channel regions and a corner portion of the inter-channel region formed at the corner portion of the channel region. It is preferable to further include a fourth breakdown voltage holding region of the mold.
- the dielectric breakdown of the gate insulating film is particularly likely to occur near the corner of the interchannel region. Therefore, if the fourth breakdown voltage holding region is formed in the corner portion of the inter-channel region, the dielectric breakdown of the gate insulating film in the vicinity of the corner portion can be effectively suppressed.
- a channel is formed along each side of the channel region by controlling the voltage applied to the gate electrode. That is, a channel is not formed at the corner of the channel region, or even if it is formed, a small amount of current flows through the channel. Therefore, by forming the fourth breakdown voltage holding region at the corner in the inter-channel region, the effect of preventing the gate insulating film from being destroyed can be further improved without substantially affecting the performance of the device.
- the semiconductor layer preferably further includes a second conductivity type fifth breakdown voltage holding region formed in a linear portion of the inter-channel region and having a width narrower than the width of the linear portion.
- the drain region preferably has a step portion formed by selectively projecting the bottom surface of the source trench to the surface side of the semiconductor layer.
- a semiconductor device includes a semiconductor layer made of a wide band gap semiconductor, and a gate portion that is formed in the semiconductor layer and partitions the semiconductor layer into a plurality of cells.
- a first MIS transistor structure in which a first source trench is formed, the deepest part reaching the drain region through the source region and the channel region from the surface; and a first MIS transistor structure selectively formed on an inner surface of the first source trench.
- a semiconductor device employing this wide band gap semiconductor (for example, a band gap Eg of 2 eV or more, preferably 2.5 eV to 7 eV) is used as a switching element, for example.
- the current flowing through the load is turned on / off by turning on / off the gate voltage in a state where a positive voltage on the drain region side is applied between the source region and the drain region.
- the off-state current passes through the Schottky barrier diode of the Schottky cell, there is almost no carrier movement between the channel region and the drain region. Therefore, recombination of holes and electrons in the drain region can be suppressed or prevented. As a result, expansion of crystal defects in the wide band gap semiconductor can be suppressed, so that an increase in on-resistance of the transistor can be suppressed.
- the current flowing through the body diode can be reduced or eliminated, loss when the semiconductor device operates can be reduced.
- the first breakdown voltage holding region is selectively formed on the inner surface of the first source trench.
- a body diode formed by a junction (pn junction) between the first breakdown voltage holding region and the drain region can be formed. Therefore, a depletion layer generated in the body diode can be generated in the vicinity of the first source trench. Due to the presence of this depletion layer, a high potential equipotential surface can be kept away from the gate portion. As a result, dielectric breakdown in the gate portion can be prevented.
- the source electrode is formed between the Schottky region and the Schottky region by forming a heterojunction or a Schottky junction with the Schottky region made of a wide band gap semiconductor. May have a barrier forming layer for forming a junction barrier lower than the diffusion potential of the body diode. That is, in the semiconductor device according to another aspect of the present invention, the source electrode is a metal electrode that forms a Schottky barrier by forming a Schottky barrier between the source electrode and a band different from the band gap of the semiconductor layer.
- any of the semiconductor electrodes which are made of a heterogeneous semiconductor having a gap, and which form a heterojunction diode by heterojunction with the Schottky region (junction forming a potential barrier with the Schottky region using a band gap difference) It is a concept that also includes The Schottky region is a concept that includes a region where a heterojunction is formed with the source electrode.
- the barrier forming layer when forming a heterojunction, is preferably made of polysilicon.
- the barrier forming layer when forming a Schottky junction, is made of Ni, Ti, Al, and Mo. It is preferable to consist of one selected.
- the first breakdown voltage holding region extends from the bottom surface of the first source trench to the channel region along the side surface of the source trench.
- the pn diode cell further includes a second conductivity type channel contact region formed on the bottom surface of the first source trench and having a higher impurity concentration than the first breakdown voltage holding region.
- the first source trench includes a first upper layer trench having a depth from the surface of the semiconductor layer to the channel region, and the first source trench.
- the pn diode cell has a two-stage structure including a first lower trench having a width narrower than that of the upper trench and having a depth from the channel region to the drain region, and the pn diode cell includes the first upper trench and the first trench.
- the semiconductor device further includes a channel contact region of a second conductivity type formed in the channel region exposed at a step portion with respect to the first lower trench and having a higher impurity concentration than the channel region.
- the Schottky cell includes a first conductivity type source region and a second conductivity type arranged in this order from the front surface side to the back surface side of the semiconductor layer.
- a second MIS transistor structure having a channel region and a drain region of the first conductivity type, and a second source trench formed from the surface of the semiconductor layer to the drain region through the source region and the channel region;
- a second breakdown voltage holding region selectively formed at an edge portion of the second source trench formed by intersecting a side surface and a bottom surface of the second source trench, and the Schottky region includes the second source trench.
- it is formed on the bottom surface of the second source trench surrounded by the two breakdown voltage holding regions.
- a body diode formed by the junction (pn junction) between the second breakdown voltage holding region and the drain region can be formed. Therefore, a depletion layer generated in the body diode can be generated in the vicinity of the second source trench. Due to the presence of this depletion layer, a high potential equipotential surface can be kept away from the gate portion. As a result, dielectric breakdown in the gate portion can be prevented.
- the Schottky region is formed with an area where a depletion layer generated from a junction between the Schottky region and the second breakdown voltage holding region is not connected.
- the area of the Schottky cell is preferably larger than the area of the pn diode cell.
- the second source trench in the Schottky cell includes a second upper layer trench having a depth from the surface of the semiconductor layer to the channel region, and the second source trench. It has a two-stage structure including a second lower trench having a width narrower than that of the upper trench and a depth from the channel region to the drain region, and the second breakdown voltage holding region is formed of the second lower trench.
- the Schottky cell is formed in the channel region exposed at a step portion between the second upper layer trench and the second lower layer trench, and is formed so as to reach the channel region along a side surface. It is preferable to further include a second conductivity type channel contact region having a higher impurity concentration.
- the gate portion includes a gate trench formed in the semiconductor layer, a gate insulating film formed on an inner surface of the gate trench, and the gate in the gate trench.
- a gate electrode formed on the inside of the insulating film may be included, or a gate insulating film formed on the semiconductor layer and a gate electrode formed on the gate insulating film may be included.
- the semiconductor device When the gate trench is formed in a lattice shape, the semiconductor device is formed so as to straddle the pn diode cell and the Schottky cell via the intersection of the gate trench, and the first breakdown voltage holding region It is preferable to further include a second conductivity type relay region that is electrically connected to the second breakdown voltage holding region. According to this configuration, contact can be made with the channel region of the Schottky cell via the relay region.
- the Schottky cell is preferably surrounded by the pn diode cell.
- the Schottky cell corresponds to four or nine pn diode cells. It is preferable that it has the area to do.
- the Schottky cell and the pn diode cell may include a quadrangular cell formed in a square shape, or a hexagonal cell formed in a hexagonal shape. May be included, or stripe cells formed in a stripe shape may be included.
- FIG. 1A and 1B are schematic plan views of a trench gate type MIS transistor according to a first embodiment of the present invention.
- FIG. 1A is an overall view, and FIG. Each enlarged view is shown.
- FIG. 2 is a cross-sectional view of the trench gate type MIS transistor shown in FIGS. 1 (a) and 1 (b), and shows cross sections along the cutting lines AA and BB in FIG. 1 (b), respectively.
- 3A is a schematic cross-sectional view showing a part of the manufacturing process of the trench gate type MIS transistor shown in FIG. 2, and shows a cut surface at the same position as FIG.
- FIG. 3B is a diagram showing a step subsequent to FIG. 3A.
- FIG. 3C is a diagram showing a step subsequent to FIG. 3B.
- FIG. 3D is a diagram showing a step subsequent to FIG. 3C.
- FIG. 3E is a diagram showing a step subsequent to that in FIG. 3D.
- FIG. 3F is a diagram showing a step subsequent to that in FIG. 3E.
- FIG. 4 is a schematic cross-sectional view showing a modification of the trench gate type MIS transistor shown in FIG. 5A and 5B are schematic plan views of a planar gate type MIS transistor according to a second embodiment of the present invention.
- FIG. 5A is an overall view
- FIG. 5B is an internal view. Each enlarged view is shown.
- FIG. 6 is a cross-sectional view of the planar gate type MIS transistor shown in FIGS. 5A and 5B, and shows cross sections taken along section lines CC and DD in FIG.
- FIG. 7A is a schematic cross-sectional view showing a part of the manufacturing process of the planar gate type MIS transistor shown in FIG. 6, and shows a cut surface at the same position as FIG.
- FIG. 7B is a diagram showing a step subsequent to FIG. 7A.
- FIG. 7C is a diagram showing a step subsequent to FIG. 7B.
- FIG. 7D is a diagram showing a step subsequent to FIG. 7C.
- FIG. 7E is a diagram showing a step subsequent to FIG. 7D.
- FIG. 7F is a diagram showing a step subsequent to that in FIG. 7E.
- FIG. 8 is a schematic cross-sectional view showing a modification of the planar gate type MIS transistor shown in FIG. FIGS.
- FIG. 9A and 9B are schematic plan views of a trench gate type MIS transistor according to a third embodiment of the present invention.
- FIG. 9A is an overall view
- FIG. 9B is an internal view. Each enlarged view is shown.
- FIG. 10 is a cross-sectional view of the trench gate type MIS transistor of FIGS. 9A and 9B, and shows cut planes taken along cutting lines EE, FF, and GG of FIG. 9B, respectively.
- FIG. 11A is a schematic cross-sectional view showing a part of the manufacturing process of the trench gate type MIS transistor of FIG. 10, and shows a cut surface at the same position as FIG.
- FIG. 11B is a diagram showing a step subsequent to FIG. 11A.
- FIG. 11C is a diagram showing a step subsequent to FIG. 11B.
- FIG. 11D is a diagram showing a step subsequent to that in FIG. 11C.
- FIG. 11E is a diagram showing a step subsequent to FIG. 11D.
- FIG. 11F is a diagram showing a step subsequent to that in FIG. 11E.
- 12 is a schematic cross-sectional view of a trench gate type MIS transistor according to a fourth embodiment of the present invention, and shows a cut surface at the same position as FIG.
- FIG. 13A is a schematic cross-sectional view showing a part of the manufacturing process of the trench gate type MIS transistor of FIG. 12, and shows a cut surface at the same position as FIG.
- FIG. 13B is a diagram showing a step subsequent to FIG. 13A.
- FIG. 13A is a schematic cross-sectional view showing a part of the manufacturing process of the trench gate type MIS transistor of FIG. 12, and shows a cut surface at the same position as FIG.
- FIG. 13B
- FIG. 13C is a diagram showing a step subsequent to FIG. 13B.
- FIG. 13D is a diagram showing a step subsequent to FIG. 13C.
- FIG. 13E is a diagram showing a step subsequent to that in FIG. 13D.
- FIG. 13F is a diagram showing a step subsequent to that in FIG. 13E.
- FIG. 13G is a diagram showing a step subsequent to that in FIG. 13F.
- 14A and 14B are schematic plan views of a planar gate type MIS transistor according to a third embodiment of the present invention.
- FIG. 14A is an overall view
- FIG. 14B is an internal view. Each enlarged view is shown.
- FIG. 15 is a cross-sectional view of the planar gate type MIS transistor of FIGS.
- FIG. 14A and 14B shows cross sections taken along the cutting lines HH and II of FIG. 14B, respectively.
- 16 (a) and 16 (b) are schematic plan views of a trench gate type MIS transistor according to a fourth embodiment of the present invention.
- FIG. 16 (a) is an overall view
- FIG. 16 (b) is an internal view. Each enlarged view is shown.
- FIG. 17 is a cross-sectional view of the trench gate type MIS transistor shown in FIGS. 16A and 16B, and shows cross sections taken along section lines JJ and KK in FIG. 16B, respectively.
- 18 (a) and 18 (b) are diagrams showing a modification of the layout of the MIS transistor in FIGS. 9 (a) and 9 (b).
- FIG. 18 (a) is an overall view
- FIG. 18 (b) is an internal enlarged view. Each figure is shown.
- FIGS. 1 (a) and 1 (b) are schematic plan views of a trench gate type MIS transistor according to a first embodiment of the present invention.
- FIG. 1A is an overall view, and FIG. Each enlarged view is shown.
- FIG. 2 is a cross-sectional view of the trench gate type MIS transistor shown in FIGS. 1 (a) and 1 (b), and shows cross sections along the cutting lines AA and BB in FIG. 1 (b), respectively.
- the MIS transistor 1 is a trench gate type DMISFET (Double-diffused Metal-Insulator-Semiconductor-Field-Effect-Transistor) employing SiC, and has, for example, a square chip shape in plan view as shown in FIG.
- the chip-like MIS transistor 1 has a length of about several millimeters in the vertical and horizontal directions on the paper surface of FIG.
- a source pad 2 is formed on the surface of the MIS transistor 1.
- the source pad 2 has a substantially square shape in plan view with four corners curved outward, and is formed to cover almost the entire surface of the MIS transistor 1.
- the source pad 2 has a removal region 3 near the center of one side.
- the removal region 3 is a region where the source pad 2 is not formed.
- the MIS transistor 1 includes a substrate 5 made of SiC of n + type (for example, the concentration is 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 ).
- the substrate 5 functions as the drain of the MIS transistor 1, and its front surface 6 (upper surface) is a Si surface and its rear surface 7 (lower surface) is a C surface.
- an epitaxial layer 8 made of SiC having n ⁇ type (for example, concentration of 1 ⁇ 10 15 to 1 ⁇ 10 17 cm ⁇ 3 ) having a lower concentration than that of the substrate 5 is laminated.
- the thickness of the epitaxial layer 8 as a semiconductor layer is, for example, 1 ⁇ m to 100 ⁇ m.
- the epitaxial layer 8 is formed on the substrate 5 by so-called epitaxial growth.
- the epitaxial layer 8 formed on the surface 6 that is the Si surface is grown with the Si surface as the main growth surface. Therefore, the surface 9 of the epitaxial layer 8 formed by growth is a Si surface, like the surface 6 of the substrate 5.
- the MIS transistor 1 has an active region 10 that functions as the MIS transistor 1 and is disposed in the center of the epitaxial layer 8 in plan view, and a transistor peripheral region 11 that surrounds the active region 10. Is formed.
- the p-type (for example, the concentration is 1.0 ⁇ 10 16 cm ⁇ 3 to 1.0 ⁇ 10 19 cm ⁇ 3 ) channel region 12 is formed in the row direction and on the surface layer portion of the epitaxial layer 8. A large number are arranged in a matrix (matrix) at a constant pitch in the column direction.
- Each channel region 12 has a square shape in plan view. For example, the length in the vertical and horizontal directions on the paper surface of FIG. 1B is about 7.2 ⁇ m.
- the region on the substrate 5 side with respect to the channel region 12 in the epitaxial layer 8 is an n ⁇ -type drain region 13 that is maintained as it is after the epitaxial growth.
- an n + -type (for example, concentration of 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 ) source region 14 is formed in almost the entire region on the surface 9 side.
- Gate trenches 15 are formed in a lattice shape so as to surround each channel region 12 from the surface 9 of the epitaxial layer 8 through each source region 14 and channel region 12 to the drain region 13.
- the gate trench 15 includes a linear portion 16 extending linearly in each of the row direction and the column direction along the four side surfaces of each channel region 12 between the adjacent channel regions 12 and the row trenches 15.
- intersect are included.
- the intersecting portion 17 is surrounded by the corners inside the four arranged channel regions 12 and is defined by the extended lines of the four sides of the channel region 12. This is a square portion in plan view.
- the gate trench 15 has a U-shaped cross section in which a side surface 18 and a bottom surface 19 facing each other are continuous via a curved surface.
- a large number of rectangular parallelepiped unit cells 21 having four corners 20 are formed in each window portion surrounded by the lattice-like gate trench 15.
- the depth direction of the gate trench 15 is the gate length direction
- the circumferential direction of each unit cell 21 orthogonal to the gate length direction is the gate width direction.
- a gate insulating film 22 made of SiO 2 is formed on the inner surface of the gate trench 15 so as to cover the entire area.
- the gate electrode 23 is embedded in the gate trench 15 by filling the inside of the gate insulating film 22 with a polysilicon material doped with n-type impurities at a high concentration.
- a vertical MIS transistor structure is configured in which the source region 14 and the drain region 13 are spaced apart from each other via the channel region 12 in the vertical direction perpendicular to the surface 9 of the epitaxial layer 8.
- a source trench 24 having a square shape in plan view that reaches the drain region 13 from the surface 9 of the epitaxial layer 8 through the source region 14 and the channel region 12 is formed.
- the depth of the source trench 24 is the same as that of the gate trench 15 in the first embodiment.
- the source trench 24 also has a U-shaped cross section in which a side surface 25 and a bottom surface 26 facing each other are continuous via a curved surface.
- the epitaxial layer 8 is formed with a p-type gate breakdown voltage holding region 27 and a source breakdown voltage holding region 28 as a first breakdown voltage holding region, which are formed by implanting p-type impurities into the epitaxial layer 8. Yes.
- the gate breakdown voltage holding region 27 is formed along the lattice-shaped gate trench 15, and a first region 29 as a second breakdown voltage holding region formed at the intersection 17 of the gate trench 15 and the line of the gate trench 15. It integrally includes a second region 30 as a third breakdown voltage holding region formed in the shape portion 16.
- the first region 29 includes a bottom edge 19 of the gate trench 15 at the intersection 17 and a corner edge portion 31 of the gate trench 15 formed below each corner 20 of the four unit cells 21 facing the intersection 17 from the bottom 19. And the channel region 12 immediately above the corner edge 31 is formed. That is, the first region 29 is formed in a square shape slightly larger than the intersecting portion 17 of the gate trench 15 in plan view, and each corner of each of the four unit cells 21 facing the intersecting portion 17 is formed. It has entered each part 20.
- the concentration of the first region 29 is higher than the concentration of the channel region 12 and higher than the concentration of the drain region 13, for example, 1 ⁇ 10 17 to 9 ⁇ 10 19 cm ⁇ 3 . Further, the thickness T 1 along the direction from the bottom surface of the gate trench 15 to the substrate 5 in the first region 29 is, for example, about 0.8 ⁇ m.
- the second region 30 is formed in a straight line having a constant width that connects the centers of the sides of the intersecting portions 17 that are adjacent to each other in plan view.
- the width of the second region 30 is higher than that of the channel region 12 and higher than that of the first region 29.
- the second thickness T 2 along the direction from the bottom of the gate trench 15 to the substrate 5 in the second region 30, the thickness of the first region 29 T 1 (Ie, T 1 > T 2 ), for example, about 0.7 ⁇ m.
- the source breakdown voltage holding region 28 has an edge portion 32 of the source trench 24 where the bottom surface 26 and the side surface 25 intersect so that the bottom surface 26 of the source trench 24 is exposed, and a part of the side surface 25 of the source trench 24 from the edge portion 32.
- the channel region 12 is formed so as to reach the channel region 12.
- a drain exposed region 33 having a square shape in plan view and formed of a part of the drain region 13 is formed at the center of the bottom surface 26 of the source trench 24.
- the concentration of the source breakdown voltage holding region 28 is the same as that of the first region 29 of the gate breakdown voltage holding region 27 (for example, 1 ⁇ 10 17 to 9 ⁇ 10 19 cm ⁇ 3 .
- the thickness T 3 along the direction from the bottom surface of the trench 24 toward the substrate 5 is the same as the thickness T 1 of the first region 29 of the gate breakdown voltage holding region 27 (for example, about 0.8 ⁇ m).
- the p-type guard ring 34 is spaced from the active region 10 so as to surround the unit cells 21 (active region 10) arranged in a matrix on the surface layer portion of the epitaxial layer 8. Are formed (four in the first embodiment). These guard rings 34 can be formed by the same ion implantation step as the step of forming the p-type channel region 12.
- Each guard ring 34 is formed in a square shape in plan view along the outer periphery of the MIS transistor 1 in plan view.
- An interlayer insulating film 35 made of SiO 2 is laminated on the epitaxial layer 8 so as to cover the gate electrode 23.
- a contact hole 36 having a diameter larger than that of the source trench 24 is formed in the interlayer insulating film 35 and the gate insulating film 22.
- a source electrode 37 is formed on the interlayer insulating film 35.
- the source electrode 37 collectively enters the source trenches 24 of all the unit cells 21 through the contact holes 36.
- the drain exposed region 33, the source It is in contact with the breakdown voltage holding region 28, the channel region 12, and the source region 14. That is, the source electrode 37 is a common wiring for all the unit cells 21.
- An interlayer insulating film (not shown) is formed on the source electrode 37, and the source electrode 37 is connected to the source pad 2 (see FIG. 1A) via the interlayer insulating film (not shown). ) Is electrically connected.
- the gate pad 4 (see FIG. 1A) is electrically connected to the gate electrode 23 through a gate wiring (not shown) routed on the interlayer insulating film (not shown). ing.
- the source electrode 37 has a polysilicon layer 38 as a barrier forming layer, an intermediate layer 39 and a metal layer 40 in order from the contact side with the epitaxial layer 8.
- the polysilicon layer 38 is a doped layer formed using doped polysilicon doped with impurities, and is, for example, 1 ⁇ 10 15 cm ⁇ 3 or more, preferably 1 ⁇ 10 19 to 1 ⁇ 10 21 cm. This is a heavily doped layer doped with impurities at a high concentration of ⁇ 3 .
- Impurities when forming the polysilicon layer 38 as a doped layer include n-type impurities such as N (nitrogen), P (phosphorus), As (arsenic), Al (aluminum), B A p-type impurity such as (boron) can be used.
- the thickness of the polysilicon layer 38 is, for example, 5000 to 10,000 mm.
- the polysilicon layer 38 is formed so as to cover the entire surface of the unit cell 21 exposed in the contact hole 36, and the drain exposed region 33 and the source breakdown voltage holding region are formed in the source trench 24. 28 and all of the source region 14 are in contact. That is, the polysilicon layer 38 is in contact with the source breakdown voltage holding region 28 on the side surface 25 of the source trench 24, and the first portion 41 in contact with the source region 14 on the side surface 25 and the peripheral portion of the source trench 24 on the surface 9 of the epitaxial layer 8. And a second portion 42 in contact with the drain exposed region 33 on the bottom surface 26 of the source trench 24.
- the first portion 41 forms an ohmic junction between both the source breakdown voltage holding region 28 and the source region 14.
- a diffusion potential for example, a pn diode formed by a junction between the channel region 12 and the drain region 13
- Heterojunction for example, the height of the junction barrier is 1 eV to 1.5 eV
- a junction barrier smaller than 2.8 eV to 3.2 eV
- the intermediate layer 39 is a metal layer laminated on the polysilicon layer 38, and is composed of a single layer containing Ti (titanium) or a plurality of layers including a layer containing Ti.
- the layer containing Ti can be formed using Ti, TiN (titanium nitride), or the like.
- the thickness of the intermediate layer 39 is, for example, 200 nm to 500 nm.
- the metal layer 40 is laminated on the intermediate layer 39 and contains, for example, Al (aluminum), Au (gold), Ag (silver), Cu (copper), Mo (molybdenum), alloys thereof, and the like. It can be formed using a metal material.
- the metal layer 40 is the outermost layer of the source electrode 37.
- the thickness of the metal layer 40 is, for example, 1 ⁇ m to 5 ⁇ m.
- the metal layer 40 has a Mo layer. Since Mo has a high melting point, if the Mo layer is included in the metal layer 40, the metal layer 40 can be prevented from being melted by heat generated when a large current flows through the source electrode 37.
- a drain electrode 44 is formed on the back surface 7 of the substrate 5 so as to cover the entire area.
- the drain electrode 44 is a common electrode for all the unit cells 21.
- As the drain electrode 44 for example, a stacked structure (Ti / Ni / Au / Ag) in which Ti, Ni, Au, and Ag are stacked in order from the substrate 5 side can be applied.
- 3A to 3F are schematic cross-sectional views showing a part of the manufacturing process of the trench gate type MIS transistor shown in FIG. 2, and show a cut surface at the same position as FIG.
- an n-type impurity for example, N () is formed on the surface 6 (Si surface) of the substrate 5 by an epitaxial growth method such as CVD, LPE, or MBE. SiC crystal is grown while doping nitrogen), P (phosphorus), As (arsenic) and the like.
- n - -type epitaxial layer 8 is formed on the substrate 5.
- p-type impurities for example, Al (aluminum), B (boron), etc.
- n-type impurities are implanted into the epitaxial layer 8 from the surface 9 of the epitaxial layer 8.
- the epitaxial layer 8 is heat-treated at 1400 ° C. to 2000 ° C., for example.
- ions of the p-type impurity and the n-type impurity implanted into the surface layer portion of the epitaxial layer 8 are activated, and the channel region 12, the source region 14, and the guard ring 34 are simultaneously formed according to the implanted locations.
- a drain region 13 that maintains the state after epitaxial growth is formed in the base layer portion of the epitaxial layer 8.
- the epitaxial layer 8 is etched using a mask having openings in regions where the gate trench 15 and the source trench 24 are to be formed. Thereby, the epitaxial layer 8 is dry-etched from the surface 9 (Si surface), and the gate trench 15 and the source trench 24 are formed simultaneously. At the same time, a large number of unit cells 21 are formed in the epitaxial layer 8.
- the etching gas includes, for example, a mixed gas (SF 6 / O 2 gas) containing SF 6 (sulfur hexafluoride) and O 2 (oxygen), SF 6 , O 2, and HBr (hydrogen bromide).
- a mixed gas (SF 6 / O 2 / HBr gas) can be used.
- a first resist 45 having an opening exposing the intersection 17 of the gate trench 15 and the edge 32 of the source trench 24 is formed on the epitaxial layer 8.
- the linear portion 16 of the gate trench 15 and the central portion of the bottom surface 26 of the source trench 24 are covered with the first resist 45.
- p-type impurities are implanted (implanted) toward the intersection 17 and the source trench 24 of the gate trench 15 exposed from the opening of the first resist 45.
- the p-type impurity is also implanted into the side faces 18 and 25. It becomes.
- the linear portion 16 of the gate trench 15 and the central portion of the bottom surface 26 of the source trench 24 are protected by the first resist 45, so that p-type impurities are added to these portions. Injection can be prevented.
- the epitaxial layer 8 is heat-treated at 1400 ° C. to 2000 ° C., for example.
- the ions of the p-type impurity implanted into the drain region 13 are activated, and the first region 29 of the gate breakdown voltage holding region 27 and the source breakdown voltage holding region 28 are formed simultaneously.
- the drain exposed region 33 is formed in the portion of the bottom surface 26 of the source trench 24 that is covered with the first resist 45.
- a second resist 46 having an opening in a region where the second region 30 of the gate breakdown voltage holding region 27 is to be formed is formed on the epitaxial layer 8.
- the side surface 18 and the bottom surface 19 of the intersection 17 of the gate trench 15 and the side surface 25 and the bottom surface 26 of the source trench 24 are covered with the second resist 46.
- p-type impurities are implanted (implanted) toward the linear portion 16 of the gate trench 15 exposed from the opening of the second resist 46.
- the side surface 18 and the bottom surface 19, and the side surface 25 and the bottom surface 26 are protected by the second resist 46, so that p-type impurity implantation into these portions can be prevented.
- the epitaxial layer 8 is heat-treated at 1400 ° C. to 2000 ° C., for example. As a result, ions of the p-type impurity implanted into the drain region 13 are activated, and the second region 30 of the gate breakdown voltage holding region 27 is formed.
- a SiO 2 material is deposited from above the epitaxial layer 8 by a CVD method. Thereby, the gate insulating film 22 is formed.
- a doped polysilicon material is deposited from above the epitaxial layer 8 by CVD. The deposition of the polysilicon material is continued until at least the gate trench 15 and the source trench 24 are filled. Thereafter, the deposited polysilicon material is etched back until the etch back surface is flush with the surface 9 of the epitaxial layer 8. Subsequently, only the polysilicon material remaining in the source trench 24 is removed by dry etching. Thereby, the gate electrode 23 made of the polysilicon material remaining in the gate trench 15 is formed.
- SiO 2 material is deposited from above the epitaxial layer 8 by the CVD method.
- the interlayer insulating film 35 is formed.
- the interlayer insulating film 35 and the gate insulating film 22 are successively patterned by a known patterning technique. As a result, contact holes 36 are formed in the interlayer insulating film 35 and the gate insulating film 22.
- a polysilicon material is deposited by CVD until the contact holes 36 are filled.
- n-type or p-type impurities are implanted into the deposited polysilicon material.
- the implantation conditions at this time vary depending on the type of impurities, but the acceleration energy is, for example, 10 keV to 100 keV.
- the MIS transistor 1 shown in FIG. 2 is obtained by forming the intermediate layer 39, the metal layer 40, the drain electrode 44, and the like.
- the MIS transistor 1 is used as a switching element of a drive circuit (inverter circuit) of an electric motor (an example of an inductive load), for example.
- a predetermined voltage (gate threshold voltage) is applied to the gate pad 4 while a drain voltage having a positive drain side is applied between the source pad 2 (source electrode 37) and the drain electrode 44 (between the source and drain).
- the gate trench 15 and the vicinity (for example, the gate trench 15) in the n-type drain region 13. (Side) the majority carrier electrons may recombine with the holes transferred from the p-type channel region 12. Therefore, the SiC crystal defects of the epitaxial layer 8 are expanded in a direction parallel to the stacking direction of the epitaxial layer 8 due to the energy generated by the coupling, and may reach a drain current path (for example, a channel) when turned on. .
- the MIS transistor 1 performs a switching operation by forming a channel in the vicinity of the side surface 18 of the gate trench 15 in the channel region 12, there is a possibility that the on-resistance increases.
- the polysilicon layer 38 forms a heterojunction with the drain region 13 (drain exposed region 33). Therefore, current flows preferentially through the heterojunction between the second portion 42 of the polysilicon layer 38 and the drain region 13, and the current flowing through the body diode 43 can be reduced or eliminated.
- the current flowing through the MIS transistor 1 in this way can be supplied to the electric motor as a return current, for example.
- the off-state current flows from the second portion 42 of the polysilicon layer 38 formed in the source trench 24 at the center of the unit cell 21 surrounded by the gate trench 15 to the drain region 13. Almost no carrier movement occurs near 15 (that is, between the p-type channel region 12 and the n-type drain region 13). Therefore, recombination of holes and electrons in the drain region 13 can be prevented. As a result, expansion of SiC crystal defects in the epitaxial layer 8 can be suppressed, so that an increase in on-resistance of the transistor 1 can be suppressed.
- an electric field is applied to the gate insulating film 22 interposed between the gate electrode 23 and the epitaxial layer 8. This electric field is generated due to a potential difference between the gate electrode 23 and the epitaxial layer 8.
- an equipotential surface with a very high potential is distributed with the gate electrode 23 as a reference (0 V), and an interval between the equipotential surfaces is small, so that a very large electric field is generated.
- the drain voltage is 900 V
- an equipotential surface of 900 V is distributed near the back surface 7 of the substrate 5 in contact with the drain electrode 44, and the voltage increases from the back surface 7 of the substrate 5 toward the surface 9 of the epitaxial layer 8.
- the distance D 1 (see the AA cross section in FIG. 2) of the source trenches 24 adjacent to each other on the diagonal line of the intersecting portion 17 of the gate trench 15 is set so as to sandwich the linear portion 16 of the gate trench 15. It becomes larger than the distance D 2 (see the BB cross section in FIG. 2) between the adjacent source trenches 24 (for example, in the first embodiment, D 1 is 1.4 times D 2 ). Therefore, an equipotential surface enters directly under the corner edge portion 31 of the gate trench 15 having a relatively wide space, and the equipotential surfaces are densely formed. As a result, the dielectric breakdown of the gate insulating film 22 is particularly likely to occur near the corner edge portion 31 of the gate trench 15.
- the gate breakdown voltage holding region 27 (first region 29) is formed at the corner edge portion 31 of the gate trench 15.
- the body diode 48 can be formed in the vicinity of the corner edge portion 31 of the gate trench 15 by the junction (pn junction) between the first region 29 and the drain region 13.
- a source breakdown voltage holding region 28 is formed at the edge portion 32 of the source trench 24 formed in the center portion of each unit cell 21. Therefore, an annular body diode 49 surrounding the edge portion 32 of the source trench 24 can be formed by the junction (pn junction) between the source breakdown voltage holding region 28 and the drain region 13.
- the presence of the depletion layer generated in these body diodes 48 and 49 can prevent an equipotential surface from entering between the corner edge portion 31 of the gate trench 15 and the edge portion 32 of the source trench 24, and the gate insulating film 22. Can be kept away from As a result, crowding of equipotential surfaces in the vicinity of the corner edge portion 31 of the gate trench 15 can be prevented. As a result, since the electric field applied to the gate insulating film 22 can be reduced, dielectric breakdown can be suppressed. In addition, since the concentration of the first region 29 is higher than the concentration of the drain region 13, the depletion layer generated by the junction (pn junction) between the first region 29 and the drain region 13 is prevented from spreading too much into the epitaxial layer 8. be able to.
- the first region 29 is formed so as to reach the channel region 12 immediately above the corner edge portion 31 through the corner edge portion 31, but the channel is formed in the corner portion 20 of the unit cell 21. It is not formed or even if it is formed, the current flowing through the channel is very small. Therefore, by forming the gate breakdown voltage holding region 27 (first region 29) so as to reach the portion immediately above the corner edge 31 in the channel region 12, the performance of the gate insulating film 22 is hardly affected. The destruction prevention effect can be further improved.
- a gate breakdown voltage holding region 27 (second region 30) having a width narrower than the width of the linear portion 16 is formed in the linear portion 16 of the gate trench 15.
- a depletion layer generated by the junction (pn junction) between the second region 30 and the drain region 13 can be generated along the linear portion 16 of the gate trench 15. Therefore, the electric field generated immediately below the linear portion 16 of the gate trench 15 can be relaxed by the depletion layer. As a result, the electric field generated in the gate insulating film 22 can be alleviated uniformly.
- the gate breakdown voltage holding region 27 (second region 30) is not formed on the side surface 18 of the linear portion 16 of the gate trench 15 (that is, the portion where the channel is formed in the unit cell 21). Therefore, the channel characteristics can be controlled with high accuracy. Further, the concentration of the second region 30 is higher than the concentration of the first region 29, and the thickness T 2 of the second region 30 is smaller than the thickness T 1 of the first region 29 (T 1 > T 2 ). Therefore, an increase in channel resistance can be prevented.
- the gate breakdown voltage holding region 27 and the source breakdown voltage holding region 28 can be formed simultaneously.
- the structure of the MIS transistor 1 for preventing the dielectric breakdown of the gate insulating film 22 can be easily manufactured.
- the drain exposed region 33 protrudes from the central portion of the bottom surface 26 of the source trench 24 to a position flush with the surface 9 of the epitaxial layer 8 as in the MIS transistor 47 of FIG. parts may have a step S 1 between the (different other parts than the central portion).
- Such a configuration can be obtained, for example, by forming the source trench 24 in a ring shape in the step shown in FIG. 3B.
- FIGS. 5A and 5B are schematic plan views of a planar gate type MIS transistor according to the second embodiment of the present invention.
- FIG. 5A is an overall view, and FIG. Each enlarged view is shown.
- FIG. 6 is a cross-sectional view of the planar gate type MIS transistor shown in FIGS. 5A and 5B, and shows cross sections taken along section lines CC and DD in FIG. 5B, respectively.
- the MIS transistor 51 is a planar gate type DMISFET adopting SiC, and has, for example, a square chip shape in plan view as shown in FIG.
- Each of the chip-like MIS transistors 51 has a length of about several millimeters in the vertical and horizontal directions on the paper surface of FIG.
- a source pad 52 is formed on the surface of the MIS transistor 51.
- the source pad 52 has a substantially square shape in plan view with four corners curved outward, and is formed so as to cover almost the entire surface of the MIS transistor 51.
- the source pad 52 has a removal region 53 near the center of one side.
- the removal region 53 is a region where the source pad 52 is not formed.
- the MIS transistor 51 includes a substrate 55 made of SiC of n + type (for example, the concentration is 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 ).
- the substrate 55 functions as the drain of the MIS transistor 51, and its front surface 56 (upper surface) is a Si surface and its rear surface 57 (lower surface) is a C surface.
- an epitaxial layer 58 made of SiC having an n ⁇ type (for example, concentration of 1 ⁇ 10 15 to 1 ⁇ 10 17 cm ⁇ 3 ) having a lower concentration than that of the substrate 55 is laminated.
- the thickness of the epitaxial layer 58 as a semiconductor layer is, for example, 1 ⁇ m to 100 ⁇ m.
- the epitaxial layer 58 is formed on the substrate 55 by so-called epitaxial growth.
- the epitaxial layer 58 formed on the surface 56 that is the Si surface is grown with the Si surface as the main growth surface. Therefore, the surface 59 of the epitaxial layer 58 formed by the growth is a Si surface, like the surface 56 of the substrate 55.
- the MIS transistor 51 includes an active region 60 that is disposed in the center of the epitaxial layer 58 in plan view and functions as the MIS transistor 51, and a transistor peripheral region 61 that surrounds the active region 60. Is formed.
- a p-type (for example, a concentration of 1.0 ⁇ 10 16 cm ⁇ 3 to 1.0 ⁇ 10 19 cm ⁇ 3 ) channel region 62 is formed in the row direction and on the surface layer of the epitaxial layer 58. A large number are arranged in a matrix (matrix) at a constant pitch in the column direction.
- Each channel region 62 has a square shape in plan view. For example, the length in the vertical and horizontal directions on the paper surface of FIG. 5B is about 7.2 ⁇ m.
- the region on the substrate 55 side with respect to the channel region 62 in the epitaxial layer 58 is an n ⁇ -type drain region 63 that is maintained as it is after epitaxial growth.
- an n + -type (for example, concentration of 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 ) source region 64 is formed in almost the entire region on the surface 59 side.
- the region between the channel regions 62 arranged in a matrix at a constant pitch has a lattice shape having a constant (for example, 2.8 ⁇ m) width.
- the inter-channel region 65 includes a linear portion 66 extending linearly in each of the row direction and the column direction along the four side surfaces of each channel region 62 between the adjacent channel regions 62, and It includes an intersecting portion 67 where the linear portion 66 extending in the row direction intersects with the linear portion 66 extending in the column direction.
- the intersecting portion 67 is surrounded by the corners inside the four arranged channel regions 62, and is defined by the extended lines of the four sides of the channel region 62. This is a square portion in plan view.
- each unit cell 71 has, for example, a length of about 10 ⁇ m in the vertical and horizontal directions on the paper surface of FIG.
- the depth direction of the channel region 62 is the gate length direction
- the circumferential direction of the channel region 62 orthogonal to the gate length direction is the gate width direction.
- a lattice-like gate insulating film 72 is formed along the interchannel region 65.
- the gate insulating film 72 straddles between adjacent channel regions 62 and covers a portion surrounding the source region 64 in the channel region 62 (periphery of the channel region 62) and the outer periphery of the source region 64.
- the gate insulating film 72 is made of SiO 2 and has a thickness of about 400 mm and is almost uniform.
- a gate electrode 73 is formed on the gate insulating film 72.
- the gate electrode 73 is formed in a lattice shape along the lattice-shaped gate insulating film 72, and faces the peripheral portion of each channel region 62 with the gate insulating film 72 interposed therebetween.
- the gate electrode 73 is made of polysilicon and, for example, is doped with an n-type impurity at a high concentration.
- the thickness of the gate electrode 73 is about 6000 mm, for example.
- a source trench 74 having a square shape in plan view is formed from the surface 59 of the epitaxial layer 58 through the source region 64 and the channel region 62 to reach the drain region 63.
- the source trench 74 has a U-shaped cross section in which a side surface 75 and a bottom surface 76 facing each other are continuous via a curved surface.
- the epitaxial layer 58 includes a p-type gate breakdown voltage holding region 77 and a source breakdown voltage holding region 78 as a first breakdown voltage holding region, which are formed by implanting p-type impurities into the epitaxial layer 58. Yes.
- the gate breakdown voltage holding region 77 is formed along the lattice-shaped inter-channel region 65, and the first region 79 as the fourth breakdown voltage holding region formed at the intersection 67 of the inter-channel region 65 and the inter-channel region. It integrally includes a second region 80 as a fifth breakdown voltage holding region formed in the 65 linear portions 66.
- the first region 79 is formed so as to reach the corner portion 81 of the channel region 62 formed at each corner portion 70 of the four unit cells 71 facing the intersecting portion 67. That is, the first region 79 is formed in a square shape slightly larger than the intersecting portion 67 of the inter-channel region 65 in plan view, and each corner of each of the four unit cells 71 facing the intersecting portion 67 is formed. It enters into each corner 70.
- the concentration of the first region 79 is not less than the concentration of the channel region 62 and higher than the concentration of the drain region 63, for example, 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 . Further, the thickness T 4 along the direction from the surface 59 of the epitaxial layer 58 to the substrate 55 in the first region 79 is, for example, about 0.8 ⁇ m.
- the second region 80 is formed in a straight line having a constant width that connects the centers of the sides of the intersecting portions 67 adjacent to each other in plan view, and is narrower than the width (for example, 3.0 ⁇ m) of the linear portion 66 ( For example, 1.5 ⁇ m).
- the concentration of the second region 80 is higher than that of the channel region 62 and higher than that of the first region 79, for example, 2 ⁇ 10 18 to 2 ⁇ 10 19 cm ⁇ 3 .
- the thickness T 5 along the direction from the surface 59 of the epitaxial layer 58 to the substrate 55 in the second region 80 is equal to or less than the thickness T 4 of the first region 79 (that is, T 4 ⁇ T 5 ).
- the source breakdown voltage holding region 78 has an edge portion 82 of the source trench 74 where the bottom surface 76 and the side surface 75 intersect so that the bottom surface 76 of the source trench 74 is exposed, and a part of the side surface 75 of the source trench 74 from the edge portion 82.
- the channel region 62 is formed so as to reach the channel region 62.
- a drain exposed region 83 having a square shape in plan view and formed of a part of the drain region 63 is formed at the center of the bottom surface 76 of the source trench 74.
- the concentration of the source breakdown voltage holding region 78 is the same as that of the first region 79 of the gate breakdown voltage holding region 77 (for example, 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 ).
- the thickness T 6 along the direction from the bottom surface of the source trench 74 to the substrate 55 in the source breakdown voltage holding region 78 is, for example, about 0.8 ⁇ m, and the deepest portion of the source breakdown voltage holding region 78 is the gate breakdown voltage holding region.
- 77 (first region 79 and second region 80) is deeper than the deepest part.
- a p-type guard ring 84 is provided on the surface layer portion of the epitaxial layer 58 at a distance from the active region 60 so as to surround the unit cells 71 (active regions 60) arranged in a matrix. Are formed (four in the second embodiment). These guard rings 84 can be formed by the same ion implantation step as the step of forming the p-type channel region 62.
- Each guard ring 84 is formed in a square shape in plan view along the outer periphery of the MIS transistor 51 in plan view.
- An interlayer insulating film 85 made of SiO 2 is laminated on the epitaxial layer 58 so as to cover the gate electrode 73.
- a contact hole 86 having a diameter larger than that of the source trench 74 is formed in the interlayer insulating film 85 and the gate insulating film 72.
- a source electrode 87 is formed on the interlayer insulating film 85.
- the source electrode 87 enters the source trenches 74 of all the unit cells 71 through the contact holes 86 all together, and in each unit cell 71, the drain exposed region 83, the source It is in contact with the breakdown voltage holding region 78, the channel region 62 and the source region 64. That is, the source electrode 87 is a wiring common to all the unit cells 71.
- An interlayer insulating film (not shown) is formed on the source electrode 87, and the source electrode 87 is connected to the source pad 52 (see FIG. 5A) via the interlayer insulating film (not shown). ) Is electrically connected.
- the gate pad 54 (see FIG. 5A) is electrically connected to the gate electrode 73 via a gate wiring (not shown) routed on the interlayer insulating film (not shown). ing.
- the source electrode 87 includes a polysilicon layer 88, an intermediate layer 89, and a metal layer 90 as barrier forming layers in order from the contact side with the epitaxial layer 58.
- the polysilicon layer 88 is a doped layer formed using doped polysilicon doped with impurities, and is, for example, 1 ⁇ 10 15 cm ⁇ 3 or more, preferably 1 ⁇ 10 19 to 1 ⁇ 10 21 cm. This is a heavily doped layer doped with impurities at a high concentration of ⁇ 3 .
- Impurities when forming the polysilicon layer 88 as a doped layer include n-type impurities such as N (nitrogen), P (phosphorus), As (arsenic), Al (aluminum), B A p-type impurity such as (boron) can be used. Further, the thickness of the polysilicon layer 88 is, for example, 5000 to 10,000 mm.
- the polysilicon layer 88 is formed so as to cover the entire surface of the unit cell 71 exposed in the contact hole 86, and the drain exposed region 83 and the source breakdown voltage holding region in the source trench 74. 78 and all of the source region 64 are in contact. That is, the polysilicon layer 88 is in contact with the source breakdown voltage holding region 78 on the side surface 75 of the source trench 74, and the first portion 91 in contact with the source region 64 on the side surface 75 and the peripheral portion of the source trench 74 on the surface 59 of the epitaxial layer 58. And a second portion 92 in contact with the drain exposed region 83 at the bottom surface 76 of the source trench 74.
- the first portion 91 forms an ohmic junction between both the source breakdown voltage holding region 78 and the source region 64.
- the diffusion potential of body diode 93 (pn diode formed by the junction of source breakdown voltage holding region 78 and drain region 63) inherent in MIS transistor 51 is between second portion 92 and drain exposed region 83.
- a heterojunction (for example, the height of the junction barrier is 1 eV to 1.5 eV) having a junction barrier smaller than (for example, 2.8 eV to 3.2 eV) is formed.
- the intermediate layer 89 is a metal layer stacked on the polysilicon layer 88, and includes a single layer containing Ti (titanium) or a plurality of layers including a layer containing Ti.
- the layer containing Ti can be formed using Ti, TiN (titanium nitride), or the like. Further, the thickness of the intermediate layer 89 is, for example, 200 nm to 500 nm.
- the metal layer 90 is laminated on the intermediate layer 89 and contains, for example, Al (aluminum), Au (gold), Ag (silver), Cu (copper), Mo (molybdenum), alloys thereof, and the like. It can be formed using a metal material.
- the metal layer 90 is the outermost layer of the source electrode 87.
- the thickness of the metal layer 90 is, for example, 1 ⁇ m to 5 ⁇ m.
- the metal layer 90 As a combination of the polysilicon layer 88, the intermediate layer 89, and the metal layer 90 as described above, in the second embodiment, Poly-Si (polysilicon layer 88), Ti (intermediate layer 89), TiN (intermediate layer 89) And a laminated structure (Poly-Si / Ti / TiN / Al) in which Al (metal layer 90) is sequentially laminated.
- the metal layer 90 preferably has a Mo layer. Since Mo has a high melting point, if the Mo layer is included in the metal layer 90, melting of the metal layer 90 due to heat generated when a large current flows through the source electrode 87 can be suppressed.
- a drain electrode 94 is formed on the back surface 57 of the substrate 55 so as to cover the entire area.
- the drain electrode 94 is a common electrode for all the unit cells 71.
- As the drain electrode 94 for example, a stacked structure (Ti / Ni / Au / Ag) in which Ti, Ni, Au, and Ag are stacked in this order from the substrate 55 side can be applied.
- 7A to 7F are schematic cross-sectional views showing a part of the manufacturing process of the planar gate type MIS transistor shown in FIG. 6, and show a cut surface at the same position as FIG.
- an n-type impurity for example, N () is formed on the surface 56 (Si surface) of the substrate 55 by an epitaxial growth method such as a CVD method, an LPE method, or an MBE method. SiC crystal is grown while doping nitrogen), P (phosphorus), As (arsenic) and the like. As a result, an n ⁇ type epitaxial layer 58 is formed on the substrate 55.
- p-type impurities for example, Al (aluminum), B (boron), etc.
- n-type impurities are implanted into the epitaxial layer 58 from the surface 59 of the epitaxial layer 58.
- the epitaxial layer 58 is heat-treated at, for example, 1400 ° C. to 2000 ° C.
- ions of the p-type impurity and the n-type impurity implanted into the surface layer portion of the epitaxial layer 58 are activated, and the channel region 62, the source region 64, and the guard ring 84 are simultaneously formed according to the implanted locations.
- a drain region 63 that maintains the state after epitaxial growth is formed in the base layer portion of the epitaxial layer 58.
- the inter-channel region 65 is formed at the same time, and a large number of unit cells 71 are formed in the epitaxial layer 58.
- the epitaxial layer 58 is etched using a mask having an opening in the region where the source trench 74 is to be formed. Thereby, the epitaxial layer 58 is dry-etched from the surface 59 (Si surface), and the source trench 74 is formed.
- the etching gas includes, for example, a mixed gas (SF 6 / O 2 gas) containing SF 6 (sulfur hexafluoride) and O 2 (oxygen), SF 6 , O 2, and HBr (hydrogen bromide).
- SF 6 / O 2 gas containing SF 6 (sulfur hexafluoride) and O 2 (oxygen), SF 6 , O 2, and HBr (hydrogen bromide).
- a mixed gas SF 6 / O 2 / HBr gas
- a first resist 95 having an opening exposing the crossing portion 67 of the inter-channel region 65 and the edge portion 82 of the source trench 74 is formed on the epitaxial layer 58.
- the linear portion 66 of the inter-channel region 65 and the central portion of the bottom surface 76 of the source trench 74 are covered with the first resist 95.
- the epitaxial layer 58 is heat-treated at, for example, 1400 ° C. to 2000 ° C.
- ions of the p-type impurity implanted into the drain region 63 are activated, and the first region 79 of the gate breakdown voltage holding region 77 and the source breakdown voltage holding region 78 are simultaneously formed. Further, a drain exposed region 83 is formed in a portion of the bottom surface 76 of the source trench 74 that is covered with the first resist 95.
- a second resist 96 having an opening in a region where the second region 80 of the gate breakdown voltage holding region 77 is to be formed is formed on the epitaxial layer 58.
- the intersecting portion 67 of the inter-channel region 65 and the side surface 75 and the bottom surface 76 of the source trench 74 are covered with the second resist 96.
- a p-type impurity is implanted (implanted) toward the linear portion 66 of the inter-channel region 65 exposed from the opening of the second resist 96.
- the intersecting portion 67 of the inter-channel region 65, the side surface 75, and the bottom surface 76 are protected by the second resist 96, so that p-type impurity implantation into these portions can be prevented.
- the epitaxial layer 58 is heat-treated at, for example, 1400 ° C. to 2000 ° C. As a result, ions of the p-type impurity implanted into the drain region 63 are activated, and the second region 80 of the gate breakdown voltage holding region 77 is formed.
- a SiO 2 material is deposited from above the epitaxial layer 58 by a CVD method. Thereby, the gate insulating film 72 is formed. Subsequently, a doped polysilicon material is deposited from above the epitaxial layer 58 by CVD. Thereafter, the deposited polysilicon material is patterned by a known patterning technique, whereby the gate electrode 73 is formed.
- a SiO 2 material is deposited from above the epitaxial layer 58 by a CVD method.
- an interlayer insulating film 85 is formed.
- the interlayer insulating film 85 and the gate insulating film 72 are successively patterned by a known patterning technique. As a result, contact holes 86 are formed in the interlayer insulating film 85 and the gate insulating film 72.
- a polysilicon material is deposited by CVD until the contact hole 86 is filled.
- n-type or p-type impurities are implanted into the deposited polysilicon material.
- the implantation conditions at this time vary depending on the type of impurities, but the acceleration energy is, for example, 10 keV to 100 keV.
- the intermediate layer 89, the metal layer 90, the drain electrode 94, and the like are formed, whereby the MIS transistor 51 shown in FIG. 6 is obtained.
- the same operational effects as those of the MIS transistor 1 of the first embodiment described above can be exhibited. That is, in the second embodiment, the polysilicon layer 88 forms a heterojunction with the drain region 63 (drain exposed region 83). Therefore, when a back electromotive force is applied between the source and the drain, a current flows preferentially through the heterojunction between the second portion 92 of the polysilicon layer 88 and the drain region 63, and the current flowing through the body diode 93 is reduced. Or can be eliminated.
- the current flowing through the MIS transistor 51 in this way can be supplied to the electric motor as a return current, for example.
- the off-state current flows from the second portion 92 of the polysilicon layer 88 formed in the source trench 74 in the center of the unit cell 71 surrounded by the inter-channel region 65 to the drain region 63, so that the channel Almost no carrier movement occurs in the vicinity of the inter-region 65 (that is, between the p-type channel region 62 and the n-type drain region 63). Therefore, recombination of holes and electrons in the drain region 63 can be prevented. As a result, expansion of SiC crystal defects in the epitaxial layer 58 can be suppressed, so that an increase in on-resistance of the transistor 51 can be suppressed.
- the inter-channel region 65 is formed in a lattice shape as in the second embodiment, and the window portion of the lattice-shaped inter-channel region 65 is formed.
- the dielectric breakdown of the gate insulating film 72 occurs particularly in the vicinity of the corner portions 81 of the channel regions 62 formed at the respective corner portions 70 of the unit cells 71.
- D 4 is 1.4 times D 4 . Therefore, an equipotential surface enters immediately below the corner portion 81 of the channel region 62 having a relatively wide space, and the equipotential surfaces are densely formed. As a result, the dielectric breakdown of the gate insulating film 72 is particularly likely to occur near the corner portion 81 of the channel region 62.
- the gate breakdown voltage holding region 77 (first region 79) is formed at the corner portion 81 of the channel region 62.
- the body diode 98 can be formed in the vicinity of the corner portion 81 of the channel region 62 by the junction (pn junction) between the first region 79 and the drain region 63.
- a source breakdown voltage holding region 78 is formed at the edge portion 82 of the source trench 74 formed in the central portion of each unit cell 71. Therefore, an annular body diode 99 surrounding the edge portion 82 of the source trench 74 can be formed by the junction (pn junction) between the source breakdown voltage holding region 78 and the drain region 63.
- the presence of the depletion layer generated in these body diodes 98 and 99 can prevent an equipotential surface from entering between the corner portion 81 of the channel region 62 and the edge portion 82 of the source trench 74. You can keep away. As a result, crowding of equipotential surfaces in the vicinity of the corner portion 81 of the channel region 62 can be prevented. As a result, the electric field applied to the gate insulating film 72 can be reduced, so that dielectric breakdown can be suppressed.
- the concentration of the first region 79 is higher than the concentration of the drain region 63, the depletion layer generated by the junction (pn junction) between the first region 79 and the drain region 63 is prevented from spreading too much into the epitaxial layer 58. be able to.
- a gate breakdown voltage holding region 77 (second region 80) having a width narrower than the width of the linear portion 66 is formed in the linear portion 66 of the inter-channel region 65. Accordingly, a depletion layer generated by the junction (pn junction) between the second region 80 and the drain region 63 can be generated along the linear portion 66 of the inter-channel region 65. Therefore, an electric field generated immediately below the linear portion 66 of the inter-channel region 65 can be relaxed by the depletion layer. As a result, the electric field generated in the gate insulating film 72 can be alleviated uniformly.
- the gate breakdown voltage holding region 77 (second region 80) is not formed in the peripheral portion of the channel region 62 (that is, the portion where the channel is formed in the unit cell 71). Therefore, the channel characteristics can be controlled with high accuracy.
- the drain exposed region 83 protrudes from the center of the bottom surface 76 of the source trench 74 to a position flush with the surface 59 of the epitaxial layer 58 as in the MIS transistor 97 of FIG. parts may have a step S 2 between the (different other parts than the central portion).
- Such a configuration can be obtained, for example, by forming the source trench 74 annularly in the step shown in FIG. 7B.
- FIGS. 9A and 9B are schematic plan views of a trench gate type MIS transistor 101 according to the third embodiment of the present invention.
- FIG. 9A is an overall view, and FIG. Each internal enlarged view is shown.
- FIG. 10 is a cross-sectional view of the trench gate type MIS transistor 101 of FIGS. 9A and 9B, and shows cross sections along the cutting lines EE, FF, and GG of FIG. 9B. Each is shown.
- the MIS transistor 101 is a trench gate type DMISFET (Double-diffused Metal-Insulator-Semiconductor-Field-Effect-Transistor) employing SiC, and has, for example, a square chip shape in plan view as shown in FIG.
- the chip-like MIS transistor 101 has a length of about several millimeters in the vertical and horizontal directions on the paper surface of FIG.
- a source pad 102 is formed on the surface of the MIS transistor 101.
- the source pad 102 has a substantially square shape in plan view with four corners curved outward, and is formed so as to cover almost the entire surface of the MIS transistor 101.
- the source pad 102 has a removal region 103 near the center of one side. This removal region 103 is a region where the source pad 102 is not formed.
- the MIS transistor 101 includes a substrate 105 made of SiC of n + type (for example, the concentration is 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 ).
- the substrate 105 functions as the drain of the MIS transistor 101, and the front surface 106 (upper surface) is a Si surface and the rear surface 107 (lower surface) is a C surface.
- an epitaxial layer 108 made of SiC having an n ⁇ type (for example, concentration of 1 ⁇ 10 15 to 1 ⁇ 10 17 cm ⁇ 3 ) having a lower concentration than that of the substrate 105 is laminated.
- the thickness of the epitaxial layer 108 as a semiconductor layer is, for example, 1 ⁇ m to 100 ⁇ m.
- the epitaxial layer 108 is formed on the substrate 105 by so-called epitaxial growth.
- the epitaxial layer 108 formed on the surface which is the Si surface is grown using the Si surface as a growth main surface. Therefore, the surface 109 of the epitaxial layer 108 formed by growth is a Si surface, like the surface 106 of the substrate 105.
- the MIS transistor 101 is arranged in the center of the epitaxial layer 108 in plan view, and functions as the MIS transistor 101, and a transistor peripheral region 111 surrounding the active region 110. Is formed.
- gate trenches 112 are formed in the epitaxial layer 108 in a lattice pattern (see FIG. 9B). By this gate trench 112, the epitaxial layer 108 is partitioned into a plurality of cells 113 each having a square shape (square shape).
- the plurality of cells 113 includes a Schottky cell 114 and a pn diode cell 115 having a relatively smaller planar area than the Schottky cell 114.
- the Schottky cell 114 has an area corresponding to four of the pn diode cells 115, and the length of one side of the Schottky cell 114 corresponds to twice the length of one side of the pn diode cell 115.
- the size of the pn diode cell 115 is about 6 ⁇ m in the vertical and horizontal directions on the paper surface of FIG. 9B, and the size of the Schottky cell 114 is the length in the same direction. Each is about 12 ⁇ m.
- One Schottky cell 114 and a plurality of pn diode cells 115 (12 pn diode cells 115 in this embodiment) surrounding the Schottky cell 114 constitute one cell group.
- Cell groups are further arranged in a matrix.
- the pn diode cell 115 is shared. That is, the pn diode cell 115 surrounding the Schottky cell 114 of a certain cell group is also used as the pn diode cell 115 surrounding the Schottky cell 114 of the cell group adjacent to the cell group.
- the epitaxial layer 108 has n + -type (for example, a concentration of 1 ⁇ 10 18 to 1 ⁇ 10 10 in order from the front surface 109 side to the back surface 116 side. 21 cm ⁇ 3 ) source region 117, p-type (for example, concentration of 1.0 ⁇ 10 16 cm ⁇ 3 to 1.0 ⁇ 10 19 cm ⁇ 3 ) channel region 118 and drain region 119.
- n + -type for example, a concentration of 1 ⁇ 10 18 to 1 ⁇ 10 10 in order from the front surface 109 side to the back surface 116 side. 21 cm ⁇ 3
- p-type for example, concentration of 1.0 ⁇ 10 16 cm ⁇ 3 to 1.0 ⁇ 10 19 cm ⁇ 3
- the drain region 119 is an n ⁇ -type region in which the state after the epitaxial growth is maintained, and is integrally connected at the bottom of all the cells 113 and shared between them. That is, the gate trench 112 defines the cells 113 such that the source region 117 and the channel region 118 are exposed to the side surface 124 and the deepest portion is located in the middle of the drain region 119.
- Such a gate trench 112 includes a linear portion 120 extending linearly in the row direction and the column direction along the four side surfaces of each cell 113 between adjacent cells 113 and a line extending in the row direction.
- intersect is included.
- a gate insulating film 122 is formed on the inner surface of the gate trench 112 so as to cover the entire area. In the gate insulating film 122, the portion on the bottom surface 123 of the gate trench 112 is thicker than the portion on the side surface 124 of the gate trench 112.
- the gate electrode 125 is embedded in the gate trench 112 by filling the inside of the gate insulating film 122 in the gate trench 112 with polysilicon.
- the source region 117 and the drain region 119 are arranged apart from each other via the channel region 118 in the vertical direction perpendicular to the surface 109 of the epitaxial layer 108.
- a vertical MIS transistor 101 structure (first and second MIS transistor structures) is configured.
- an HD source trench 126 as a second source trench having a square shape in plan view, reaching the drain region 119 from the surface 109 of the epitaxial layer 108 through the source region 117 and the channel region 118. It is formed (see the FF cross section and the GG cross section in FIG. 9B and FIG. 10).
- the depth of the HD source trench 126 is the same as that of the gate trench 112.
- a p-type (for example, concentration of 1 ⁇ 10 17 to 9 ⁇ 10 19 cm ⁇ 3 ) HD breakdown voltage holding region 127 (second breakdown voltage holding region) is formed.
- the HD withstand voltage holding region 127 is formed by intersecting the bottom surface 128 and the side surface 129 of the HD source trench 126, and the annular edge portion 130 surrounding the bottom surface 128 and the side surface 129 of the HD source trench 126 from the edge portion 130.
- An annular shape reaching the exposed channel region 118 is formed.
- a square-shaped Schottky region 131 in plan view made of a part of the drain region 119 is formed at the center of the bottom surface 128 of the HD source trench 126 surrounded by the HD breakdown voltage holding region 127.
- the Schottky region 131 is formed with an area where a depletion layer generated from the pn junction (body diode 132) between the Schottky region 131 and the HD breakdown voltage holding region 127 is not connected.
- the length L 1 of one side thereof Is 4 ⁇ m or more.
- a Di source trench serving as a first source trench having a square shape in plan view reaching the drain region 119 from the surface 109 of the epitaxial layer 108 through the source region 117 and the channel region 118.
- 133 is formed (see the EE cross section and the GG cross section in FIG. 9B and FIG. 10).
- the depth of the Di source trench 133 is the same as that of the gate trench 112.
- the area of Di source trenches 133, smaller than the Schottky region 131, the length L 2 of one side is about 3 [mu] m.
- Di breakdown voltage holding region 134 (first breakdown voltage holding region) is formed.
- the Di withstand voltage holding region 134 is formed on the entire bottom surface 135 of the Di source trench 133, and is further formed by intersecting the bottom surface 135 and the side surface 136. To the channel region 118 exposed on the side surface 136 of the Di source trench 133.
- the Di source trench 133 has a p + type (for example, a concentration of 1.0 ⁇ 10 18 cm ⁇ 3 to 2.0 ⁇ 10 21) on the surface layer portion of the Di breakdown voltage holding region 134 at the center of the bottom surface 135. cm ⁇ 3 ) bottom channel contact region 138 is formed.
- a contact can be made (electrically connected) to the channel region 118 of the pn diode cell 115 via the Di breakdown voltage holding region 134.
- the pn diode cell 115 is formed by a pn junction between the Di breakdown voltage holding region 134 and the drain region 119, and serves as a bottom channel as a contact on the anode side.
- a body diode 139 having a contact region 138 and having a substrate 105 as a cathode side contact is incorporated.
- a G breakdown voltage holding region 140 (relay region) is formed at each intersection 121 of the gate trench 112 that partitions the plurality of cells 113.
- the G withstand voltage holding region 140 is formed on the entire bottom surface 123 of the gate trench 112 at the intersection 121 and is further formed below the corners of the cells 113 facing the intersection 121 from the bottom 123.
- the corner edge portion 141 is formed so as to reach the channel region 118 immediately above the corner edge portion 141.
- the G breakdown voltage holding region 140 is formed in a square shape slightly larger than the intersection 121 of the gate trench 112 in plan view, and each corner of each cell 113 facing the intersection 121 is provided. In each.
- the concentration of the G breakdown voltage holding region 140 is higher than that of the channel region 118 and higher than that of the drain region 119, for example, 1 ⁇ 10 17 to 9 ⁇ 10 19 cm ⁇ 3 .
- a plurality of p-type guard rings 142 are formed in the surface layer portion of the epitaxial layer 108 so as to surround the active region 110 and spaced from the active region 110.
- These guard rings 142 can be formed by the same ion implantation step as the step of forming the p-type channel region 118.
- Each guard ring 142 is formed in a square ring shape in plan view along the outer periphery of the MIS transistor 101 in plan view.
- An interlayer insulating film 143 made of SiO 2 is laminated on the epitaxial layer 108 so as to cover the gate electrode 125.
- contact holes 144 and 145 having larger diameters than the HD source trench 126 and the Di source trench 133 are formed.
- a source electrode 146 is formed on the interlayer insulating film 143.
- the source electrode 146 enters all the HD source trenches 126 and the Di source trenches 133 through the contact holes 144 and 145 at the same time.
- the source electrode 146 is in contact with the Schottky region 131, the HD withstand voltage holding region 127, and the source region 117 in order from the bottom side of the HD source trench 126.
- the bottom channel contact region 138, the Di breakdown voltage holding region 134 and the source region 117 are in contact with each other in order from the bottom side of the Di source trench 133. That is, the source electrode 146 is a common wiring for all the cells 113.
- An interlayer insulating film 143 (not shown) is formed on the source electrode 146, and the source electrode 146 is connected to the source pad 102 (FIG. 9A) via the interlayer insulating film 143 (not shown). ))) Is electrically connected.
- the gate pad 104 (see FIG. 9A) is electrically connected to the gate electrode 125 through a gate wiring (not shown) routed on the interlayer insulating film 143 (not shown). Has been.
- the source electrode 146 has a polysilicon layer 147, an intermediate layer 148, and a metal layer 149 as a barrier forming layer in order from the contact side with the epitaxial layer.
- the polysilicon layer 147 is a doped layer formed using doped polysilicon doped with impurities, and is, for example, 1 ⁇ 10 15 cm ⁇ 3 or more, preferably 1 ⁇ 10 19 to 1 ⁇ 10 21 cm. This is a heavily doped layer doped with impurities at a high concentration of ⁇ 3 .
- Impurities when forming the polysilicon layer 147 as a doped layer include n-type impurities such as N (nitrogen), P (phosphorus), As (arsenic), Al (aluminum), B A p-type impurity such as (boron) can be used. Further, the thickness of the polysilicon layer 147 is, for example, 5000 mm to 10,000 mm.
- the polysilicon layer 147 is formed so as to cover the entire surface of the cell 113 exposed in the contact holes 144 and 145, and the Schottky region 131 and the HD breakdown voltage are formed in the HD source trench 126. All of the holding region 127 and the source region 117 are in contact with all of the bottom channel contact region 138, the Di withstand voltage holding region 134 and the source region 117 in the Di source trench 133.
- the polysilicon layer 147 forms a Schottky junction with the source region 117 in the Schottky cell 114.
- the polysilicon layer 147 is formed between the Schottky region 131 and the body diode 150 (the pn junction between the channel region 118 and the drain region 119) incorporated in the Schottky cell 114 and the pn diode cell 115, respectively.
- the heterojunction for example, the height of the junction barrier is 1 eV to 1.5 eV
- having a junction barrier smaller than the diffusion potential (for example, 2.8 eV to 3.2 eV) of the diode is formed.
- a heterojunction diode 151 (HD) is formed between the source electrode 146 and the Schottky region 131.
- the polysilicon layer 147 forms an ohmic contact between the bottom channel contact region 138 and the source region 117 in the pn diode cell 115.
- the intermediate layer 148 is a metal layer 149 laminated on the polysilicon layer 147, and is composed of a single layer containing Ti (titanium) or a plurality of layers including a layer containing Ti.
- the layer containing Ti can be formed using Ti, TiN (titanium nitride), or the like. Further, the thickness of the intermediate layer 148 is, for example, 200 nm to 500 nm.
- the metal layer 149 is laminated on the intermediate layer 148 and contains, for example, Al (aluminum), Au (gold), Ag (silver), Cu (copper), Mo (molybdenum), alloys thereof, and the like. It can be formed using a metal material.
- the metal layer 149 is the outermost layer of the source electrode 146.
- the thickness of the metal layer 149 is, for example, 1 ⁇ m to 5 ⁇ m.
- polysilicon polysilicon layer 147
- Ti intermediate layer 148
- TiN intermediate layer 1448
- It is a laminated structure (polysilicon / Ti / TiN / Al) in which Al (metal layer 149) is sequentially laminated.
- the metal layer 149 preferably has a Mo layer. Since Mo has a high melting point, if the Mo layer is included in the metal layer 149, the metal layer 149 can be prevented from being melted by heat generated when a large current flows through the source electrode 146.
- a drain electrode 152 is formed on the back surface 107 of the substrate 105 so as to cover the entire area.
- the drain electrode 152 is a common electrode for all the cells 113.
- As the drain electrode 152 for example, a stacked structure (Ti / Ni / Au / Ag) in which Ti, Ni, Au, and Ag are stacked in this order from the substrate 105 side can be applied.
- 11A to 11F are schematic cross-sectional views showing a part of the manufacturing process of the trench gate type MIS transistor 101 in FIG.
- an n-type impurity for example, N () is formed on the surface 106 (Si surface) of the substrate 105 by an epitaxial growth method such as a CVD method, an LPE method, or an MBE method. SiC crystal is grown while doping nitrogen), P (phosphorus), As (arsenic) and the like. As a result, an n ⁇ -type epitaxial layer 108 is formed on the substrate 105.
- p-type impurities for example, Al (aluminum), B (boron), etc.
- n-type impurities are implanted (implanted) from the surface 109 of the epitaxial layer 108 into the epitaxial layer 108.
- the epitaxial layer 108 is heat-treated at, for example, 1400 ° C. to 2000 ° C.
- ions of the p-type impurity and the n-type impurity implanted into the surface layer portion of the epitaxial layer 108 are activated, and the channel region 118, the source region 117, and the guard ring 142 are simultaneously formed according to the implanted locations.
- a drain region 119 that maintains the state after epitaxial growth is formed in the base layer portion of the epitaxial layer 108.
- the epitaxial layer 108 is etched using a mask having openings in regions where the gate trench 112, the HD source trench 126 and the Di source trench 133 are to be formed. Thereby, the epitaxial layer 108 is dry-etched from the surface 109 (Si surface), and the gate trench 112, the HD source trench 126, and the Di source trench 133 are formed simultaneously. At the same time, a large number of cells 113 partitioned by the gate trench 112 are formed in the epitaxial layer 108.
- the etching gas includes, for example, a mixed gas (SF 6 / O 2 gas) containing SF 6 (sulfur hexafluoride) and O 2 (oxygen), SF 6 , O 2, and HBr (hydrogen bromide).
- SF 6 / O 2 gas a mixed gas containing SF 6 (sulfur hexafluoride) and O 2 (oxygen), SF 6 , O 2, and HBr (hydrogen bromide).
- a mixed gas SF 6 / O 2 / HBr gas
- a resist 153 in which an opening for exposing the intersection 121 of the gate trench 112, the edge 130 of the HD source trench 126, and the bottom surface 135 and the edge 137 of the Di source trench 133 is formed. , Formed on the epitaxial layer 108. Subsequently, p-type impurities are implanted (implanted) toward the intersection 121 of the gate trench 112 exposed from the opening of the resist 153, the HD source trench 126, and the Di source trench 133. At this time, the side surface 124 of the gate trench 112 (intersection 121), the side surface 129 of the HD source trench 126, and the side surface 136 of the Di source trench 133 are not covered with the resist 153.
- the epitaxial layer 108 is heat-treated at, for example, 1400 ° C. to 2000 ° C.
- ions of the p-type impurity implanted into the drain region 119 are activated, and the G breakdown voltage holding region 140, the HD breakdown voltage holding region 127, and the Di breakdown voltage holding region 134 are formed simultaneously.
- a Schottky region 131 is formed in the portion covered with the resist 153 on the bottom surface 128 of the HD source trench 126.
- a resist 154 having an opening in a region where the bottom channel contact region 138 of the Di source trench 133 is to be formed is formed on the epitaxial layer 108.
- p-type impurities are implanted (implanted) toward the center of the bottom 135 of the Di source trench 133 exposed from the opening of the resist 154 (Di breakdown voltage holding region 134).
- the epitaxial layer 108 is heat-treated at, for example, 1400 ° C. to 2000 ° C.
- ions of the p-type impurity implanted into the Di breakdown voltage holding region 134 are activated, and the bottom channel contact region 138 is formed.
- a SiO 2 material is deposited from above the epitaxial layer 108 by CVD. Thereby, the gate insulating film 122 is formed.
- a doped polysilicon material is deposited from above the epitaxial layer 108 by CVD. After deposition, the polysilicon material is etched back until the etch back surface is flush with the surface 109 of the epitaxial layer 108. Subsequently, only the polysilicon material remaining in the HD source trench 126 and the Di source trench 133 is removed by dry etching. As a result, the gate electrode 125 made of the polysilicon material remaining in the gate trench 112 is formed.
- a SiO 2 material is deposited from above the epitaxial layer 108 by CVD. Thereby, an interlayer insulating film 143 is formed. Subsequently, the interlayer insulating film 143 and the gate insulating film 122 are successively patterned by a known patterning technique. As a result, contact holes 144 and 145 are formed in the interlayer insulating film 143 and the gate insulating film 122.
- a polysilicon material is deposited by CVD until the contact holes 144 and 145 are filled. Thereafter, n-type or p-type impurities are implanted into the deposited polysilicon material.
- the implantation conditions at this time vary depending on the type of impurities, but the acceleration energy is, for example, 10 keV to 100 keV. Thereby, the polysilicon layer 147 is formed.
- the MIS transistor 101 of FIG. 10 is obtained by forming the intermediate layer 148, the metal layer 149, the drain electrode 152, and the like.
- the MIS transistor 101 is used as a switching element of a drive circuit (inverter circuit) of an electric motor (an example of an inductive load), for example.
- a predetermined voltage gate threshold voltage
- a drain voltage having a positive drain side applied between the source pad 102 (source electrode 146) and the drain electrode 152 (between the source and drain).
- the gate trench 112 near the n-type drain region 119 (for example, the gate trench 112).
- the SiC crystal defects in the epitaxial layer 108 may expand in a direction parallel to the stacking direction of the epitaxial layer 108 due to the energy generated by the coupling, and may reach a drain current path (for example, a channel) when turned on. .
- this MIS transistor 101 performs a switching operation by forming a channel in the vicinity of the side surface 124 of the gate trench 112 in the channel region 118, the on-resistance may increase.
- the polysilicon layer 147 forms a heterojunction with the drain region 119 (Schottky region 131), and the heterojunction diode 151 is incorporated. Therefore, current flows preferentially through the heterojunction diode 151, and the current flowing through the body diode 150 can be reduced or eliminated.
- the current flowing through the MIS transistor 101 in this way can be passed to the electric motor as a return current, for example.
- the off-state current flows to the heterojunction diode 151 formed in the HD source trench 126 in the center of the Schottky cell 114, so that it is near the gate trench 112 (that is, the p-type channel region 118 and the n-type drain). There is almost no carrier movement between the region 119). Therefore, recombination of holes and electrons in the drain region 119 can be prevented. As a result, expansion of SiC crystal defects in the epitaxial layer 108 can be suppressed, so that an increase in on-resistance of the transistor can be suppressed. In addition, since the current flowing through the body diode 150 can be reduced or eliminated, loss when the MIS transistor 101 operates can be reduced.
- the length L 1 of one side of the Schottky region 131 constituting the heterojunction diode 151 is set so that the depletion layer generated from the body diode 132 is not connected. Therefore, when the heterojunction diode 151 operates, it is possible to prevent the current path from being closed by the depletion layer. As a result, low on-resistance of the heterojunction diode 151 can be achieved.
- an electric field is applied to the gate insulating film 122 interposed between the gate electrode 125 and the epitaxial layer 108. This electric field is generated due to a potential difference between the gate electrode 125 and the epitaxial layer 108.
- equipotential surfaces with a very high potential are distributed with the gate electrode 125 as a reference (0 V), and the interval between the equipotential surfaces is small, so a very large electric field is generated.
- an equipotential surface of 900 V is distributed in the vicinity of the back surface 107 of the substrate 105 in contact with the drain electrode 152, and the voltage increases from the back surface 107 of the substrate 105 toward the surface 109 side of the epitaxial layer 108.
- an equipotential surface of about several tens of volts is distributed near the bottom surface 123 of the gate trench 112. Therefore, a very large electric field is generated on the bottom surface 123 of the gate trench 112 toward the gate electrode 125 side.
- each corner of the cell 113 is displayed.
- the dielectric breakdown of the gate insulating film 122 is particularly likely to occur.
- the G breakdown voltage holding region 140 is formed in the corner edge portion 141 of the gate trench 112.
- the body diode 155 can be formed in the vicinity of the corner edge portion 141 of the gate trench 112 by the pn junction between the G breakdown voltage holding region 140 and the drain region 119.
- an HD breakdown voltage holding region 127 is formed at the edge portion 130 of the HD source trench 126 of the Schottky cell 114, and the Di breakdown voltage is held at the bottom surface 135 of the Di source trench 133 and the edge portion 137 of the pn diode cell 115. Region 134 is formed.
- an annular body diode 132 surrounding the edge portion 130 of the HD source trench 126 is formed by the pn junction between the HD breakdown voltage holding region 127 and the drain region 119 and the pn junction between the Di breakdown voltage holding region 134 and the drain region 119. be able to.
- a vessel-shaped body diode 139 covering the bottom of the Di source trench 133 can be formed.
- FIG. 12 is a schematic cross-sectional view of a trench gate type MIS transistor 161 according to the fourth embodiment of the present invention, and shows a cut surface at the same position as FIG.
- parts corresponding to the parts shown in FIG. 10 are given the same reference numerals as those given to the respective parts, and description of those parts is omitted.
- the HD source trench 126 has a planar shape with no step formed on its side surface.
- the HD source trench 162 of the MIS transistor 161 according to the fourth embodiment is epitaxial.
- HD upper layer trench 163 (second upper layer trench) having a depth from surface 109 of channel 108 to channel region 118 and HD lower layer having a width narrower than HD upper layer trench 163 and a depth from channel region 118 to drain region 119 Trench 164 (second lower layer trench).
- the HD source trench 162 has a two-stage structure in which the side surface of the HD upper layer trench 163 extends one step outward from the side surface of the HD lower layer trench 164.
- a channel region 118 is exposed in a ring shape at a step portion between the HD upper trench 163 and the HD lower trench 164, and a p + type HD channel contact region 165 is formed in the exposed portion.
- the Di source trench 166 of the MIS transistor 161 is narrower in width than the Di upper layer trench 167 (first upper layer trench) having a depth from the surface 109 of the epitaxial layer 108 to the channel region 118, and the Di upper layer trench 167.
- Di lower trench 168 (first lower trench) having a depth from channel region 118 to drain region 119 is included. Accordingly, the Di source trench 166 has a two-stage structure in which the side surface of the Di upper layer trench 167 extends one step outward from the side surface of the Di lower layer trench 168.
- a channel region 118 is exposed in a ring shape at a step portion between the Di upper trench 167 and the Di lower trench 168, and a p + -type Di channel contact region 169 is formed in the exposed portion.
- 13A to 13G are schematic cross-sectional views showing a part of the manufacturing process of the trench gate type MIS transistor 161 in FIG. 12 in the order of steps, and show a cut surface at the same position as FIG.
- the n ⁇ type epitaxial layer 108 is formed on the substrate 105 as shown in FIG. 13A by the same method as FIG. A source region 117, a drain region 119, and a guard ring 142 are formed at the same time.
- the epitaxial layer 108 is etched using a mask having openings in regions where the HD upper trench 163 and the Di upper trench 167 are to be formed. Thereby, the epitaxial layer 108 is dry-etched from the surface 109 (Si surface), and the HD upper layer trench 163 and the Di upper layer trench 167 are simultaneously formed.
- a resist 170 in which an opening exposing the entire bottom surface of the HD upper layer trench 163 and the Di upper layer trench 167 is formed on the epitaxial layer 108.
- p-type impurities are implanted (implanted) toward the HD upper layer trench 163 and the Di upper layer trench 167 exposed from the opening of the resist 170.
- the epitaxial layer 108 is heat-treated at, for example, 1400 ° C. to 2000 ° C. Thereby, ions of the p-type impurity implanted into the channel region 118 through the HD upper layer trench 163 and the Di upper layer trench 167 are activated, and the HD channel contact region 165 and the Di channel contact region 169 are formed simultaneously.
- the epitaxial layer 108 is etched using a mask having openings in regions where the gate trench 112, the HD lower trench 164 and the Di lower trench 168 are to be formed. Thereby, the epitaxial layer 108 is dry-etched from the bottom surfaces of the HD upper trench 163 and the Di upper trench 167, and the HD lower trench 164 and the Di lower trench 168 are simultaneously formed. At the same time, the epitaxial layer 108 is dry-etched from the surface 109 to form the gate trench 112.
- a resist 171 in which an opening exposing the edge portion 130 of the HD source trench 162 and the bottom surface 135 and the edge portion 137 of the Di source trench 166 is formed on the epitaxial layer 108.
- p-type impurities are implanted (implanted) toward the HD source trench 162 and the Di source trench 166 exposed from the opening of the resist 171.
- the epitaxial layer 108 is heat-treated at, for example, 1400 ° C. to 2000 ° C.
- ions of the p-type impurity implanted in the drain region 119 are activated, and the HD breakdown voltage holding region 127 and the Di breakdown voltage holding region 134 are formed simultaneously.
- a Schottky region 131 is formed in the portion of the bottom surface 128 of the HD source trench 162 covered with the resist 171.
- a SiO 2 material is deposited from above the epitaxial layer 108 by CVD. Thereby, the gate insulating film 122 is formed. Thereafter, a gate electrode 125 is formed inside the gate insulating film 122 by a method similar to that shown in FIG. 11E.
- the interlayer insulating film 143 is formed by the same method as in FIG. 11F, the polysilicon layer 147 is formed. Thereafter, the intermediate layer 148, the metal layer 149, the drain electrode 152, and the like are formed, whereby the MIS transistor 161 of FIG. 12 is obtained.
- this MIS transistor 161 can achieve the same function and effect as those of the MIS transistor 101 described above. Further, in this MIS transistor 161, each of the trenches 162 and 166 has a two-stage structure, and the HD channel contact region 165 and the Di channel contact region 169 are formed. Therefore, each channel of the Schottky cell 114 and the pn diode cell 115 is provided. Direct contact can be made to region 118. As a result, the potential of the channel region 118 can be precisely controlled.
- FIGS. 14A and 14B are schematic plan views of a planar gate type MIS transistor 181 according to the fifth embodiment of the present invention.
- FIG. 14A is an overall view, and FIG. Each internal enlarged view is shown.
- FIG. 15 is a cross-sectional view of the planar gate type MIS transistor 181 shown in FIGS. 14A and 14B, and shows cross sections taken along the cutting lines HH and II shown in FIG. 14B.
- parts corresponding to the parts shown in FIGS. 9 and 10 are denoted by the same reference numerals as those given to the respective parts, and description thereof will be omitted.
- the present invention is not limited to a planar gate type transistor like the MIS transistor 181 according to the fifth embodiment. Can also be adopted.
- the gate insulating film 182 is formed on the surface 109 of the epitaxial layer 108 instead of being formed on the inner surface of the gate trench 112, and the gate electrode 183 is formed thereon.
- FIGS. 16A and 16B are schematic plan views of a trench gate type MIS transistor 191 according to the sixth embodiment of the present invention.
- FIG. 16A is an overall view, and FIG. Each internal enlarged view is shown.
- FIG. 17 is a cross-sectional view of the trench gate type MIS transistor 191 shown in FIGS. 16A and 16B, and shows cross sections taken along the cutting lines JJ and KK of FIG. 16 and FIG. 17, parts corresponding to the parts shown in FIG. 9 and FIG. 10 are given the same reference numerals as those given to the respective parts, and the description of those parts is omitted.
- the Schottky cell 114 has an area larger than that of the pn diode cell 115.
- the area of the Schottky cell 114 and the pn diode cell 115 may be the same.
- Schottky cells 114 and pn diode cells 115 having a square shape in plan view and having the same size are arranged in a matrix (matrix shape), and the Schottky cell 114 is a pn diode. It is surrounded by the cell 115.
- the MIS transistor 101 structure having the source region 117, the channel region 118, and the drain region 119 and having the HD source trench 126 formed therein is not formed.
- the Schottky region 131 appears on the same plane as the surface 109 of the epitaxial layer 108.
- this MIS transistor 191 can also achieve the same effects as those of the MIS transistor 101 described above.
- the MIS transistor 191 does not require a space for forming the MIS transistor structure, the Schottky region 131 having a sufficient area can be exposed even if the cell 113 is not large. Low resistance can be achieved.
- this invention can also be implemented with another form.
- the source electrodes 37 and 87 do not need to have a laminated structure of polysilicon layers 38 and 88, intermediate layers 39 and 89, and metal layers 40 and 90, and may be formed of only a metal layer, for example.
- the material of the metal layer is preferably made of one selected from the group consisting of Ni, Ti, Al, and Mo, for example.
- a configuration in which the conductivity type of each semiconductor portion of MIS transistors 1, 47, 51, 97, 101, 161, 181, 191 is inverted may be employed.
- the p-type portion may be n-type and the n-type portion may be p-type.
- Each unit cell 21 is not limited to a rectangular parallelepiped shape (quadrangular columnar shape), and may be other polygonal columnar shapes such as a triangular prism shape, a pentagonal column shape, and a hexagonal column shape.
- Each unit cell 71 is not limited to a square (square shape) in plan view, and may be other polygonal shapes in plan view such as a triangle in plan view, a pentagon in plan view, and a hexagon in plan view.
- each cell 113 is not limited to a square (rectangular shape) in plan view, and may be, for example, another plan view polygonal shape such as a plan view triangle, a plan view pentagon, a plan view hexagon, and a stripe shape. .
- the Schottky cell 114 has an area corresponding to, for example, nine of the pn diode cells 115, and the length of one side of the Schottky cell 114. May correspond to three times the length of one side of the pn diode cell 115.
- the source electrode 146 for example, the polysilicon layer 147 and the intermediate layer 148 are omitted, and a single layer structure of the metal layer 149 can be used to form a Schottky junction with the Schottky region 131.
- a Schottky barrier diode can be formed instead of the heterojunction diode 151.
- the semiconductor power device of the present invention is, for example, a power used for an inverter circuit constituting a drive circuit for driving an electric motor used as a power source for an electric vehicle (including a hybrid vehicle), a train, an industrial robot, and the like. Can be incorporated into modules. It can also be incorporated into a power module used in an inverter circuit that converts electric power generated by a solar cell, wind power generator, or other power generation device (especially an in-house power generation device) to match the power of a commercial power source.
- first 2 areas 31 ... (gate train Corner edge portion, 32... (Source trench) edge portion, 33... Drain exposed region, 37... Source electrode, 38... Polysilicon layer, 41. First part, 42 ... second part (of polysilicon layer), 43 ... body diode, 47 ... MIS transistor, 51 ... MIS transistor, 55 ... substrate, 58 ... Epitaxial layer, 59... (Epitaxial layer) surface, 62... Channel region, 63... Drain region, 64... Source region, 65. Linear portion of the inter-region, 67... Crossing of the inter-channel region, 70... Corner of the unit cell, 71... Unit cell, 72. ..Gate electrodes, 74 Source trench, 75 ... (source trench) side surface, 76 ...
Abstract
Description
SiCパワーデバイスは、たとえば、モータ制御システム、電力変換システムなどに組み込まれる各種インバータ回路のスイッチング素子として利用される。
具体的には、デバイスに内在するp型チャネル領域とn型ドレイン領域とのpn接合による寄生ダイオード(ボディダイオード)の整流作用により、逆起電力に起因する電流を還流電流としてモータコイルに流すことで、高い逆起電力がスイッチング素子に印加されることを防止している。
本発明の目的は、オン抵抗の上昇を抑制することができ、さらに耐圧を向上させることができる半導体装置を提供することである。
このような場合に、障壁形成層とドレイン領域との接合部に優先的に電流が流れ、ボディダイオードに流れる電流を少なくするか、またはなくすことができる。こうして半導体装置を流れた電流は、たとえば、還流電流として負荷に流すことができる。
具体的には、半導体装置がオフの状態(つまり、ゲート電圧が0Vの状態)において、ソース領域と、ドレインとして機能するドレイン領域との間(ソース-ドレイン間)にドレイン領域が(+)側となる電圧が印加されると、ゲート電極とドレイン領域との間に介在するゲート絶縁膜に電界がかかる。この電界は、ゲート電極とドレイン領域との電位差に起因して生じるものである。そして、ゲートトレンチの底部においては、ゲート電極を基準(0V)として非常に高い電位の等電位面が分布し、しかも等電位面の間隔が小さいため、非常に大きな電界が生じる。そのため、デバイス耐圧ほどの電圧がソース-ドレイン間に印加され続けると、ゲート絶縁膜におけるゲートトレンチの底部上の箇所が、その大きさの電界集中に耐え切れず、絶縁破壊を起こすといったメカニズムである。
ゲートトレンチが格子状に形成されており、当該格子状のゲートトレンチの窓部に多角柱状の単位セルが配列されている場合は、単位セルの角部に形成されたゲートトレンチのコーナーエッジ部付近において、ゲート絶縁膜の絶縁破壊が特に発生しやすい。したがって、第2耐圧保持領域がコーナーエッジ部に形成されていれば、そのコーナーエッジ部付近におけるゲート絶縁膜の絶縁破壊を効果的に抑制することができる。
多角柱状の単位セルでは、ゲート電極に印加する電圧を制御することにより、ゲートトレンチの側面の一部を形成する単位セルの側面に沿ってチャネルが形成される。すなわち、単位セルの角部には、チャネルが形成されないか、形成されても当該チャネルを流れる電流は微量である。したがって、チャネル領域におけるコーナーエッジ部直上の部分に至るように第2耐圧保持領域を形成することにより、デバイスの性能にほとんど影響を与えずに、ゲート絶縁膜の破壊防止効果を一層向上させることができる。
また、前記半導体層は、格子状の前記ゲートトレンチの線状部の底面に形成され、当該線状部の幅よりも狭い幅を有する第2導電型の第3耐圧保持領域をさらに含むことが好ましい。
しかも、第3耐圧保持領域がゲートトレンチの線状部の側面(つまり、単位セルにおいてチャネルが形成される部分)に形成されていないので、デバイスの性能の低下を防止することもできる。
この構成により、チャネル抵抗の上昇を抑制することができる。なお、第2および第3耐圧保持領域の厚さとは、たとえば、前記半導体層の前記表面から前記裏面側に向かう方向に沿う厚さのことである。
チャネル領域がマトリクス状に形成されているプレーナゲート型MISトランジスタでは、チャネル間領域のコーナー部付近において、ゲート絶縁膜の絶縁破壊が特に発生しやすい。したがって、第4耐圧保持領域がチャネル間領域のコーナー部に形成されていれば、そのコーナー部付近におけるゲート絶縁膜の絶縁破壊を効果的に抑制することができる。
この構成により、チャネル間領域の線状部に沿って生じる電界がゲート絶縁膜に作用しても、第5耐圧保持領域とドレイン領域との接合(pn接合)により生じる空乏層により、当該電界を緩和することができる。その結果、ゲート絶縁膜に生じる電界を、満遍なく緩和することができる。
また、前記ドレイン領域は、前記ソーストレンチの前記底面が選択的に前記半導体層の前記表面側に突出することにより形成された段部を有していることが好ましい。
また、本発明の他の局面に係る半導体装置は、ワイドバンドギャップ半導体からなる半導体層と、前記半導体層に形成され、前記半導体層を複数のセルに区画するゲート部とを含み、前記セルは、前記半導体層の表面側から裏面側へ向かってこの順に配置された第1導電型のソース領域、第2導電型のチャネル領域および第1導電型のドレイン領域を有し、前記半導体層の前記表面から前記ソース領域および前記チャネル領域を貫通して最深部が前記ドレイン領域に達する第1ソーストレンチが形成された第1MISトランジスタ構造と、前記第1ソーストレンチの内面に選択的に形成された第2導電型の第1耐圧保持領域を有し、当該第1耐圧保持領域と前記ドレイン領域とのpn接合により構成されたpnダイオードとを含むpnダイオードセルと、前記ドレイン領域と一体な第1導電型のショットキー領域が選択的に露出したショットキーセルとを含み、前記pnダイオードセルおよび前記ショットキーセルに跨って形成され、前記ソース領域に対してオーミック接触を形成し、前記ショットキー領域に対して、前記チャネル領域と前記ドレイン領域とのpn接合により形成されるボディダイオードの拡散電位よりも低いショットキー障壁を形成するソース電極をさらに含む。
このような場合に、ショットキー領域とソース電極との接合部(ショットキーバリアダイオード)に優先的に電流が流れ、ボディダイオードに流れる電流を少なくするか、またはなくすことができる。こうして半導体装置を流れた電流は、たとえば、還流電流として負荷に流すことができる。
つまり、本発明の他の局面に係る半導体装置においてソース電極は、ショットキー領域との間にショットキー障壁を形成してショットキーバリアダイオードを形成する金属電極、半導体層のバンドギャップとは異なるバンドギャップを有する異種半導体からなり、ショットキー領域に対してヘテロ接合(バンドギャップ差を利用してショットキー領域との間に電位障壁を形成する接合)してヘテロ接合ダイオードを形成する半導体電極のいずれをも含む概念である。また、ショットキー領域とは、ソース電極との間にヘテロ接合を形成する領域も含む概念である。
また、本発明の他の局面に係る半導体装置では、前記pnダイオードセルにおいて前記第1耐圧保持領域は、前記第1ソーストレンチの底面から前記ソーストレンチの側面に沿って前記チャネル領域に至るように形成されており、前記pnダイオードセルは、前記第1ソーストレンチの前記底面に形成され、前記第1耐圧保持領域よりも不純物濃度が高い第2導電型のチャネルコンタクト領域をさらに含むことが好ましい。
また、本発明の他の局面に係る半導体装置では、前記pnダイオードセルにおいて前記第1ソーストレンチは、前記半導体層の前記表面から前記チャネル領域までの深さの第1上層トレンチと、前記第1上層トレンチよりも幅が狭く、前記チャネル領域から前記ドレイン領域までの深さの第1下層トレンチとを含む2段構造を有しており、前記pnダイオードセルは、前記第1上層トレンチと前記第1下層トレンチとの段差部分に露出する前記チャネル領域に形成され、前記チャネル領域よりも不純物濃度が高い第2導電型のチャネルコンタクト領域をさらに含むことが好ましい。
また、本発明の他の局面に係る半導体装置では、前記ショットキーセルは、前記半導体層の表面側から裏面側へ向かってこの順に配置された第1導電型のソース領域、第2導電型のチャネル領域および第1導電型のドレイン領域を有し、前記半導体層の前記表面から前記ソース領域および前記チャネル領域を貫通して前記ドレイン領域に達する第2ソーストレンチが形成された第2MISトランジスタ構造と、前記第2ソーストレンチの側面と底面とが交わって形成された前記第2ソーストレンチのエッジ部に選択的に形成された第2耐圧保持領域とをさらに含み、前記ショットキー領域は、前記第2耐圧保持領域で取り囲まれた前記第2ソーストレンチの底面に形成されていることが好ましい。
この構成によれば、ショットキーバリアダイオード(ヘテロ接合ダイオード)が動作するときに、その電流路が当該空乏層で閉じられることを防止することができる。その結果、ショットキーバリアダイオード(ヘテロ接合ダイオード)の低オン抵抗化を達成することができる。
また、本発明の他の局面に係る半導体装置では、前記ゲート部は、前記半導体層に形成されたゲートトレンチと、前記ゲートトレンチの内面に形成されたゲート絶縁膜と、前記ゲートトレンチにおいて前記ゲート絶縁膜の内側に形成されたゲート電極とを含んでいてもよいし、前記半導体層上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極と含んでいてもよい。
この構成によれば、中継領域を介してショットキーセルのチャネル領域にコンタクトをとることができる。
また、前記ゲート部が、前記pnダイオードセルを互いに同じ大きさで行列状に配列させる格子状に形成されている場合、前記ショットキーセルは、前記pnダイオードセル4つ分または9つ分に相当する面積を有していることが好ましい。
<第1実施形態>
図1(a)(b)は、本発明の第1実施形態に係るトレンチゲート型MISトランジスタの模式的な平面図であって、図1(a)は全体図、図1(b)は内部拡大図をそれぞれ示す。図2は、図1(a)(b)に示すトレンチゲート型MISトランジスタの断面図であって、図1(b)の切断線A-AおよびB-Bでの切断面をそれぞれ示す。
次に、MISトランジスタ1の内部構造について説明する。
MISトランジスタ1は、n+型(たとえば、濃度が1×1018~1×1021cm-3)のSiCからなる基板5を備えている。基板5は、第1実施形態では、MISトランジスタ1のドレインとして機能し、その表面6(上面)がSi面であり、その裏面7(下面)がC面である。
活性領域10において、エピタキシャル層8の表層部には、p型(たとえば、濃度が1.0×1016cm-3~1.0×1019cm-3)のチャネル領域12が、行方向および列方向に一定のピッチで行列状(マトリクス状)に配列されて多数形成されている。各チャネル領域12は、平面視正方形状であり、たとえば、図1(b)の紙面における上下左右方向の長さがそれぞれ7.2μm程度である。
各チャネル領域12には、その表面9側のほぼ全域にn+型(たとえば、濃度が1×1018~1×1021cm-3)のソース領域14が形成されている。
具体的には、ゲートトレンチ15は、隣り合うチャネル領域12の各間を、各チャネル領域12の4つの側面に沿って行方向および列方向のそれぞれに直線状に延びる線状部16と、行方向に延びる線状部16と列方向に延びる線状部16とが交差する交差部17とを含んでいる。交差部17は、平面視で2行2列に配列されたチャネル領域12に着目したとき、配列された4つのチャネル領域12の内側の角に取り囲まれ、チャネル領域12の四辺の延長線により区画される平面視正方形状の部分である。また、ゲートトレンチ15は、互いに対向する側面18と底面19とが湾曲面を介して連続する断面U字状である。
ゲートトレンチ15の内面には、その全域を覆うように、SiO2からなるゲート絶縁膜22が形成されている。
ゲート耐圧保持領域27は、格子状のゲートトレンチ15に沿って形成されており、ゲートトレンチ15の交差部17に形成された第2耐圧保持領域としての第1領域29と、ゲートトレンチ15の線状部16に形成された第3耐圧保持領域としての第2領域30とを一体的に含んでいる。
これにより、ソーストレンチ24の底面26の中央部には、ドレイン領域13の一部からなる平面視正方形状のドレイン露出領域33が形成されている。
また、トランジスタ周辺領域11において、エピタキシャル層8の表層部には、マトリクス状に配列された単位セル21(活性領域10)を取り囲むように、活性領域10から間隔を開けてp型のガードリング34が複数本(第1実施形態では、4本)形成されている。これらのガードリング34は、p型のチャネル領域12を形成する工程と同一のイオン注入工程で形成することができる。
エピタキシャル層8上には、ゲート電極23を被覆するように、SiO2からなる層間絶縁膜35が積層されている。
層間絶縁膜35およびゲート絶縁膜22には、ソーストレンチ24よりも大径のコンタクトホール36が形成されている。これにより、コンタクトホール36内には、各単位セル21のソーストレンチ24の全体(すなわち、ソーストレンチ24の側面25および底面26)およびエピタキシャル層8の表面9におけるソーストレンチ24の周縁部が露出していて、表面9と底面26との高低差に応じた段差が形成されている。
ポリシリコン層38は、不純物がドーピングされたドープトポリシリコンを用いて形成されたドープ層であり、たとえば、1×1015cm-3以上、好ましくは、1×1019~1×1021cm-3の高濃度で不純物がドーピングされた高濃度ドープ層である。ポリシリコン層38をドープ層(高濃度ドープ層を含む)として形成するときの不純物としては、N(窒素)、P(リン)、As(ひ素)などのn型不純物、Al(アルミニウム)、B(ホウ素)などのp型不純物を用いることができる。また、ポリシリコン層38の厚さは、たとえば、5000Å~10000Åである。
すなわち、ポリシリコン層38は、ソーストレンチ24の側面25においてソース耐圧保持領域28に接し、側面25およびエピタキシャル層8の表面9におけるソーストレンチ24の周縁部においてソース領域14に接する第1部分41と、ソーストレンチ24の底面26においてドレイン露出領域33に接する第2部分42とを有している。
メタル層40は、中間層39上に積層されており、たとえば、Al(アルミニウム)、Au(金)、Ag(銀)、Cu(銅)、Mo(モリブデン)、それらの合金およびそれらを含有するメタル材料を用いて形成することができる。メタル層40は、ソース電極37の最表層をなしている。また、メタル層40の厚さは、たとえば、1μm~5μmである。
図3A~図3Fは、図2に示すトレンチゲート型MISトランジスタの製造工程の一部を示す模式的な断面図であって、図2と同じ位置での切断面を示す。
続いて、n型不純物が、エピタキシャル層8の表面9からエピタキシャル層8の内部にインプランテーション(注入)される。
続いて、第2レジスト46の開口から露出するゲートトレンチ15の線状部16へ向けて、p型不純物がインプランテーション(注入)される。この際、側面18および底面19、ならびに側面25および底面26は第2レジスト46で保護されるので、これらの部分へのp型不純物の注入を防止することができる。その後、たとえば、1400℃~2000℃でエピタキシャル層8が熱処理される。これにより、ドレイン領域13に注入されたp型不純物のイオンが活性化され、ゲート耐圧保持領域27の第2領域30が形成される。
続いて、CVD法により、ドーピングされたポリシリコン材料がエピタキシャル層8の上方から堆積される。ポリシリコン材料の堆積は、少なくともゲートトレンチ15およびソーストレンチ24が埋め尽くされるまで続けられる。その後、堆積したポリシリコン材料が、エッチバック面がエピタキシャル層8の表面9に対して面一になるまでエッチバックされる。続いて、ソーストレンチ24内に残存するポリシリコン材料のみがドライエッチングにより除去される。これにより、ゲートトレンチ15内に残存するポリシリコン材料からなるゲート電極23が形成される。
この後、中間層39、メタル層40、ドレイン電極44などが形成されることにより、図2に示すMISトランジスタ1が得られる。
このような場合に、ボディダイオード43の整流作用により、電流が、たとえば還流電流としてモータコイルに流れると、以下の不具合がある。
この電界は、ゲート電極23とエピタキシャル層8との電位差に起因して生じるものである。そして、ゲートトレンチ15の底面19においては、ゲート電極23を基準(0V)として非常に高い電位の等電位面が分布し、しかも等電位面の間隔が小さいため、非常に大きな電界が生じる。たとえば、ドレイン電圧が900Vであれば、ドレイン電極44に接する基板5の裏面7付近では900Vの等電位面が分布しており、基板5の裏面7からエピタキシャル層8の表面9側へ向かうにつれて電圧降下を生じるが、ゲートトレンチ15の底面19付近では、数十V程度の等電位面が分布する。そのため、ゲートトレンチ15の底面19では、ゲート電極23側へ向かう非常に大きな電界が生じる。とりわけ、第1実施形態のように、ゲートトレンチ15が格子状に形成されており、格子状のゲートトレンチ15の窓部に四角柱状の単位セル21が配列されている場合は、単位セル21の各角部20に形成されたゲートトレンチ15のコーナーエッジ部31付近において、ゲート絶縁膜22の絶縁破壊が特に発生しやすい。
また、第2領域30の濃度が第1領域29の濃度よりも高く、さらに、第2領域30の厚さT2が第1領域29の厚さT1よりも小さい(T1>T2)ので、チャネル抵抗の上昇を防止することもできる。
なお、ドレイン露出領域33は、図4のMISトランジスタ47のように、ソーストレンチ24の底面26の中央部をエピタキシャル層8の表面9と面一になる位置まで突出させることにより、底面26の周縁部(中央部とは異なる他の部分)との間に段差S1を有していてもよい。このような構成は、たとえば、図3Bに示す工程において、ソーストレンチ24を環状に形成することにより得ることができる。
<第2実施形態>
図5(a)(b)は、本発明の第2実施形態に係るプレーナゲート型MISトランジスタの模式的な平面図であって、図5(a)は全体図、図5(b)は内部拡大図をそれぞれ示す。図6は、図5(a)(b)に示すプレーナゲート型MISトランジスタの断面図であって、図5(b)の切断線C-CおよびD-Dでの切断面をそれぞれ示す。
MISトランジスタ51の表面には、ソースパッド52が形成されている。ソースパッド52は、四隅が外方へ湾曲した平面視略正方形状であり、MISトランジスタ51の表面のほぼ全域を覆うように形成されている。このソースパッド52には、その一辺の中央付近に除去領域53が形成されている。この除去領域53は、ソースパッド52が形成されていない領域である。
次に、MISトランジスタ51の内部構造について説明する。
MISトランジスタ51は、n+型(たとえば、濃度が1×1018~1×1021cm-3)のSiCからなる基板55を備えている。基板55は、第2実施形態では、MISトランジスタ51のドレインとして機能し、その表面56(上面)がSi面であり、その裏面57(下面)がC面である。
活性領域60において、エピタキシャル層58の表層部には、p型(たとえば、濃度が1.0×1016cm-3~1.0×1019cm-3)のチャネル領域62が、行方向および列方向に一定のピッチで行列状(マトリクス状)に配列されて多数形成されている。各チャネル領域62は、平面視正方形状であり、たとえば、図5(b)の紙面における上下左右方向の長さがそれぞれ7.2μm程度である。
各チャネル領域62には、その表面59側のほぼ全域にn+型(たとえば、濃度が1×1018~1×1021cm-3)のソース領域64が形成されている。
具体的には、チャネル間領域65は、隣り合うチャネル領域62の各間を、各チャネル領域62の4つの側面に沿って行方向および列方向のそれぞれに直線状に延びる線状部66と、行方向に延びる線状部66と列方向に延びる線状部66とが交差する交差部67とを含んでいる。交差部67は、平面視で2行2列に配列されたチャネル領域62に着目したとき、配列された4つのチャネル領域62の内側の角に取り囲まれ、チャネル領域62の四辺の延長線により区画される平面視正方形状の部分である。
また、エピタキシャル層58には、エピタキシャル層58にp型不純物をインプランテーションすることにより形成された、p型のゲート耐圧保持領域77および第1耐圧保持領域としてのソース耐圧保持領域78が形成されている。
第1領域79は、交差部67に臨む4つの単位セル71の各角部70に形成されたチャネル領域62のコーナー部81に至るように形成されている。すなわち、第1領域79は、平面視では、チャネル間領域65の交差部67よりもやや大きい正方形状に形成されていて、その各角が、当該交差部67に臨む4つの単位セル71の各角部70にそれぞれ入り込んでいる。また、第1領域79の濃度は、チャネル領域62の濃度以上で、ドレイン領域63の濃度よりも高く、たとえば、1×1018~1×1019cm-3である。また、第1領域79におけるエピタキシャル層58の表面59から基板55へ向かう方向に沿う厚さT4は、たとえば、0.8μm程度である。
これにより、ソーストレンチ74の底面76の中央部には、ドレイン領域63の一部からなる平面視正方形状のドレイン露出領域83が形成されている。
エピタキシャル層58上には、ゲート電極73を被覆するように、SiO2からなる層間絶縁膜85が積層されている。
層間絶縁膜85およびゲート絶縁膜72には、ソーストレンチ74よりも大径のコンタクトホール86が形成されている。これにより、コンタクトホール86内には、各単位セル71のソーストレンチ74の全体(すなわち、ソーストレンチ74の側面75および底面76)およびエピタキシャル層58の表面59におけるソーストレンチ74の周縁部が露出していて、表面59と底面76との高低差に応じた段差が形成されている。
ポリシリコン層88は、不純物がドーピングされたドープトポリシリコンを用いて形成されたドープ層であり、たとえば、1×1015cm-3以上、好ましくは、1×1019~1×1021cm-3の高濃度で不純物がドーピングされた高濃度ドープ層である。ポリシリコン層88をドープ層(高濃度ドープ層を含む)として形成するときの不純物としては、N(窒素)、P(リン)、As(ひ素)などのn型不純物、Al(アルミニウム)、B(ホウ素)などのp型不純物を用いることができる。また、ポリシリコン層88の厚さは、たとえば、5000Å~10000Åである。
すなわち、ポリシリコン層88は、ソーストレンチ74の側面75においてソース耐圧保持領域78に接し、側面75およびエピタキシャル層58の表面59におけるソーストレンチ74の周縁部においてソース領域64に接する第1部分91と、ソーストレンチ74の底面76においてドレイン露出領域83に接する第2部分92とを有している。
メタル層90は、中間層89上に積層されており、たとえば、Al(アルミニウム)、Au(金)、Ag(銀)、Cu(銅)、Mo(モリブデン)、それらの合金およびそれらを含有するメタル材料を用いて形成することができる。メタル層90は、ソース電極87の最表層をなしている。また、メタル層90の厚さは、たとえば、1μm~5μmである。
図7A~図7Fは、図6に示すプレーナゲート型MISトランジスタの製造工程の一部を示す模式的な断面図であって、図6と同じ位置での切断面を示す。
続いて、n型不純物が、エピタキシャル層58の表面59からエピタキシャル層58の内部にインプランテーション(注入)される。
続いて、第2レジスト96の開口から露出するチャネル間領域65の線状部66へ向けて、p型不純物がインプランテーション(注入)される。この際、チャネル間領域65の交差部67、ならびに側面75および底面76は第2レジスト96で保護されるので、これらの部分へのp型不純物の注入を防止することができる。その後、たとえば、1400℃~2000℃でエピタキシャル層58が熱処理される。これにより、ドレイン領域63に注入されたp型不純物のイオンが活性化され、ゲート耐圧保持領域77の第2領域80が形成される。
続いて、CVD法により、ドーピングされたポリシリコン材料がエピタキシャル層58の上方から堆積される。その後、公知のパターニング技術により、堆積したポリシリコン材料がパターニングされることにより、ゲート電極73が形成される。
この後、中間層89、メタル層90、ドレイン電極94などが形成されることにより、図6に示すMISトランジスタ51が得られる。
すなわち、第2実施形態では、ポリシリコン層88がドレイン領域63(ドレイン露出領域83)に対してヘテロ接合を形成している。そのため、ソース-ドレイン間に逆起電力がかかった場合、ポリシリコン層88の第2部分92とドレイン領域63とのヘテロ接合部に優先的に電流が流れ、ボディダイオード93に流れる電流を少なくするか、またはなくすことができる。こうしてMISトランジスタ51を流れた電流は、たとえば還流電流として電動モータに流すことができる。
なお、ドレイン露出領域83は、図8のMISトランジスタ97のように、ソーストレンチ74の底面76の中央部をエピタキシャル層58の表面59と面一になる位置まで突出させることにより、底面76の周縁部(中央部とは異なる他の部分)との間に段差S2を有していてもよい。このような構成は、たとえば、図7Bに示す工程において、ソーストレンチ74を環状に形成することにより得ることができる。
<第3実施形態>
図9(a)(b)は、本発明の第3実施形態に係るトレンチゲート型MISトランジスタ101の模式的な平面図であって、図9(a)は全体図、図9(b)は内部拡大図をそれぞれ示す。図10は、図9(a)(b)のトレンチゲート型MISトランジスタ101の断面図であって、図9(b)の切断線E-E、F-FおよびG-Gでの切断面をそれぞれ示す。
次に、MISトランジスタ101の内部構造について説明する。
MISトランジスタ101は、n+型(たとえば、濃度が1×1018~1×1021cm-3)のSiCからなる基板105を備えている。基板105は、第3実施形態では、MISトランジスタ101のドレインとして機能し、その表面106(上面)がSi面であり、その裏面107(下面)がC面である。
活性領域110において、エピタキシャル層108にはゲートトレンチ112が格子状に形成されている(図9(b)参照)。このゲートトレンチ112によりエピタキシャル層108は、それぞれが四角状(正方形状)の複数のセル113に区画されている。
ゲートトレンチ112の内面には、その全域を覆うようにゲート絶縁膜122が形成されている。ゲート絶縁膜122は、ゲートトレンチ112の底面123上の部分が、ゲートトレンチ112の側面124上の部分よりも厚くなっている。
一方、pnダイオードセル115の中央部には、エピタキシャル層108の表面109からソース領域117およびチャネル領域118を貫通してドレイン領域119に達する、平面視正方形状の第1ソーストレンチとしてのDiソーストレンチ133が形成されている(図9(b)および図10のE-E断面、G-G断面参照)。Diソーストレンチ133の深さは、ゲートトレンチ112と同じである。また、Diソーストレンチ133の面積は、ショットキー領域131よりも小さくて、その一辺の長さL2が3μm程度である。
G耐圧保持領域140は、交差部121におけるゲートトレンチ112の底面123全面に形成され、さらに、当該底面123から交差部121に臨む各セル113の各角部の下部に形成されたゲートトレンチ112のコーナーエッジ部141をおよびコーナーエッジ部141直上のチャネル領域118に至るように形成されている。
層間絶縁膜143およびゲート絶縁膜122には、HDソーストレンチ126およびDiソーストレンチ133よりも大径のコンタクトホール144,145が形成されている。
ソース電極146は、ショットキーセル114において、HDソーストレンチ126の底側から順にショットキー領域131、HD耐圧保持領域127およびソース領域117に接触している。また、pnダイオードセル115において、Diソーストレンチ133の底側から順に底部チャネルコンタクト領域138、Di耐圧保持領域134およびソース領域117に接触している。すなわち、ソース電極146は、すべてのセル113に対して共通の配線となっている。
ポリシリコン層147は、不純物がドーピングされたドープトポリシリコンを用いて形成されたドープ層であり、たとえば、1×1015cm-3以上、好ましくは、1×1019~1×1021cm-3の高濃度で不純物がドーピングされた高濃度ドープ層である。ポリシリコン層147をドープ層(高濃度ドープ層を含む)として形成するときの不純物としては、N(窒素)、P(リン)、As(ひ素)などのn型不純物、Al(アルミニウム)、B(ホウ素)などのp型不純物を用いることができる。また、ポリシリコン層147の厚さは、たとえば、5000Å~10000Åである。
中間層148は、ポリシリコン層147上に積層されたメタル層149であり、Ti(チタン)を含有する層の単層またはTiを含有する層を含む複数の層からなる。Tiを含有する層は、Ti、TiN(窒化チタン)などを用いて形成することができる。また、中間層148の厚さは、たとえば、200nm~500nmである。
図11A~図11Fは、図10のトレンチゲート型MISトランジスタ101の製造工程の一部を工程順に示す模式的な断面図であって、図10と同じ位置での切断面を示す。
続いて、n型不純物が、エピタキシャル層108の表面109からエピタキシャル層108の内部にインプランテーション(注入)される。
続いて、レジスト153の開口から露出するゲートトレンチ112の交差部121、HDソーストレンチ126およびDiソーストレンチ133へ向けて、p型不純物がインプランテーション(注入)される。この際、ゲートトレンチ112(交差部121)の側面124、HDソーストレンチ126の側面129およびDiソーストレンチ133の側面136はいずれもレジスト153で覆われていないので、p型不純物は、側面124,129,136にも注入されることとなる。その後、たとえば、1400℃~2000℃でエピタキシャル層108が熱処理される。これにより、ドレイン領域119に注入されたp型不純物のイオンが活性化され、G耐圧保持領域140、HD耐圧保持領域127およびDi耐圧保持領域134が同時に形成される。また、それと同時に、HDソーストレンチ126の底面128におけるレジスト153で覆われていた部分に、ショットキー領域131が形成される。
続いて、レジスト154の開口から露出するDiソーストレンチ133の底面135中央部(Di耐圧保持領域134)へ向けて、p型不純物がインプランテーション(注入)される。その後、たとえば、1400℃~2000℃でエピタキシャル層108が熱処理される。これにより、Di耐圧保持領域134に注入されたp型不純物のイオンが活性化され、底部チャネルコンタクト領域138が形成される。
続いて、CVD法により、ドーピングされたポリシリコン材料がエピタキシャル層108の上方から堆積される。堆積後、ポリシリコン材料が、エッチバック面がエピタキシャル層108の表面109に対して面一になるまでエッチバックされる。続いて、HDソーストレンチ126およびDiソーストレンチ133内に残存するポリシリコン材料のみがドライエッチングにより除去される。これにより、ゲートトレンチ112内に残存するポリシリコン材料からなるゲート電極125が形成される。
このMISトランジスタ101は、たとえば、電動モータ(誘導性負荷の一例)の駆動回路(インバータ回路)のスイッチング素子として利用される。この場合、ソースパッド102(ソース電極146)とドレイン電極152との間(ソース-ドレイン間)にドレイン側が正となるドレイン電圧が印加された状態で、ゲートパッド104に所定の電圧(ゲート閾値電圧以上の電圧)がオン/オフされることによって、電動モータに流す電流をオン/オフするスイッチングを行なう。
このような場合に、ボディダイオード150の整流作用により、電流が、たとえば還流電流としてモータコイルに流れると、以下の不具合がある。
この電界は、ゲート電極125とエピタキシャル層108との電位差に起因して生じるものである。そして、ゲートトレンチ112の底面123においては、ゲート電極125を基準(0V)として非常に高い電位の等電位面が分布し、しかも等電位面の間隔が小さいため、非常に大きな電界が生じる。たとえば、ドレイン電圧が900Vであれば、ドレイン電極152に接する基板105の裏面107付近では900Vの等電位面が分布しており、基板105の裏面107からエピタキシャル層108の表面109側へ向かうにつれて電圧降下を生じるが、ゲートトレンチ112の底面123付近では、数十V程度の等電位面が分布する。そのため、ゲートトレンチ112の底面123では、ゲート電極125側へ向かう非常に大きな電界が生じる。とりわけ、このMISトランジスタ101のように、ゲートトレンチ112が格子状に形成されており、格子状のゲートトレンチ112の窓部に四角柱状のセル113が配列されている場合は、セル113の各角部に形成されたゲートトレンチ112のコーナーエッジ部141付近において、ゲート絶縁膜122の絶縁破壊が特に発生しやすい。
<第4実施形態>
図12は、本発明の第4実施形態に係るトレンチゲート型MISトランジスタ161の模式的な断面図であって、図10と同じ位置での切断面を示す。図12において、図10に示す各部に相当する部分には、それらの各部に付した参照符号と同一の参照符号を付し、それらの部分については説明を省略する。
同様に、MISトランジスタ161のDiソーストレンチ166は、エピタキシャル層108の表面109からチャネル領域118までの深さのDi上層トレンチ167(第1上層トレンチ)と、Di上層トレンチ167よりも幅が狭く、チャネル領域118からドレイン領域119までの深さのDi下層トレンチ168(第1下層トレンチ)とを含む。これによりDiソーストレンチ166では、Di上層トレンチ167の側面がDi下層トレンチ168の側面よりも外側に一段広がった2段構造を有している。
図13A~図13Gは、図12のトレンチゲート型MISトランジスタ161の製造工程の一部を工程順に示す模式的な断面図であって、図12と同じ位置での切断面を示す。
次に、図13Bに示すように、エピタキシャル層108が、HD上層トレンチ163およびDi上層トレンチ167を形成すべき領域に開口を有するマスクを用いてエッチングされる。これにより、エピタキシャル層108が表面109(Si面)からドライエッチングされて、HD上層トレンチ163およびDi上層トレンチ167が同時に形成される。
続いて、レジスト170の開口から露出するHD上層トレンチ163およびDi上層トレンチ167へ向けて、p型不純物がインプランテーション(注入)される。その後、たとえば、1400℃~2000℃でエピタキシャル層108が熱処理される。これにより、HD上層トレンチ163およびDi上層トレンチ167を介してチャネル領域118に注入されたp型不純物のイオンが活性化され、HDチャネルコンタクト領域165およびDiチャネルコンタクト領域169が同時に形成される。
続いて、レジスト171の開口から露出するHDソーストレンチ162およびDiソーストレンチ166へ向けて、p型不純物がインプランテーション(注入)される。その後、たとえば、1400℃~2000℃でエピタキシャル層108が熱処理される。これにより、ドレイン領域119に注入されたp型不純物のイオンが活性化され、HD耐圧保持領域127およびDi耐圧保持領域134が同時に形成される。また、それと同時に、HDソーストレンチ162の底面128におけるレジスト171で覆われていた部分に、ショットキー領域131が形成される。
次に、図13Gに示すように、図11Fと同様の方法により、層間絶縁膜143が形成された後、ポリシリコン層147が形成される。この後、中間層148、メタル層149、ドレイン電極152などが形成されることにより、図12のMISトランジスタ161が得られる。
さらに、このMISトランジスタ161では、各トレンチ162,166が2段構造であり、HDチャネルコンタクト領域165およびDiチャネルコンタクト領域169が形成されているので、ショットキーセル114およびpnダイオードセル115それぞれのチャネル領域118に対して直接コンタクトをとることができる。その結果、チャネル領域118の電位を精密に制御することができる。
<第5実施形態>
図14(a)(b)は、本発明の第5実施形態に係るプレーナゲート型MISトランジスタ181の模式的な平面図であって、図14(a)は全体図、図14(b)は内部拡大図をそれぞれ示す。図15は、図14(a)(b)のプレーナゲート型MISトランジスタ181の断面図であって、図14(b)の切断線H-HおよびI-Iでの切断面をそれぞれ示す。図14および図15において、図9および図10に示す各部に相当する部分には、それらの各部に付した参照符号と同一の参照符号を付し、それらの部分については説明を省略する。
プレーナ型MISトランジスタ181では、ゲート絶縁膜182は、ゲートトレンチ112の内面に形成される代わりに、エピタキシャル層108の表面109に形成され、その上に、ゲート電極183が形成されている。
<第6実施形態>
図16(a)(b)は、本発明の第6実施形態に係るトレンチゲート型MISトランジスタ191の模式的な平面図であって、図16(a)は全体図、図16(b)は内部拡大図をそれぞれ示す。図17は、図16(a)(b)のトレンチゲート型MISトランジスタ191の断面図であって、図16(b)の切断線J-JおよびK-Kでの切断面をそれぞれ示す。図16および図17において、図9および図10に示す各部に相当する部分には、それらの各部に付した参照符号と同一の参照符号を付し、それらの部分については説明を省略する。
この第6実施形態に係るMISトランジスタ191では、互いに同じ大きさの平面視四角形のショットキーセル114およびpnダイオードセル115が行列状(マトリクス状)に配列されており、ショットキーセル114はpnダイオードセル115に包囲されている。
以上のように、このMISトランジスタ191によっても、前述のMISトランジスタ101と同様の作用効果を達成することができる。
以上、本発明の実施形態を説明したが、本発明は、他の形態で実施することもできる。
たとえば、MISトランジスタ1,47,51,97,101,161,181,191の各半導体部分の導電型を反転した構成が採用されてもよい。たとえば、MISトランジスタ1において、p型の部分がn型であり、n型の部分がp型であってもよい。
また、各単位セル71は、平面視正方形(四角形状)に限らず、たとえば、平面視三角形、平面視五角形、平面視六角形等の他の平面視多角形状であってもよい。
また、各セル113は、平面視正方形(四角形状)に限らず、たとえば、平面視三角形、平面視五角形、平面視六角形等の他の平面視多角形状、さらにはストライプ状であってもよい。
また、ソース電極146としては、たとえば、ポリシリコン層147および中間層148を省略して、メタル層149の単層構造にすることにより、ショットキー領域131に対してショットキー接合させることができる。これにより、ショットキーセル114において、ヘテロ接合ダイオード151に代えて、ショットキーバリアダイオードを形成することができる。
また、本発明の各実施形態において表した構成要素は、本発明の範囲で組み合わせることができる。
Claims (29)
- ワイドバンドギャップ半導体からなる半導体層を有する半導体装置であって、
前記半導体層は、
前記半導体層の表面側に露出するように形成された第1導電型のソース領域と、
前記ソース領域に対して前記半導体層の裏面側に前記ソース領域に接するように形成された第2導電型のチャネル領域と、
前記チャネル領域に対して前記半導体層の前記裏面側に前記チャネル領域に接するように形成された第1導電型のドレイン領域と、
前記半導体層の前記表面から前記ソース領域および前記チャネル領域を貫通して前記ドレイン領域に達し、側面および底面を有するソーストレンチと、
前記チャネル領域に接するように形成されたゲート絶縁膜と、
前記ゲート絶縁膜を介して前記チャネル領域に対向するゲート電極と、
前記ソーストレンチの前記側面または前記底面に選択的に形成された第2導電型の第1耐圧保持領域とを含み、
前記ソーストレンチ内において前記ドレイン領域に接合され、前記チャネル領域と前記ドレイン領域とのpn接合により形成されるボディダイオードの拡散電位よりも低い接合障壁を、前記ドレイン領域との接合により形成する障壁形成層を含む、半導体装置。 - 前記障壁形成層が、Ni、Ti、Al、MoおよびPoly-Siからなる群から選択される1種からなる、請求項1に記載の半導体装置。
- 前記半導体層は、前記半導体層の前記表面から前記ソース領域および前記チャネル領域を貫通して前記ドレイン領域に達し、側面および底面を有する格子状のゲートトレンチと、
格子状の前記ゲートトレンチにより区画され、複数の角部を有する多角柱状の単位セルを複数含み、当該各単位セルが、前記ソース領域、前記チャネル領域および前記ドレイン領域を有しており、
前記ゲート絶縁膜は、前記ゲートトレンチの前記側面および前記底面上に形成されており、
前記ゲート電極は、前記ゲート絶縁膜を介して前記チャネル領域に対向するように、前記ゲートトレンチに埋め込まれており、
前記第1耐圧保持領域は、前記ドレイン領域を前記ソーストレンチの前記底面に露出させるように、前記ソーストレンチの一部の領域において、前記側面と前記底面とが交わる前記ソーストレンチのエッジ部に選択的に形成されており、
前記障壁形成層は、前記ソーストレンチの前記底面に露出する前記ドレイン領域に接合されている、請求項1または2に記載の半導体装置。 - 前記半導体層は、前記単位セルの前記角部に形成された前記ゲートトレンチのコーナーエッジ部に選択的に形成された第2導電型の第2耐圧保持領域をさらに含む、請求項3に記載の半導体装置。
- 前記第2耐圧保持領域は、前記チャネル領域における前記コーナーエッジ部直上の部分に至るように形成されている、請求項4に記載の半導体装置。
- 前記第2耐圧保持領域は、格子状の前記ゲートトレンチの交差部に選択的に形成されている、請求項4または5に記載の半導体装置。
- 前記半導体層は、格子状の前記ゲートトレンチの線状部の底面に形成され、当該線状部の幅よりも狭い幅を有する第2導電型の第3耐圧保持領域をさらに含む、請求項3~6のいずれか一項に記載の半導体装置。
- 前記第3耐圧保持領域の不純物濃度は、前記第2耐圧保持領域の不純物濃度よりも高い、請求項7に記載の半導体装置。
- 前記第3耐圧保持領域の厚さは、前記第2耐圧保持領域の厚さよりも小さい、請求項7または8に記載の半導体装置。
- 前記チャネル領域は、複数の角部を有する平面視多角形状で前記半導体層の前記表面に露出するように形成されており、当該チャネル領域がマトリクス状に配列されており、
前記ソース領域は、各前記チャネル領域の表面に露出するようにウェル状に形成されており、
前記ゲート絶縁膜は、前記半導体層の前記表面に露出する前記チャネル領域上に形成されており、
前記第1耐圧保持領域は、前記ドレイン領域を前記ソーストレンチの前記底面に露出させるように、前記ソーストレンチの一部の領域において、前記側面と前記底面とが交わる前記ソーストレンチのエッジ部に選択的に形成されており、
前記障壁形成層は、前記ソーストレンチの前記底面に露出する前記ドレイン領域に接合されている、請求項1または2に記載の半導体装置。 - 前記半導体層は、隣り合う前記チャネル領域の各間を延びるチャネル間領域と、前記チャネル領域の前記角部に形成された前記チャネル間領域のコーナー部に選択的に形成された第2導電型の第4耐圧保持領域とをさらに含む、請求項10に記載の半導体装置。
- 前記半導体層は、前記チャネル間領域の線状部に形成され、当該線状部の幅よりも狭い幅を有する第2導電型の第5耐圧保持領域をさらに含む、請求項11に記載の半導体装置。
- 前記ドレイン領域は、前記ソーストレンチの前記底面が選択的に前記半導体層の前記表面側に突出することにより形成された段部を有している、請求項1~12のいずれか一項に記載の半導体装置。
- ワイドバンドギャップ半導体からなる半導体層と、
前記半導体層に形成され、前記半導体層を複数のセルに区画するゲート部とを含み、
前記セルは、
前記半導体層の表面側から裏面側へ向かってこの順に配置された第1導電型のソース領域、第2導電型のチャネル領域および第1導電型のドレイン領域を有し、前記半導体層の前記表面から前記ソース領域および前記チャネル領域を貫通して最深部が前記ドレイン領域に達する第1ソーストレンチが形成された第1MISトランジスタ構造と、前記第1ソーストレンチの内面に選択的に形成された第2導電型の第1耐圧保持領域を有し、当該第1耐圧保持領域と前記ドレイン領域とのpn接合により構成されたpnダイオードとを含むpnダイオードセルと、
前記ドレイン領域と一体な第1導電型のショットキー領域が選択的に露出したショットキーセルとを含み、
前記pnダイオードセルおよび前記ショットキーセルに跨って形成され、前記ソース領域に対してオーミック接触を形成し、前記ショットキー領域に対して、前記チャネル領域と前記ドレイン領域とのpn接合により形成されるボディダイオードの拡散電位よりも低いショットキー障壁を形成するソース電極をさらに含む、半導体装置。 - 前記ソース電極は、前記ショットキー領域との接触部分に、Ni、Ti、Al、Moおよびポリシリコンからなる群から選択される1種からなる障壁形成層を有する、請求項14に記載の半導体装置。
- 前記pnダイオードセルにおいて前記第1耐圧保持領域は、前記第1ソーストレンチの底面から前記ソーストレンチの側面に沿って前記チャネル領域に至るように形成されており、
前記pnダイオードセルは、前記第1ソーストレンチの前記底面に形成され、前記第1耐圧保持領域よりも不純物濃度が高い第2導電型のチャネルコンタクト領域をさらに含む、請求項14または15に記載の半導体装置。 - 前記pnダイオードセルにおいて前記第1ソーストレンチは、前記半導体層の前記表面から前記チャネル領域までの深さの第1上層トレンチと、前記第1上層トレンチよりも幅が狭く、前記チャネル領域から前記ドレイン領域までの深さの第1下層トレンチとを含む2段構造を有しており、
前記pnダイオードセルは、前記第1上層トレンチと前記第1下層トレンチとの段差部分に露出する前記チャネル領域に形成され、前記チャネル領域よりも不純物濃度が高い第2導電型のチャネルコンタクト領域をさらに含む、請求項14または15に記載の半導体装置。 - 前記ショットキーセルは、前記半導体層の表面側から裏面側へ向かってこの順に配置された第1導電型のソース領域、第2導電型のチャネル領域および第1導電型のドレイン領域を有し、前記半導体層の前記表面から前記ソース領域および前記チャネル領域を貫通して前記ドレイン領域に達する第2ソーストレンチが形成された第2MISトランジスタ構造と、前記第2ソーストレンチの側面と底面とが交わって形成された前記第2ソーストレンチのエッジ部に選択的に形成された第2耐圧保持領域とをさらに含み、
前記ショットキー領域は、前記第2耐圧保持領域で取り囲まれた前記第2ソーストレンチの底面に形成されている、請求項14~17のいずれか一項に記載の半導体装置。 - 前記ショットキー領域は、当該ショットキー領域と前記第2耐圧保持領域との接合部から発生する空乏層が繋がらない面積で形成されている、請求項18に記載の半導体装置。
- 前記ショットキーセルの面積が、前記pnダイオードセルの面積よりも大きい、請求項14~19のいずれか一項に記載の半導体装置。
- 前記ショットキーセルにおいて前記第2ソーストレンチは、前記半導体層の前記表面から前記チャネル領域までの深さの第2上層トレンチと、前記第2上層トレンチよりも幅が狭く、前記チャネル領域から前記ドレイン領域までの深さの第2下層トレンチとを含む2段構造を有しており、前記第2耐圧保持領域は、前記第2下層トレンチの側面に沿って前記チャネル領域に至るように形成されており、
前記ショットキーセルは、前記第2上層トレンチと前記第2下層トレンチとの段差部分に露出する前記チャネル領域に形成され、前記チャネル領域よりも不純物濃度が高い第2導電型のチャネルコンタクト領域をさらに含む、請求項18または19に記載の半導体装置。 - 前記ゲート部は、前記半導体層に形成されたゲートトレンチと、前記ゲートトレンチの内面に形成されたゲート絶縁膜と、前記ゲートトレンチにおいて前記ゲート絶縁膜の内側に形成されたゲート電極とを含む、請求項14~21のいずれか一項に記載の半導体装置。
- 前記ゲートトレンチが格子状に形成されており、
前記半導体装置は、前記ゲートトレンチの交差部を介して前記pnダイオードセルおよび前記ショットキーセルに跨るように形成され、前記第1耐圧保持領域と前記第2耐圧保持領域とを電気的に接続する第2導電型の中継領域をさらに含む、請求項18または19に記載の半導体装置。 - 前記ゲート部は、前記半導体層上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極と含む、請求項14~21のいずれか一項に記載の半導体装置。
- 前記ショットキーセルは、前記pnダイオードセルに取り囲まれている、請求項14~24のいずれか一項に記載の半導体装置。
- 前記ゲート部は、前記pnダイオードセルを互いに同じ大きさで行列状に配列させる格子状に形成されており、
前記ショットキーセルは、前記pnダイオードセル4つ分または9つ分に相当する面積を有している、請求項14~25のいずれか一項に記載の半導体装置。 - 前記ショットキーセルおよび前記pnダイオードセルは、四角状に形成された四角形セルを含む、請求項14~26のいずれか一項に記載の半導体装置。
- 前記ショットキーセルおよび前記pnダイオードセルは、六角形に形成された六角形セルを含む、請求項14~27のいずれか一項に記載の半導体装置。
- 前記ショットキーセルおよび前記pnダイオードセルは、ストライプ状に形成されたストライプセルを含む、請求項14~28のいずれか一項に記載の半導体装置。
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US9406744B2 (en) | 2016-08-02 |
JP2015173290A (ja) | 2015-10-01 |
US20130313635A1 (en) | 2013-11-28 |
JPWO2012105609A1 (ja) | 2014-07-03 |
JP5858933B2 (ja) | 2016-02-10 |
US9184286B2 (en) | 2015-11-10 |
JP6065335B2 (ja) | 2017-01-25 |
US20160329397A1 (en) | 2016-11-10 |
US9698216B2 (en) | 2017-07-04 |
US20160043167A1 (en) | 2016-02-11 |
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