JP7101101B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7101101B2 JP7101101B2 JP2018214459A JP2018214459A JP7101101B2 JP 7101101 B2 JP7101101 B2 JP 7101101B2 JP 2018214459 A JP2018214459 A JP 2018214459A JP 2018214459 A JP2018214459 A JP 2018214459A JP 7101101 B2 JP7101101 B2 JP 7101101B2
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Description
図16は、検討例の半導体装置の断面図、図17は、検討例の半導体装置の等価回路図、図18は、検討例の半導体装置(特に、ダイオード)の電圧・電流特性を示すグラフである。
図1は、実施の形態の半導体装置SD1の平面図、図2は、図1のA-A線に沿う断面図、図3は、実施の形態の半導体装置の等価回路図、図4は、実施の形態の半導体装置(特に、ダイオード)の電圧・電流特性を示すグラフ、図5は、図1のB-B線に沿う断面図である。
次に、図2、図6~図15を用いて、本実施の形態における半導体装置の製造方法を説明する。図6~図15は、本実施の形態の半導体装置の製造方法を示す断面図であり、図2の断面図に対応している。
図19は、変形例1の半導体装置SD2の断面図、図20および図21は、変形例1の半導体装置SD2の製造工程中の断面図である。変形例1は、上記実施の形態に対する変形例であり、変形例1の半導体装置SD2では、ボディダイオード領域BDRおよびショットキーバリアダイオード領域SBRに溝GR1が設けられていない。つまり、トランジスタ領域TRにおける半導体基板SBの主面SBaと、ボディダイオード領域BDRおよびショットキーバリアダイオード領域SBRにおける半導体基板SBの主面SBaとは、半導体基板SBの裏面SBbを基準としてほぼ等しい高さを有する。仮に、両者間に高さの差が有ったとしても、その高低差は、ソース領域SRの厚さよりも小さい。その他の構成要素は、上記実施の形態の半導体装置SD1と同様であり、同様の符号を付している。
図22は、変形例2の半導体装置SD3の断面図、図23は、変形例2の半導体装置SD3の製造工程中の断面図である。変形例2は、変形例1に対する変形例であり、変形例2の半導体装置SD3では、チャネル形成領域CH1は、トランジスタ領域TRにのみ形成されている。その他の構成要素は、上記変形例1の半導体装置SD2と同様であり、同様の符号を付している。
図24は、変形例3の半導体装置SD4の断面図、図25および図26は、変形例3の半導体装置SD4の製造工程中の断面図である。変形例3は、上記実施の形態に対する変形例であり、半導体装置SD4では、p型半導体領域PLが設けられていない。
(a)第1導電型を有し、第1主面と前記第1主面の反対側の第2主面とを含む第1半導体層と、前記第2主面上に配置され、前記第1導電型を有し、かつ、前記第1半導体層よりも高濃度の第2半導体層とを備える半導体基板を準備する工程、
(b)MOSFETの形成領域である第1領域において、前記第1主面側に露出するように、前記第1半導体層に前記第1導電型の第1半導体領域を形成する工程、
(c)前記第1領域において、前記第1半導体領域に対して前記第2主面側に位置するように、前記第1導電型と反対の第2導電型を有する第2半導体領域を形成する工程、
(d)ボディダイオードの形成領域である第2領域において、前記第1主面側に露出するように前記第2導電型の第3半導体領域を形成する工程、
(e)前記第2領域において、前記第3半導体領域に対して前記第2主面側に位置するように、前記第2導電型の第4半導体領域を形成する工程、
(f)前記第2領域において、前記第4半導体領域に対して前記第2主面側に位置するように、前記第2導電型の第5半導体領域を形成する工程、
(g)前記第1領域において、前記第1半導体領域および前記第2半導体領域を貫通し、前記第1半導体層に達する第1溝を形成する工程、
(h)前記第1溝内にゲート絶縁膜を介してゲート電極を形成する工程、
(i)前記第1領域、前記第2領域、および、ショットキーバリアダイオードの形成領域である第3領域において、前記第1主面上に金属層を形成する工程、
を有し、
前記第4半導体領域の不純物濃度は、前記第3半導体領域および前記第5半導体領域の不純物濃度よりも低く、
前記第2領域において、前記第5半導体領域と前記第1半導体層との間で前記ボディダイオードが構成され、
前記第3領域において、前記金属層と、前記第1半導体層との間で前記ショットキーバリアダイオードが構成される、半導体装置の製造方法。
付記1記載の半導体装置の製造方法において、
前記(b)工程は、
(b-1)前記第1領域、前記第2領域および前記第3領域において、前記第1半導体領域を形成する工程、
(b-2)前記第2領域および前記第3領域において、前記第1半導体層の前記第1主面に第2溝を形成することで、前記第1半導体領域の一部を除去し、前記第1領域に前記第1半導体領域の他部を残す工程、
を含む、半導体装置の製造方法。
付記1記載の半導体装置の製造方法において、
前記(b)工程は、
(b-3)前記第2領域および前記第3領域を覆う第1マスク膜を形成する工程、
(b-4)前記第1マスク膜から露出した前記第1領域において、前記第1半導体層に前記第1導電型の不純物を注入して前記第1半導体領域を形成する工程、
を含む、半導体装置の製造方法。
付記1記載の半導体装置の製造方法において、
前記(c)工程は、前記第2領域および前記第3領域を覆う第2マスク膜を用いて、前記第1領域に選択的に前記第2半導体領域を形成する、半導体装置の製造方法。
付記1記載の半導体装置の製造方法において、
前記第1半導体層および前記第2半導体層は、炭化ケイ素からなる、半導体装置の製造方法。
(a)第1導電型を有し、第1主面と前記第1主面の反対側の第2主面とを含む第1半導体層と、前記第1導電型と反対の第2導電型を有し、前記第1主面に沿って、前記第1半導体層の内部に分散配置された第1半導体領域と、前記第2主面上に配置され、前記第1導電型を有し、かつ、前記第1半導体層よりも高濃度の第2半導体層とを備える半導体基板を準備する工程、
(b)MOSFETの形成領域である第1領域において、前記第1主面側に露出するように、前記第1半導体層に前記第1導電型の第2半導体領域を形成する工程、
(c)前記第1領域において、前記第2半導体領域に対して前記第2主面側に位置するように、前記第2導電型を有する第3半導体領域を形成する工程、
(d)ボディダイオードの形成領域である第2領域において、前記第1主面側に露出するように前記第2導電型の第4半導体領域を形成する工程、
(e)前記第1領域において、前記第2半導体領域および前記第3半導体領域を貫通し、前記第1半導体層に達する第1溝を形成する工程、
(f)前記第1溝内にゲート絶縁膜を介してゲート電極を形成する工程、
(g)前記第1領域、前記第2領域、および、ショットキーバリアダイオードの形成領域である第3領域において、前記第1主面上に金属層を形成する工程、
を有し、
前記第1半導体領域は、前記第4半導体領域から離間して配置され、
前記第1半導体領域と前記第4半導体領域との間には、前記第1半導体層の一部が介在し、
前記第1半導体領域の不純物濃度は、前記第4半導体領域の不純物濃度よりも低く、
前記第2領域において、前記第1半導体領域と前記第1半導体層との間で前記ボディダイオードが構成され、
前記第3領域において、前記金属層と、前記第1半導体層との間で前記ショットキーバリアダイオードが構成される、半導体装置の製造方法。
BDR ボディダイオード領域
BK 基板(バルク基板、半導体層)
BKa 主面(第1主面)
BKb 裏面(第2主面)
CH、CH1 チャネル形成領域(p型半導体領域)
CR セル領域
D ドレイン
DE ドレイン電極
DF ドリフト層(n型半導体領域、ドリフト領域)
DR ドレイン領域(n型半導体領域、半導体層)
EP、EP1、EP2 エピタキシャル層(半導体層)
EPa 主面(第1主面)
EPb 裏面(第2主面)
FET
G ゲート
GE ゲート電極
GI ゲート絶縁膜
GR1、GR2 溝
GR1b 底面(底部)
GW ゲート配線
IF 層間絶縁膜
M1、M2 金属層
MSK1~MSK8 マスク膜
NR1 n型半導体領域
OP 開口
PER 周辺領域
PH p型半導体領域
PL p型半導体領域
PR、PR1 p型半導体領域
Rn0、Rn1、Rn2、Rp、Rp1 抵抗(寄生抵抗)
S ソース
SB 半導体基板
SBa 主面(第1主面)
SBb 裏面(第2主面)
SBD ショットキーバリアダイオード
SBR ショットキーバリアダイオード領域
SD0、SD1、SD2、SD3、SD4 半導体装置
SE ソース電極
SL シリサイド層
SR ソース領域(n型半導体領域)
TM ターミネーション領域
TR トランジスタ領域
Claims (15)
- ボディダイオードの形成領域である第1領域、ショットキーバリアダイオードの形成領域である第2領域を備える第1主面と、前記第1主面の反対側の第2主面とを含み、第1導電型を有する第1半導体層と、
前記第2主面上に配置され、前記第1導電型を有し、かつ、前記第1半導体層よりも高濃度の第2半導体層と、
前記第1領域において、前記第1導電型と反対の第2導電型を有し、前記第1主面側に露出するように、前記第1半導体層内に形成された第1半導体領域と、
前記第1領域において、前記第2導電型を有し、前記第1半導体領域に対して前記第2主面側に形成された第2半導体領域と、
前記第1領域において、前記第2導電型を有し、前記第1半導体領域と前記第2半導体領域との間に形成された第3半導体領域と、
前記第1領域および前記第2領域において、前記第1主面上に形成された金属層と、
を有し、
前記第3半導体領域の不純物濃度は、前記第1半導体領域および前記第2半導体領域の不純物濃度よりも低く、
前記第1領域において、前記第2半導体領域と前記第1半導体層との間で前記ボディダイオードが構成され、
前記第2領域において、前記金属層と前記第1半導体層との間で前記ショットキーバリアダイオードが構成される、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1半導体層および前記第2半導体層は、炭化ケイ素からなる、半導体装置。 - 請求項2に記載の半導体装置において、
前記ショットキーバリアダイオードのオン開始電圧は、前記ボディダイオードのオン開始電圧よりも低い、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1領域において、前記金属層は、前記第1半導体領域に電気的に接続されている、半導体装置。 - 請求項1に記載の半導体装置において、
断面視において、前記第3半導体領域は、前記第1半導体領域および前記第2半導体領域に接しており、
前記第2半導体領域は、前記第1半導体領域および前記第3半導体領域を介して前記金属層に接続されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記第3半導体領域の不純物濃度は、前記第2半導体領域の不純物濃度よりも一桁以上低い、半導体装置。 - 請求項6に記載の半導体装置において、
前記第3半導体領域の不純物濃度は、1×1017cm-3以下である、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1主面は、前記第1領域に対して前記第2領域と反対側にMOSFET形成領域である第3領域を備え、
前記第3領域において、さらに、
前記第1導電型を有し、前記第1主面側に露出するように、前記第1半導体層内に形成された第4半導体領域と、
前記第2導電型を有し、前記第4半導体領域に対して前記第2主面側に形成された第5半導体領域と、
前記第1主面から前記第2主面に向かって延び、前記第4半導体領域および前記第5半導体領域を貫通して前記第1半導体層に達する第1溝の内部に、ゲート絶縁膜を介して形成されたゲート電極と、
を有する、半導体装置。 - 請求項8に記載の半導体装置において、
前記第1半導体層は、前記第1主面の前記第1領域および前記第2領域において、底面を有する第2溝を備え、
前記第2主面を基準とし、前記第3領域の前記第1主面は、前記底面よりも高い、半導体装置。 - 請求項8に記載の半導体装置において、
前記第3半導体領域は、前記第5半導体領域と重なる部分と、重ならない部分とを含んでいる、半導体装置。 - 請求項8に記載の半導体装置において、
前記第1主面は、さらに、前記第1領域、前記第2領域および前記第3領域を取り囲む第4領域を備え、
前記第4領域において、さらに、
前記第2導電型を有し、前記第1主面側に露出するように、前記第1半導体層内に形成された第6半導体領域と、
前記第2導電型を有し、前記第6半導体領域に対して前記第2主面側に形成された第7半導体領域と、
前記第2導電型を有し、前記第6半導体領域と前記第7半導体領域との間に形成された第8半導体領域と、
を有し、
前記第8半導体領域の不純物濃度は、前記第6半導体領域および前記第7半導体領域の不純物濃度よりも低く、
前記金属層は、前記第4領域に延在し、前記第6半導体領域および前記第8半導体領域を介して前記第7半導体領域に電気的に接続されている、半導体装置。 - ボディダイオードの形成領域である第1領域、ショットキーバリアダイオードの形成領域である第2領域を備える第1主面と、前記第1主面の反対側の第2主面とを含み、第1導電型を有する第1半導体層と、
前記第2主面上に配置され、前記第1導電型を有し、かつ、前記第1半導体層よりも高濃度の第2半導体層と、
前記第1領域において、前記第1導電型と反対の第2導電型を有し、前記第1主面側に露出するように、前記第1半導体層内に形成された第1半導体領域と、
前記第1領域において、前記第2導電型を有し、前記第1半導体領域に対して前記第2主面側に形成された第2半導体領域と、
前記第1領域および前記第2領域において、前記第1主面上に形成された金属層と、
を有し、
前記第2半導体領域は、前記第1半導体領域から離間して配置されており、
前記第2半導体領域と前記第1半導体領域との間には、前記第1半導体層の一部が介在しており、
前記第1領域において、前記第2半導体領域と前記第1半導体層との間で前記ボディダイオードが構成され、
前記第2領域において、前記金属層と前記第1半導体層との間で前記ショットキーバリアダイオードが構成される、半導体装置。 - 請求項12に記載の半導体装置において、
前記第1半導体層および前記第2半導体層は、炭化ケイ素からなる、半導体装置。 - 請求項13に記載の半導体装置において、
前記ショットキーバリアダイオードのオン開始電圧は、前記ボディダイオードのオン開始電圧よりも低い、半導体装置。 - 請求項12に記載の半導体装置において、
前記第1主面は、さらに、MOSFET形成領域である第3領域を備え、
前記第3領域において、さらに、
前記第1導電型を有し、前記第1主面側に露出するように、前記第1半導体層内に形成された第3半導体領域と、
前記第2導電型を有し、前記第3半導体領域に対して前記第2主面側に形成された第4半導体領域と、
前記第1主面から前記第2主面に向かって延び、前記第3半導体領域および前記第4半導体領域を貫通して前記第1半導体層に達する溝の内部に、ゲート絶縁膜を介して形成されたゲート電極と、
を有する、半導体装置。
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