JP6144674B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6144674B2 JP6144674B2 JP2014515523A JP2014515523A JP6144674B2 JP 6144674 B2 JP6144674 B2 JP 6144674B2 JP 2014515523 A JP2014515523 A JP 2014515523A JP 2014515523 A JP2014515523 A JP 2014515523A JP 6144674 B2 JP6144674 B2 JP 6144674B2
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Description
図1は、実施の形態1に係る半導体装置である炭化珪素MOSFETの上面構成を模式的に示す図である。また図2は、当該半導体装置の半導体層の最表面の構成を示す図である。つまり、当該半導体装置は、図2に示す半導体層の上に、図1に示す各要素が形成されて構成されている。
実施の形態1では、ソースコンタクト領域12a及びソースエクステンション領域12bを形成するためのイオン注入と、ソース抵抗制御領域15aを形成するためのイオン注入とを別の工程で行っていたが、実施の形態2では、それらを1回のイオン注入工程で行う技術を提案する。
実施の形態3においては、ソースコンタクト領域12a及びソースエクステンション領域12bを形成するための注入マスクと、ウェル領域20を形成するための注入マスクとを、1回の写真製版のみを用いて形成する技術を提案する。
実施の形態4では、本発明をトレンチ形のMOSFETに適用する。図31〜図39は、本実施の形態に係る半導体装置であるトレンチ形の炭化珪素MOSFETの製造方法を示す工程図である。これらの図は、能動領域7内に複数配設されたユニットセル10のうちの一つの右側半分の縦断面に相当する。つまり、図31〜図39は終端領域を含んでおらず、能動領域7内の領域の任意の位置の断面を示している。
実施の形態5では、実施の形態4と同様に、本発明をトレンチ形のMOSFETに適用するが、ソース領域12の構成を、ソースコンタクト領域12a、ソース抵抗制御領域15a、ソースエクステンション領域12bが縦方向(ドリフト層2の表面に対して垂直な方向、以下「深さ方向」ともいう)に並ぶ積層構造とする。
Claims (13)
- 炭化珪素からなる半導体基板(1a)と、
前記半導体基板(1a)上に形成された炭化珪素半導体の第1導電型のドリフト層(2)と、
前記ドリフト層(2)の表層部に選択的に形成された第2導電型のウェル領域(20)と、
前記ウェル領域(20)内の表層部に形成された第1導電型のソース領域(12)と、
前記ウェル領域(20)に隣接する前記ドリフト層(2)の部分であるJFET領域(11)と、
前記ソース領域(12)と前記JFET領域(11)とに挟まれた前記ウェル領域(20)の部分であるチャネル領域と、
前記ドリフト層(2)上にゲート絶縁膜(30)を介して配設され、前記ソース領域(12)、前記チャネル領域および前記JFET領域(11)に跨って延在するゲート電極(35)と、
前記ソース領域(12)に接続するソース電極(41)と、
前記半導体基板(1a)の裏面に形成されたドレイン電極(43)とを備え、
前記ソース領域(12)は、
前記ソース電極(41)に接続するソースコンタクト領域(12a)と、
前記チャネル領域に隣接するソースエクステンション領域(12b)と、
前記ソースエクステンション領域(12b)と前記ソースコンタクト領域(12a)との間に配設され、前記ソースエクステンション領域(12b)および前記ソースコンタクト領域(12a)よりも第1導電型の不純物濃度が低く設定されたソース抵抗制御領域(15a)とを含み、
前記ソースコンタクト領域(12a)の外周のコーナー部および前記ソースエクステンション領域(12b)の内周のコーナー部はラウンド形状になっており、
前記ソース抵抗制御領域(15a)は、オン電流の流れる方向に均一な長さを持つように形成されており、
前記チャネル領域のチャネル長は均一になっており、
前記ゲート電極(35)は、前記ソース領域(12)のうちの前記ソースエクステンション領域(12b)のみにオーバーラップしている
ことを特徴とする半導体装置。 - 炭化珪素からなる半導体基板(1a)と、
前記半導体基板(1a)上に形成された炭化珪素半導体の第1導電型のドリフト層(2)と、
前記ドリフト層(2)の表層部に選択的に形成された第2導電型のウェル領域(20)と、
前記ウェル領域(20)を貫通するように形成されたトレンチ(110)と、
前記ウェル領域(20)内の表層部および前記トレンチ(110)の側壁に形成された第1導電型のソース領域(12)と、
前記ソース領域(12)と前記ドリフト層(2)とに挟まれた前記ウェル領域(20)の部分であって、前記トレンチ(110)の側壁の部分であるチャネル領域と、
前記ドリフト層(2)上にゲート絶縁膜(30)を介して配設され、前記ソース領域(12)および前記チャネル領域に跨って延在するゲート電極(35)と、
前記ソース領域(12)に接続するソース電極(41)と、
前記半導体基板(1a)の裏面に形成されたドレイン電極(43)とを備え、
前記ソース領域(12)は、
前記ソース電極(41)に接続するソースコンタクト領域(12a)と、
前記チャネル領域に隣接するソースエクステンション領域(12b)と、
前記ソースエクステンション領域(12b)と前記ソースコンタクト領域(12a)との間に配設され、前記ソースエクステンション領域(12b)および前記ソースコンタクト領域(12a)よりも第1導電型の不純物濃度が低く設定されたソース抵抗制御領域(15a)とを含み、
前記ソースコンタクト領域(12a)の外周のコーナー部および前記ソースエクステンション領域(12b)の内周のコーナー部はラウンド形状になっており、
前記ソース抵抗制御領域(15a)は、オン電流の流れる方向に均一な長さを持つように形成されており、
前記チャネル領域のチャネル長は均一になっており、
前記ゲート電極(35)は、前記ソース領域(12)のうちの前記ソースエクステンション領域(12b)のみに対向している
ことを特徴とする半導体装置。 - 前記ソースコンタクト領域(12a)と前記ソースエクステンション領域(12b)は同じ不純物濃度分布を有している
請求項1または請求項2記載の半導体装置。 - 前記ソース抵抗制御領域(15a)の第1導電型の不純物濃度は、前記ソースエクステンション領域(12b)およびソースコンタクト領域(12a)の第1導電型の不純物濃度よりも1桁以上小さい
請求項1から請求項3のいずれか一項記載の半導体装置。 - 前記ソース抵抗制御領域(15a)のシート抵抗は、前記ソースエクステンション領域(12b)およびソースコンタクト領域(12a)のシート抵抗よりも高い
請求項1から請求項3のいずれか一項記載の半導体装置。 - 炭化珪素からなる半導体基板(1a)と、
前記半導体基板(1a)上に形成された炭化珪素半導体の第1導電型のドリフト層(2)と、
前記ドリフト層(2)の表層部に選択的に形成された第2導電型のウェル領域(20)と、
前記ウェル領域(20)を貫通するように形成されたトレンチ(110)と、
前記ウェル領域(20)内の表層部および前記トレンチ(110)の側壁に形成された第1導電型のソース領域(12)と、
前記ソース領域(12)と前記ドリフト層(2)とに挟まれた前記ウェル領域(20)の部分であって、前記トレンチ(110)の側壁の部分であるチャネル領域と、
前記ドリフト層(2)上にゲート絶縁膜(30)を介して配設され、前記ソース領域(12)および前記チャネル領域に跨って延在するゲート電極(35)と、
前記ソース領域(12)に接続するソース電極(41)と、
前記半導体基板(1a)の裏面に形成されたドレイン電極(43)とを備え、
前記ソース領域(12)は、
前記ソース電極(41)に接続するソースコンタクト領域(12a)と、
前記チャネル領域に隣接するソースエクステンション領域(12b)と、
前記ソースエクステンション領域(12b)と前記ソースコンタクト領域(12a)との間に配設され、前記ソースエクステンション領域(12b)および前記ソースコンタクト領域(12a)よりも第1導電型の不純物濃度が低く設定されたソース抵抗制御領域(15a)とを含み、
前記ソースエクステンション領域(12b)、前記ソース抵抗制御領域(15a)および前記ソースコンタクト領域(12a)は、前記トレンチ(110)の側壁に存在し、
前記ソース抵抗制御領域(15a)は、オン電流の流れる方向に均一な長さを持つように形成されており、
前記ゲート電極(35)は、前記ソース領域(12)のうちの前記ソースエクステンション領域(12b)のみに対向している
ことを特徴とする半導体装置。 - (a)炭化珪素半導体の第1導電型の半導体層(2)の表層部に、第2導電型の不純物をイオン注入することによりウェル領域(20)を形成する工程と、
(b)前記ウェル領域(20)内の表層部に第1導電型の不純物をイオン注入することよりソース領域(12)を形成する工程と、
(c)前記ウェル領域(20)に隣接する前記半導体層(2)の部分であるJFET領域(11)、前記ソース領域(12)と前記JFET領域(11)とに挟まれた前記ウェル領域(20)の部分であるチャネル領域および前記ソース領域(12)に跨がるように、前記半導体層(2)上にゲート絶縁膜(30)を介してゲート電極(35)を形成する工程と、
(d)前記ソース領域(12)に接続するソース電極(41)を形成する工程とを備え、
前記工程(b)は、
(b−1)前記ソース電極(41)に接続する前記ソース領域(12)の部分であるソースコンタクト領域(12a)を形成するイオン注入工程と、
(b−2)前記チャネル領域に隣接する前記ソース領域(12)の部分であるソースエクステンション領域(12b)を形成するイオン注入工程と、
(b−3)前記ソースエクステンション領域(12b)と前記ソースコンタクト領域(12a)とに挟まれた前記ソース領域(12)の部分であるソース抵抗制御領域(15a)を形成するイオン注入工程と、を含み、
前記工程(b−1)及び(b−2)は同時に行われ、
前記ソースコンタクト領域(12a)の外周のコーナー部および前記ソースエクステンション領域(12b)の内周のコーナー部はラウンド形状になっており、
前記チャネル領域のチャネル長は均一になっており、
前記ソース抵抗制御領域(15a)は、オン電流の流れる方向に均一な長さを持つように形成されている
ことを特徴とする半導体装置の製造方法。 - (a)炭化珪素半導体の第1導電型の半導体層(2)の表層部に、第2導電型の不純物をイオン注入することによりウェル領域(20)を形成する工程と、
(b)前記ウェル領域(20)内の表層部に第1導電型の不純物をイオン注入することよりソース領域(12)を形成する工程と、
(c)前記ソース領域(12)および前記ウェル領域(20)を貫通して前記ウェル領域(20)の下の前記半導体層(2)に達するトレンチ(110)を形成する工程と、
(d)前記トレンチ(110)の側壁に露出した、前記ソース領域(12)、前記半導体層(2)、および当該ソース領域(12)と当該半導体層(2)との間の前記ウェル領域(20)の部分であるチャネル領域に跨がるように、前記トレンチ(110)の側壁にゲート絶縁膜(30)を介してゲート電極(35)を形成する工程と、
(e)前記ソース領域(12)に接続するソース電極(41)を形成する工程とを備え、
前記工程(b)は、
(b−1)前記ソース電極(41)に接続する前記ソース領域(12)の部分であるソースコンタクト領域(12a)を形成するイオン注入工程と、
(b−2)前記チャネル領域の上に接する前記ソース領域(12)の部分であるソースエクステンション領域(12b)を形成するイオン注入工程と、
(b−3)前記ソースエクステンション領域(12b)と前記ソースコンタクト領域(12a)とに挟まれた前記ソース領域(12)の部分であるソース抵抗制御領域(15a)を形成するイオン注入工程と、を含み、
前記工程(b−1)及び(b−2)は同時に行われ、
前記ソースコンタクト領域(12a)の外周のコーナー部および前記ソースエクステンション領域(12b)の内周のコーナー部はラウンド形状になっており、
前記チャネル領域のチャネル長は均一になっており、
前記ソース抵抗制御領域(15a)は、オン電流の流れる方向に均一な長さを持つように形成されている
ことを特徴とする半導体装置の製造方法。 - 前記工程(b)は、
(b−4)前記ソース抵抗制御領域(15a)の形成領域上に、前記工程(b−2)のイオン注入で不純物の一部が貫通する薄いマスク(101b)を形成する工程を含み、
前記工程(b−1)、(b−2)及び(b−3)は、前記工程(b−4)の後に同時に行われる
請求項7または請求項8記載の半導体装置の製造方法。 - 前記工程(b−4)で形成される前記マスク(101c)はテーパー形状である
請求項9記載の半導体装置の製造方法。 - 前記工程(b)は、
(b−4)前記ソース抵抗制御領域(15a)の形成領域上に、前記(b−1)及び(b−2)のイオン注入における前記半導体層(2)内での不純物の横方向の広がりの和よりも狭いマスク(100cN)を形成する工程を含み、
前記工程(b−3)は、前記マスク(100cN)を挟んで前記工程(b−1)及び(b−2)のイオン注入を行うことにより実施される
請求項7または請求項8記載の半導体装置の製造方法。 - 前記工程(b)は、
(b−4)前記ソースエクステンション領域(12b)および前記ソースコンタクト領域(12a)の形成領域が開口され、前記ソース抵抗制御領域(15a)の形成領域を覆う第1のマスク(100d,100dN)を形成する工程を含み、
前記工程(b−1)及び(b−2)のイオン注入は前記第1のマスク(100d,100dN)を用いて行われ、
前記工程(a)は、
(a−1)前記第1のマスク(100d,100dN)の側面を後退させることにより第2のマスク(100d)を形成する工程と、
(a−2)前記第2のマスク(100d)を用いたイオン注入により前記ウェル領域(20)を形成する工程とを含み、
前記工程(a−1)において、前記第1のマスク(100d,100dN)における前記ソース抵抗制御領域(15a)の形成領域を覆う部分(100dN)は除去される
請求項7または請求項8記載の半導体装置の製造方法。 - (a)炭化珪素半導体の第1導電型の半導体層(2)の表層部に、第2導電型のウェル領域(20)を形成する工程と、
(b)前記ウェル領域(20)内の表層部に、第1導電型のソース領域(12)を形成する工程と、
(c)前記ソース領域(12)および前記ウェル領域(20)を貫通して前記ウェル領域(20)の下の前記半導体層(2)に達するトレンチ(110)を形成する工程と、
(d)前記トレンチ(110)の側壁に露出した、前記ソース領域(12)、前記半導体層(2)、および当該ソース領域(12)と当該半導体層(2)との間の前記ウェル領域(20)の部分であるチャネル領域に跨がるように、前記トレンチ(110)の側壁にゲート絶縁膜(30)を介してゲート電極(35)を形成する工程と、
(e)前記ソース領域(12)に接続するソース電極(41)を形成する工程とを備え、
前記工程(b)は、
(b−1)前記チャネル領域の上に接する前記ソース領域(12)の部分であるソースエクステンション領域(12b)を形成する工程と、
(b−2)前記ソースエクステンション領域(12b)の上に接し、前記ソースエクステンション領域(12b)とは第1導電型の不純物濃度が異なるソース抵抗制御領域(15a)を形成する工程と、
(b−3)前記ソース抵抗制御領域(15a)の上に接し、前記ソース抵抗制御領域(15a)とは第1導電型の不純物濃度が異なり、前記ソース電極(41)に接続する前記ソース領域(12)の部分であるソースコンタクト領域(12a)を形成する工程と、を含み、
前記ソース抵抗制御領域(15a)は、オン電流の流れる方向に均一な長さを持つように形成されている
ことを特徴とする半導体装置の製造方法。
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